mirror of https://github.com/pevans/erc-c.git
507 lines
15 KiB
C
507 lines
15 KiB
C
/*
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* mos6502.c
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*
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* These functions are kind of the "top-level", if you will, for the MOS
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* 6502 processor. You can create the processor struct, operate on the
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* stack, etc.
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*/
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include "log.h"
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#include "mos6502/mos6502.h"
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#include "mos6502/dis.h"
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#include "vm_debug.h"
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// All of our address modes, instructions, etc. are defined here.
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#include "mos6502/enums.h"
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/*
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* This is a table which defines what instruction each opcode is mapped
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* to. All possible (256) values are defined here. You will note many
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* cases where we use NOP where opcodes are not _technically_ defined;
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* this may or may not be the best behavior. It's quite possible we should
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* instead crash the program when we stumble upon such malformed opcodes
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*/
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static int instructions[] = {
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// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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BRK, ORA, NP2, NOP, TSB, ORA, ASL, NOP, PHP, ORA, ASL, NOP, TSB, ORA, ASL, NOP, // 0x
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BPL, ORA, ORA, NOP, TRB, ORA, ASL, NOP, CLC, ORA, INC, NOP, TRB, ORA, ASL, NOP, // 1x
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JSR, AND, NP2, NOP, BIT, AND, ROL, NOP, PLP, AND, ROL, NOP, BIT, AND, ROL, NOP, // 2x
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BMI, AND, AND, NOP, BIT, AND, ROL, NOP, SEC, AND, DEC, NOP, BIT, AND, ROL, NOP, // 3x
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RTI, EOR, NP2, NOP, NP2, EOR, LSR, NOP, PHA, EOR, LSR, NOP, JMP, EOR, LSR, NOP, // 4x
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BVC, EOR, EOR, NOP, NP2, EOR, LSR, NOP, CLI, EOR, PHY, NOP, NP3, EOR, LSR, NOP, // 5x
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RTS, ADC, NP2, NOP, STZ, ADC, ROR, NOP, PLA, ADC, ROR, NOP, JMP, ADC, ROR, NOP, // 6x
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BVS, ADC, ADC, NOP, STZ, ADC, ROR, NOP, SEI, ADC, PLY, NOP, JMP, ADC, ROR, NOP, // 7x
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BRA, STA, NP2, NOP, STY, STA, STX, NOP, DEY, BIM, TXA, NOP, STY, STA, STX, NOP, // 8x
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BCC, STA, STA, NOP, STY, STA, STX, NOP, TYA, STA, TXS, NOP, STZ, STA, STZ, NOP, // 9x
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LDY, LDA, LDX, NOP, LDY, LDA, LDX, NOP, TAY, LDA, TAX, NOP, LDY, LDA, LDX, NOP, // Ax
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BCS, LDA, LDA, NOP, LDY, LDA, LDX, NOP, CLV, LDA, TSX, NOP, LDY, LDA, LDX, NOP, // Bx
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CPY, CMP, NP2, NOP, CPY, CMP, DEC, NOP, INY, CMP, DEX, NOP, CPY, CMP, DEC, NOP, // Cx
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BNE, CMP, CMP, NOP, NP2, CMP, DEC, NOP, CLD, CMP, PHX, NOP, NP3, CMP, DEC, NOP, // Dx
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CPX, SBC, NP2, NOP, CPX, SBC, INC, NOP, INX, SBC, NOP, NOP, CPX, SBC, INC, NOP, // Ex
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BEQ, SBC, SBC, NOP, NP2, SBC, INC, NOP, SED, SBC, PLX, NOP, NP3, SBC, INC, NOP, // Fx
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};
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/*
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* A small convenience for defining instruction handlers below.
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*/
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#define INST_HANDLER(x) \
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mos6502_handle_##x
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/*
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* Here's another table, this time mapping instruction codes to
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* instruction handler functions. They are listed in the order defined
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* in the instruction enum (in mos6502.enums.h).
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*/
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static mos6502_instruction_handler instruction_handlers[] = {
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INST_HANDLER(adc),
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INST_HANDLER(and),
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INST_HANDLER(asl),
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INST_HANDLER(bad),
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INST_HANDLER(bcc),
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INST_HANDLER(bcs),
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INST_HANDLER(beq),
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INST_HANDLER(bit),
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INST_HANDLER(bim),
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INST_HANDLER(bmi),
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INST_HANDLER(bne),
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INST_HANDLER(bpl),
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INST_HANDLER(bra),
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INST_HANDLER(brk),
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INST_HANDLER(bvc),
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INST_HANDLER(bvs),
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INST_HANDLER(clc),
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INST_HANDLER(cld),
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INST_HANDLER(cli),
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INST_HANDLER(clv),
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INST_HANDLER(cmp),
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INST_HANDLER(cpx),
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INST_HANDLER(cpy),
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INST_HANDLER(dec),
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INST_HANDLER(dex),
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INST_HANDLER(dey),
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INST_HANDLER(eor),
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INST_HANDLER(inc),
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INST_HANDLER(inx),
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INST_HANDLER(iny),
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INST_HANDLER(jmp),
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INST_HANDLER(jsr),
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INST_HANDLER(lda),
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INST_HANDLER(ldx),
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INST_HANDLER(ldy),
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INST_HANDLER(lsr),
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INST_HANDLER(nop),
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INST_HANDLER(np2),
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INST_HANDLER(np3),
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INST_HANDLER(ora),
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INST_HANDLER(pha),
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INST_HANDLER(php),
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INST_HANDLER(phx),
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INST_HANDLER(ply),
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INST_HANDLER(pla),
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INST_HANDLER(plp),
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INST_HANDLER(plx),
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INST_HANDLER(ply),
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INST_HANDLER(rol),
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INST_HANDLER(ror),
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INST_HANDLER(rti),
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INST_HANDLER(rts),
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INST_HANDLER(sbc),
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INST_HANDLER(sec),
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INST_HANDLER(sed),
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INST_HANDLER(sei),
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INST_HANDLER(sta),
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INST_HANDLER(stx),
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INST_HANDLER(sty),
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INST_HANDLER(stz),
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INST_HANDLER(tax),
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INST_HANDLER(tay),
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INST_HANDLER(trb),
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INST_HANDLER(tsb),
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INST_HANDLER(tsx),
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INST_HANDLER(txa),
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INST_HANDLER(txs),
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INST_HANDLER(tya),
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};
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/*
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* Here we have a table that maps opcodes to the number of cycles each
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* should cost. In cases where no opcode is defined, we set the number
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* of cycles to zero.
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*/
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static int cycles[] = {
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// 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
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7, 6, 2, 1, 5, 3, 5, 1, 3, 2, 2, 1, 6, 4, 6, 1, // 0x
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2, 5, 5, 1, 5, 4, 6, 1, 2, 4, 2, 1, 6, 4, 6, 1, // 1x
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6, 6, 2, 1, 3, 3, 5, 1, 4, 2, 2, 1, 4, 4, 6, 1, // 2x
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2, 5, 5, 1, 4, 4, 6, 1, 2, 4, 2, 1, 4, 4, 6, 1, // 3x
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6, 6, 2, 1, 3, 3, 5, 1, 3, 2, 2, 1, 3, 4, 6, 1, // 4x
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2, 5, 5, 1, 4, 4, 6, 1, 2, 4, 3, 1, 8, 4, 6, 1, // 5x
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6, 6, 2, 1, 3, 3, 5, 1, 4, 2, 2, 1, 5, 4, 6, 1, // 6x
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2, 5, 5, 1, 4, 4, 6, 1, 2, 4, 4, 1, 6, 4, 6, 1, // 7x
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3, 6, 2, 1, 3, 3, 3, 1, 2, 2, 2, 1, 4, 4, 4, 1, // 8x
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2, 6, 5, 1, 4, 4, 4, 1, 2, 5, 2, 1, 4, 5, 5, 1, // 9x
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2, 6, 2, 1, 3, 3, 3, 1, 2, 2, 2, 1, 4, 4, 4, 1, // Ax
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2, 5, 5, 1, 4, 4, 4, 1, 2, 4, 2, 1, 4, 4, 4, 1, // Bx
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2, 6, 2, 1, 3, 3, 5, 1, 2, 2, 2, 1, 4, 4, 3, 1, // Cx
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2, 5, 5, 1, 4, 4, 6, 1, 2, 4, 3, 1, 4, 4, 7, 1, // Dx
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2, 6, 2, 1, 3, 3, 5, 1, 2, 2, 2, 1, 4, 4, 6, 1, // Ex
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2, 5, 5, 1, 4, 4, 6, 1, 2, 4, 4, 1, 4, 4, 7, 1, // Fx
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};
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/*
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* Build a new mos6502 struct object, and also build the memory contents
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* used therein. All registers should be zeroed out.
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*/
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mos6502 *
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mos6502_create(vm_segment *rmem, vm_segment *wmem)
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{
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mos6502 *cpu;
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cpu = malloc(sizeof(mos6502));
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if (cpu == NULL) {
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log_crit("Not enough memory to allocate mos6502");
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exit(1);
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}
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mos6502_set_memory(cpu, rmem, wmem);
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cpu->eff_addr = 0;
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cpu->PC = 0;
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cpu->A = 0;
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cpu->X = 0;
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cpu->Y = 0;
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cpu->P = MOS_STATUS_DEFAULT;
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cpu->S = 0xff;
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return cpu;
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}
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/*
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* Free the memory consumed by the mos6502 struct.
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*/
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void
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mos6502_free(mos6502 *cpu)
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{
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// Note we do not free rmem or wmem; we consider this to be the
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// responsibility of the caller that passed us those values.
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free(cpu);
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}
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/*
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* Push a _16-bit_ number to the stack. Generally speaking, only
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* addresses are pushed to the stack, such that would be contained in
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* the PC register (which is 16-bit).
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*
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* The stack is contained within a single page of memory, so you would
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* be right in observing that the stack can contain at most 128, not
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* 256, addresses.
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*/
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void
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mos6502_push_stack(mos6502 *cpu, vm_8bit addr)
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{
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mos6502_set(cpu, 0x100 + cpu->S, addr);
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// And finally we need to increment S by 2 (since we've used two
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// bytes in the stack).
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cpu->S--;
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}
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/*
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* Pop an address from the stack and return that.
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*/
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vm_8bit
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mos6502_pop_stack(mos6502 *cpu)
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{
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// The first thing we want to do here is to decrement S by 2, since
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// the value we want to return is two positions back.
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cpu->S++;
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// We need to use a bitwise-or operation to combine the hi and lo
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// bytes we retrieve from the stack into the actual position we
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// would use for the PC register.
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return mos6502_get(cpu, 0x0100 + cpu->S);
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}
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/*
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* Here we set the status register to a given status value, regardless
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* of its past contents.
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*/
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void
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mos6502_set_status(mos6502 *cpu, vm_8bit status)
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{
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cpu->P = status;
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}
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/*
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* Return the instruction that is mapped to a given opcode.
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*/
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int
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mos6502_instruction(vm_8bit opcode)
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{
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return instructions[opcode];
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}
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/*
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* Return the number of cycles an opcode may consume. The cpu is a
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* required parameter, because the number of opcodes is conditional upon
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* the effective address of the instruction we're executing.
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*/
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int
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mos6502_cycles(mos6502 *cpu, vm_8bit opcode)
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{
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// In some contexts, we may need to return an additional cycle.
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int modif = 0;
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int addr_mode;
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int lo_addr;
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addr_mode = mos6502_addr_mode(opcode);
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// Mainly we care about the lo byte of the last effective address
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lo_addr = cpu->eff_addr & 0xFF;
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// Ok, here's the deal: if you are using an address mode that uses
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// any of the index registers, you need to return an additional
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// cycle if the lo byte of the address plus that index would cross a
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// memory page boundary
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switch (addr_mode) {
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case ABX:
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if (lo_addr + cpu->X > 255) {
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modif = 1;
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}
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break;
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case ABY:
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case INY:
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if (lo_addr + cpu->Y > 255) {
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modif = 1;
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}
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break;
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default:
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break;
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}
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return cycles[opcode] + modif;
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}
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/*
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* Here we intend to return the proper resolver function for any given
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* instruction.
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*/
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mos6502_instruction_handler
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mos6502_get_instruction_handler(vm_8bit opcode)
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{
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return instruction_handlers[mos6502_instruction(opcode)];
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}
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/*
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* This code does the execution step that the 6502 processor would take,
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* from soup to nuts.
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*/
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void
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mos6502_execute(mos6502 *cpu)
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{
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vm_8bit opcode, operand = 0;
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int /*cycles,*/ bytes;
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mos6502_address_resolver resolver;
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mos6502_instruction_handler handler;
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// We shouldn't normally get here, if there was a breakpoint, but we
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// will in testing.
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if (vm_debug_broke(cpu->PC)) {
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return;
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}
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opcode = mos6502_get(cpu, cpu->PC);
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// The disassembler knows how many bytes each operand requires
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// (maybe this code doesn't belong in the disassembler); let's use
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// that to figure out the total number of bytes to skip. We add 1
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// because we need to account for the opcode as well.
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bytes = 1 + mos6502_dis_expected_bytes(mos6502_addr_mode(opcode));
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// First, we need to know how to resolve our effective address and
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// how to execute anything.
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resolver = mos6502_get_address_resolver(mos6502_addr_mode(opcode));
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handler = mos6502_get_instruction_handler(opcode);
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// The operand is the effective operand, the value that the
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// instruction handler cares about (if it cares about any such
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// value). For example, the operand could be the literal value that
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// you pass into an instruction via immediate mode. As a
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// side-effect, resolver will set the eff_addr field in cpu to the
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// effective address where the operand can be found in memory, or
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// zero if that does not apply (such as in immediate mode).
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//
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// Note also that resolver may be NULL, as there may not be any
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// operand for this instruction! If so, we let the default for
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// operand stand, which is zero.
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if (resolver) {
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operand = resolver(cpu);
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}
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// Here's where the magic happens. Whatever the instruction does, it
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// happens in the handler function.
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handler(cpu, operand);
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// This will be the number of cycles we should spend on the
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// instruction. Of course, we can execute instructions pretty
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// quickly in a modern architecture, but a lot of code was written
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// with the idea that certain instructions -- in certain address
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// modes -- were more expensive than others, and you want those
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// programs to feel faster or slower in relation to that.
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//cycles = mos6502_cycles(cpu, opcode);
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// If we need to jump, then the handler has to take care of updating
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// PC. If not, then we need to do it.
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if (!mos6502_would_jump(mos6502_instruction(opcode))) {
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cpu->PC += bytes;
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}
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// FIXME: uh this probably isn't right, but I wanted to do
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// something.
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//usleep(cycles);
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// We need to record the opcode and the effective address for
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// anything which might need to reference it.
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cpu->last_opcode = opcode;
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cpu->last_addr = cpu->eff_addr;
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cpu->last_operand = operand;
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// Ok -- we're done! This wasn't so hard, was it?
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return;
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}
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/*
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* Given pointers for an opcode, operand, and effective address, set the
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* dereferenced values of those pointers to what the CPU knows to have
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* been the last of each.
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*/
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void
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mos6502_last_executed(mos6502 *cpu, vm_8bit *opcode,
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vm_8bit *operand, vm_16bit *addr)
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{
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if (opcode) {
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*opcode = cpu->last_opcode;
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}
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if (operand) {
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*operand = cpu->last_operand;
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}
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if (addr) {
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*addr = cpu->last_addr;
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}
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}
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/*
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* Return true if the given instruction would require that we jump
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* to somewhere else in the program.
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*/
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inline bool
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mos6502_would_jump(int inst_code)
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{
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return
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inst_code == BCC ||
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inst_code == BCS ||
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inst_code == BEQ ||
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inst_code == BMI ||
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inst_code == BNE ||
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inst_code == BPL ||
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inst_code == BRK ||
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inst_code == BVC ||
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inst_code == BVS ||
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inst_code == JMP ||
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inst_code == JSR ||
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inst_code == NP2 || // this is KIND of a hack, but it works!
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inst_code == NP3 || // these jump ahead by 2 or 3 bytes (respectively)
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inst_code == RTS ||
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inst_code == RTI;
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}
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/*
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* This is a _kind_ of factory method, except we're obviously not
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* instantiating an object. Given an address mode, we return the
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* resolver function which will give you the right value (for a given
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* cpu) that an instruction will use.
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*/
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mos6502_address_resolver
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mos6502_get_address_resolver(int addr_mode)
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{
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switch (addr_mode) {
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case ACC: return mos6502_resolve_acc;
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case ABS: return mos6502_resolve_abs;
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case ABX: return mos6502_resolve_abx;
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case ABY: return mos6502_resolve_aby;
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case IMM: return mos6502_resolve_imm;
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case IND: return mos6502_resolve_ind;
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case IDX: return mos6502_resolve_idx;
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case IDY: return mos6502_resolve_idy;
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case REL: return mos6502_resolve_rel;
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case ZPG: return mos6502_resolve_zpg;
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case ZPX: return mos6502_resolve_zpx;
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case ZPY: return mos6502_resolve_zpy;
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case IMP: // FALLTHRU
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default: break;
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}
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return NULL;
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}
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/*
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* Get the byte at a given address from whatever the read memory segment
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* is.
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*/
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inline vm_8bit
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mos6502_get(mos6502 *cpu, size_t addr)
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|
{
|
|
return vm_segment_get(cpu->rmem, addr);
|
|
}
|
|
|
|
/*
|
|
* Return the 16-bit value from a given address using the read memory
|
|
* segment.
|
|
*/
|
|
inline vm_16bit
|
|
mos6502_get16(mos6502 *cpu, size_t addr)
|
|
{
|
|
return vm_segment_get16(cpu->rmem, addr);
|
|
}
|
|
|
|
/*
|
|
* Set the byte at a given address to the given value, using whatever
|
|
* the write segment is.
|
|
*/
|
|
inline void
|
|
mos6502_set(mos6502 *cpu, size_t addr, vm_8bit value)
|
|
{
|
|
vm_segment_set(cpu->wmem, addr, value);
|
|
}
|
|
|
|
/*
|
|
* Set the two bytes at a given address to the given value, using the
|
|
* write segment.
|
|
*/
|
|
inline void
|
|
mos6502_set16(mos6502 *cpu, size_t addr, vm_16bit value)
|
|
{
|
|
vm_segment_set16(cpu->wmem, addr, value);
|
|
}
|
|
|
|
/*
|
|
* Given a read and write memory segment, update the CPU to use those
|
|
* implicitly when handling the mos6502_set/get functions.
|
|
*/
|
|
void
|
|
mos6502_set_memory(mos6502 *cpu, vm_segment *rmem, vm_segment *wmem)
|
|
{
|
|
cpu->rmem = rmem;
|
|
cpu->wmem = wmem;
|
|
}
|