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First implementation done, with basic tests and commenting.
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Zellyn Hunter
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9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
<program> Copyright (C) <year> <name of author>
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
|
||||
75
asm/disasm.go
Normal file
75
asm/disasm.go
Normal file
@ -0,0 +1,75 @@
|
||||
/*
|
||||
Package asm provides routines for decomiling 6502 assembly language.
|
||||
*/
|
||||
package asm
|
||||
|
||||
import (
|
||||
"fmt"
|
||||
|
||||
"github.com/zellyn/go6502/cpu"
|
||||
)
|
||||
|
||||
// bytesString takes three bytes and a length, returning the formatted
|
||||
// hex bytes for an instrction of the given length.
|
||||
func bytesString(byte0, byte1, byte2 byte, length int) string {
|
||||
switch length {
|
||||
case 1:
|
||||
return fmt.Sprintf("%02X ", byte0)
|
||||
case 2:
|
||||
return fmt.Sprintf("%02X %02X ", byte0, byte1)
|
||||
case 3:
|
||||
return fmt.Sprintf("%02X %02X %02X", byte0, byte1, byte2)
|
||||
}
|
||||
panic("Length must be 1, 2, or 3")
|
||||
}
|
||||
|
||||
// addrString returns the address part of a 6502 assembly language
|
||||
// instruction.
|
||||
func addrString(pc uint16, byte1, byte2 byte, length int, mode int) string {
|
||||
addr16 := uint16(byte1) + uint16(byte2)<<8
|
||||
addrRel := uint16(int32(pc+2) + int32(int8(byte1)))
|
||||
switch mode {
|
||||
case cpu.MODE_IMPLIED:
|
||||
return " "
|
||||
case cpu.MODE_ABSOLUTE:
|
||||
return fmt.Sprintf("$%04X ", addr16)
|
||||
case cpu.MODE_INDIRECT:
|
||||
return fmt.Sprintf("($%04X)", addr16)
|
||||
case cpu.MODE_RELATIVE:
|
||||
return fmt.Sprintf("$%04X ", addrRel)
|
||||
case cpu.MODE_IMMEDIATE:
|
||||
return fmt.Sprintf("#$%02X ", byte1)
|
||||
case cpu.MODE_ABS_X:
|
||||
return fmt.Sprintf("$%04X,X", addr16)
|
||||
case cpu.MODE_ABS_Y:
|
||||
return fmt.Sprintf("$%04X,Y", addr16)
|
||||
case cpu.MODE_ZP:
|
||||
return fmt.Sprintf("$%02X ", byte1)
|
||||
case cpu.MODE_ZP_X:
|
||||
return fmt.Sprintf("$%02X,X ", byte1)
|
||||
case cpu.MODE_ZP_Y:
|
||||
return fmt.Sprintf("$%02X,Y ", byte1)
|
||||
case cpu.MODE_INDIRECT_Y:
|
||||
return fmt.Sprintf("($%02X,X) ", byte1)
|
||||
case cpu.MODE_INDIRECT_X:
|
||||
return fmt.Sprintf("($%02X),Y ", byte1)
|
||||
case cpu.MODE_A:
|
||||
return " "
|
||||
}
|
||||
panic(fmt.Sprintf("Unknown op mode: %d", mode))
|
||||
}
|
||||
|
||||
// Disasm disassembles a single (up to three byte) 6502
|
||||
// instruction. It returns the formatted bytes, the formatted
|
||||
// instruction and address, and the length. If it cannot find the
|
||||
// instruction, it returns a 1-byte "???" instruction.
|
||||
func Disasm(pc uint16, byte0, byte1, byte2 byte) (string, string, int) {
|
||||
op, ok := cpu.Opcodes[byte0]
|
||||
if !ok {
|
||||
op = cpu.NoOp
|
||||
}
|
||||
length := cpu.ModeLengths[op.Mode]
|
||||
bytes := bytesString(byte0, byte1, byte2, length)
|
||||
addr := addrString(pc, byte1, byte2, length, op.Mode)
|
||||
return bytes, op.Name + " " + addr, length
|
||||
}
|
||||
40
cpu/cpu.go
40
cpu/cpu.go
@ -3,6 +3,7 @@
|
||||
|
||||
TODO(zellyn): Provide configurable options
|
||||
TODO(zellyn): Implement IRQ, NMI
|
||||
TODO(zellyn): Does BRK on 65C02 CLD?
|
||||
*/
|
||||
|
||||
package cpu
|
||||
@ -11,18 +12,10 @@ import (
|
||||
"fmt"
|
||||
)
|
||||
|
||||
/* Bugs and Quirks.
|
||||
See http://en.wikipedia.org/wiki/MOS_Technology_6502#Bugs_and_quirks
|
||||
*/
|
||||
// See http://en.wikipedia.org/wiki/MOS_Technology_6502#Bugs_and_quirks
|
||||
const (
|
||||
// TODO(zellyn) implement
|
||||
// JMP xxFF reads xx00 instead of (xx+1)00
|
||||
OPTION_BUG_JMP_FF = true
|
||||
OPTION_BUG_INDEXED_ADDR_ACROSS_PAGE_INVALID_READ = true
|
||||
OPTION_BUG_READ_MODIFY_WRITE_TWO_WRITES = true
|
||||
OPTION_BUG_NVZ_INVALID_IN_BCD = true
|
||||
OPTION_BUG_NO_CLD_ON_INTERRUPT = true
|
||||
OPTION_BUG_INTERRUPTS_CLOBBER_BRK = true
|
||||
VERSION_6502 = iota
|
||||
VERSION_65C02
|
||||
)
|
||||
|
||||
type Cpu interface {
|
||||
@ -63,6 +56,7 @@ const (
|
||||
FLAG_UNUSED
|
||||
FLAG_V
|
||||
FLAG_N
|
||||
FLAG_NV = FLAG_N | FLAG_V
|
||||
)
|
||||
|
||||
type registers struct {
|
||||
@ -75,13 +69,15 @@ type registers struct {
|
||||
}
|
||||
|
||||
type cpu struct {
|
||||
m Memory
|
||||
t Ticker
|
||||
r registers
|
||||
m Memory
|
||||
t Ticker
|
||||
r registers
|
||||
oldPC uint16
|
||||
version int
|
||||
}
|
||||
|
||||
func NewCPU(memory Memory, ticker Ticker) Cpu {
|
||||
c := cpu{m: memory, t: ticker}
|
||||
func NewCPU(memory Memory, ticker Ticker, version int) Cpu {
|
||||
c := cpu{m: memory, t: ticker, version: version}
|
||||
c.r.P |= FLAG_UNUSED // Set unused flag to 1
|
||||
return &c
|
||||
}
|
||||
@ -113,18 +109,24 @@ func (c *cpu) Reset() {
|
||||
c.r.SP = 0
|
||||
c.r.PC = c.readWord(RESET_VECTOR)
|
||||
c.r.P |= FLAG_I // Turn interrupts off
|
||||
if !OPTION_BUG_NO_CLD_ON_INTERRUPT {
|
||||
switch c.version {
|
||||
case VERSION_6502:
|
||||
// 6502 doesn't CLD on interrupt
|
||||
c.r.P &^= FLAG_D
|
||||
case VERSION_65C02:
|
||||
default:
|
||||
panic("Unknown chip version")
|
||||
}
|
||||
}
|
||||
|
||||
func (c *cpu) Step() error {
|
||||
c.oldPC = c.r.PC
|
||||
i := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
|
||||
if f, ok := opcodes[i]; ok {
|
||||
f(c)
|
||||
if op, ok := Opcodes[i]; ok {
|
||||
op.function(c)
|
||||
return nil
|
||||
}
|
||||
|
||||
|
||||
11
cpu/doc.go
Normal file
11
cpu/doc.go
Normal file
@ -0,0 +1,11 @@
|
||||
/*
|
||||
|
||||
Package cpu provides routines for emulating a 6502 or 65C02. It also
|
||||
provides data about opcodes that is used by the asm package to
|
||||
(dis)assemble 6502 assembly language.
|
||||
|
||||
BUG(zellyn): 6502 should do invalid reads when doing indexed addressing across page boundaries. See http://en.wikipedia.org/wiki/MOS_Technology_6502#Bugs_and_quirks.
|
||||
BUG(zellyn): rmw instructions should write old data back on 6502, read twice on 65C02. See http://en.wikipedia.org/wiki/MOS_Technology_6502#Bugs_and_quirks.
|
||||
BUG(zellyn): implement interrupts, and 6502/65C02 decimal-mode-clearing and BRK-skipping quirks.
|
||||
*/
|
||||
package cpu
|
||||
520
cpu/opcodeinstructions.go
Normal file
520
cpu/opcodeinstructions.go
Normal file
@ -0,0 +1,520 @@
|
||||
package cpu
|
||||
|
||||
// Helpers and instruction-builders
|
||||
|
||||
// samePage is a helper that returns true if two memory addresses
|
||||
// refer to the same page.
|
||||
func samePage(a1 uint16, a2 uint16) bool {
|
||||
return a1^a2&0xFF00 == 0
|
||||
}
|
||||
|
||||
// clearFlag builds instructions that clear the flag specified by the
|
||||
// given mask.
|
||||
func clearFlag(flag byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
c.r.P &^= flag
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// setFlag builds instructions that set the flag specified by the
|
||||
// given mask.
|
||||
func setFlag(flag byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
c.r.P |= flag
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// branch builds instructions that perform branches if the status
|
||||
// register masks to a given value.
|
||||
func branch(mask, value byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
offset := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
oldPC := c.r.PC
|
||||
if c.r.P&mask == value {
|
||||
c.t.Tick()
|
||||
c.r.PC = c.r.PC + uint16(offset)
|
||||
if offset >= 128 {
|
||||
c.r.PC = c.r.PC - 256
|
||||
}
|
||||
if !samePage(c.r.PC, oldPC) {
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Individual opcodes
|
||||
|
||||
func adc(c *cpu, value byte) {
|
||||
if c.r.P&FLAG_D > 0 {
|
||||
adc_d(c, value)
|
||||
return
|
||||
}
|
||||
result16 := uint16(c.r.A) + uint16(value) + uint16(c.r.P&FLAG_C)
|
||||
result := byte(result16)
|
||||
c.r.P &^= (FLAG_C | FLAG_V)
|
||||
c.r.P |= uint8(result16 >> 8)
|
||||
if (c.r.A^result)&(value^result)&0x80 > 0 {
|
||||
c.r.P |= FLAG_V
|
||||
}
|
||||
c.r.A = result
|
||||
c.SetNZ(result)
|
||||
}
|
||||
|
||||
// adc_d performs decimal-mode add-with-carry.
|
||||
func adc_d(c *cpu, value byte) {
|
||||
// See http://www.6502.org/tutorials/decimal_mode.html#A
|
||||
|
||||
// fmt.Printf("adc_d: $%04X: A=$%02X value=$%02X carry=%d\n",
|
||||
// c.oldPC, c.r.A, value, c.r.P & FLAG_C)
|
||||
|
||||
bin := c.r.A + value + (c.r.P & FLAG_C)
|
||||
al := (c.r.A & 0x0F) + (value & 0x0F) + (c.r.P & FLAG_C)
|
||||
if al >= 0x0A {
|
||||
al = ((al + 0x06) & 0x0F) + 0x10
|
||||
}
|
||||
// fmt.Printf(" al=$%04X\n", al)
|
||||
a := uint16(c.r.A&0xF0) + uint16(value&0xF0) + uint16(al)
|
||||
if a >= 0xA0 {
|
||||
a += 0x60
|
||||
}
|
||||
// fmt.Printf(" a=$%04X\n", a)
|
||||
a_nv := int16(int8(c.r.A&0xF0)) + int16(int8(value&0xF0)) + int16(int8(al))
|
||||
c.r.P &^= (FLAG_V | FLAG_N | FLAG_Z)
|
||||
if byte(a_nv&0xFF)&FLAG_N > 0 {
|
||||
c.r.P |= FLAG_N
|
||||
}
|
||||
if a_nv < -128 || a_nv > 127 {
|
||||
c.r.P |= FLAG_V
|
||||
}
|
||||
c.r.A = byte(a & 0xFF)
|
||||
// fmt.Printf(" A=$%02X\n", c.r.A)
|
||||
c.r.P &^= FLAG_C
|
||||
if a >= 0x100 {
|
||||
c.r.P |= FLAG_C
|
||||
}
|
||||
|
||||
switch c.version {
|
||||
case VERSION_6502:
|
||||
if bin == 0 {
|
||||
c.r.P |= FLAG_Z
|
||||
}
|
||||
case VERSION_65C02:
|
||||
c.t.Tick()
|
||||
c.SetNZ(byte(a & 0xFF))
|
||||
default:
|
||||
panic("Unknown chip version")
|
||||
}
|
||||
}
|
||||
|
||||
func and(c *cpu, value byte) {
|
||||
c.r.A &= value
|
||||
c.SetNZ(c.r.A)
|
||||
}
|
||||
|
||||
func asl(c *cpu, value byte) byte {
|
||||
result := value << 1
|
||||
c.r.P = (c.r.P &^ FLAG_C) | (value >> 7)
|
||||
c.SetNZ(result)
|
||||
return result
|
||||
}
|
||||
|
||||
func bit(c *cpu, value byte) {
|
||||
if t := c.r.A & value; t == 0 {
|
||||
c.r.P |= FLAG_Z
|
||||
} else {
|
||||
c.r.P &^= FLAG_Z
|
||||
}
|
||||
c.r.P = (c.r.P &^ FLAG_NV) | (value & FLAG_NV)
|
||||
}
|
||||
|
||||
// Note that BRK skips the next instruction:
|
||||
// http://en.wikipedia.org/wiki/Interrupts_in_65xx_processors#Using_BRK_and_COP
|
||||
func brk(c *cpu) {
|
||||
// T1
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.m.Write(0x100+uint16(c.r.SP), byte(c.r.PC>>8))
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.m.Write(0x100+uint16(c.r.SP), byte(c.r.PC&0xff))
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(0x100+uint16(c.r.SP), c.r.P|FLAG_B) // Set B flag
|
||||
c.r.SP--
|
||||
c.r.P |= FLAG_I // Disable interrupts
|
||||
c.t.Tick()
|
||||
// T5
|
||||
addr := uint16(c.m.Read(IRQ_VECTOR))
|
||||
c.t.Tick()
|
||||
// T6
|
||||
addr |= (uint16(c.m.Read(IRQ_VECTOR+1)) << 8)
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func cmp(c *cpu, value byte) {
|
||||
v := c.r.A - value
|
||||
c.r.P &^= FLAG_C
|
||||
if c.r.A >= value {
|
||||
c.r.P |= FLAG_C
|
||||
}
|
||||
c.SetNZ(v)
|
||||
}
|
||||
|
||||
func cpx(c *cpu, value byte) {
|
||||
v := c.r.X - value
|
||||
c.r.P &^= FLAG_C
|
||||
if c.r.X >= value {
|
||||
c.r.P |= FLAG_C
|
||||
}
|
||||
c.SetNZ(v)
|
||||
}
|
||||
|
||||
func cpy(c *cpu, value byte) {
|
||||
v := c.r.Y - value
|
||||
c.r.P &^= FLAG_C
|
||||
if c.r.Y >= value {
|
||||
c.r.P |= FLAG_C
|
||||
}
|
||||
c.SetNZ(v)
|
||||
}
|
||||
|
||||
func dec(c *cpu, value byte) byte {
|
||||
result := value - 1
|
||||
c.SetNZ(result)
|
||||
return result
|
||||
}
|
||||
|
||||
func dex(c *cpu) {
|
||||
c.r.X--
|
||||
c.SetNZ(c.r.X)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func dey(c *cpu) {
|
||||
c.r.Y--
|
||||
c.SetNZ(c.r.Y)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func eor(c *cpu, value byte) {
|
||||
c.r.A ^= value
|
||||
c.SetNZ(c.r.A)
|
||||
}
|
||||
|
||||
func inc(c *cpu, value byte) byte {
|
||||
result := value + 1
|
||||
c.SetNZ(result)
|
||||
return result
|
||||
}
|
||||
|
||||
func inx(c *cpu) {
|
||||
c.r.X++
|
||||
c.SetNZ(c.r.X)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func iny(c *cpu) {
|
||||
c.r.Y++
|
||||
c.SetNZ(c.r.Y)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func jmpAbsolute(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func jmpIndirect(c *cpu) {
|
||||
// T1
|
||||
iAddr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
iAddr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr := uint16(c.m.Read(iAddr))
|
||||
c.t.Tick()
|
||||
// T4
|
||||
// 6502 jumps to (xxFF,xx00) instead of (xxFF,xxFF+1).
|
||||
// See http://en.wikipedia.org/wiki/MOS_Technology_6502#Bugs_and_quirks
|
||||
switch c.version {
|
||||
case VERSION_6502:
|
||||
if iAddr&0xff == 0xff {
|
||||
addr |= (uint16(c.m.Read(iAddr&0xff00)) << 8)
|
||||
} else {
|
||||
addr |= (uint16(c.m.Read(iAddr+1)) << 8)
|
||||
}
|
||||
case VERSION_65C02:
|
||||
addr |= (uint16(c.m.Read(iAddr+1)) << 8)
|
||||
default:
|
||||
panic("Unknown chip version")
|
||||
}
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func jsr(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC)) // We actually push PC(next) - 1
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.m.Write(0x100+uint16(c.r.SP), byte(c.r.PC>>8))
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(0x100+uint16(c.r.SP), byte(c.r.PC&0xff))
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T5
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func lda(c *cpu, value byte) {
|
||||
c.r.A = value
|
||||
c.SetNZ(value)
|
||||
}
|
||||
|
||||
func ldx(c *cpu, value byte) {
|
||||
c.r.X = value
|
||||
c.SetNZ(value)
|
||||
}
|
||||
|
||||
func ldy(c *cpu, value byte) {
|
||||
c.r.Y = value
|
||||
c.SetNZ(value)
|
||||
}
|
||||
|
||||
func lsr(c *cpu, value byte) byte {
|
||||
result := (value >> 1)
|
||||
c.r.P = (c.r.P &^ FLAG_C) | (value & FLAG_C)
|
||||
c.SetNZ(result)
|
||||
return result
|
||||
}
|
||||
|
||||
func ora(c *cpu, value byte) {
|
||||
c.r.A |= value
|
||||
c.SetNZ(c.r.A)
|
||||
}
|
||||
|
||||
func nop(c *cpu) {
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func pha(c *cpu) {
|
||||
c.t.Tick()
|
||||
c.m.Write(0x100+uint16(c.r.SP), c.r.A)
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func pla(c *cpu) {
|
||||
c.t.Tick()
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
c.r.A = c.m.Read(0x100 + uint16(c.r.SP))
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func php(c *cpu) {
|
||||
c.t.Tick()
|
||||
c.m.Write(0x100+uint16(c.r.SP), c.r.P)
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
}
|
||||
func plp(c *cpu) {
|
||||
c.t.Tick()
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
c.r.P = c.m.Read(0x100+uint16(c.r.SP)) | FLAG_UNUSED | FLAG_B
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func rol(c *cpu, value byte) byte {
|
||||
result := value<<1 | (c.r.P & FLAG_C)
|
||||
c.r.P = (c.r.P &^ FLAG_C) | (value >> 7)
|
||||
c.SetNZ(result)
|
||||
return result
|
||||
}
|
||||
|
||||
func ror(c *cpu, value byte) byte {
|
||||
result := (value >> 1) | (c.r.P << 7)
|
||||
c.r.P = (c.r.P &^ FLAG_C) | (value & FLAG_C)
|
||||
c.SetNZ(result)
|
||||
return result
|
||||
}
|
||||
|
||||
func rts(c *cpu) {
|
||||
// T1
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr := uint16(c.m.Read(0x100 + uint16(c.r.SP)))
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
// T4
|
||||
addr |= (uint16(c.m.Read(0x100+uint16(c.r.SP))) << 8)
|
||||
c.t.Tick()
|
||||
// T5
|
||||
c.r.PC = addr + 1 // Since we pushed PC(next) - 1
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func rti(c *cpu) {
|
||||
// T1
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.r.P = c.m.Read(0x100+uint16(c.r.SP)) | FLAG_UNUSED
|
||||
c.r.SP++
|
||||
// T4
|
||||
addr := uint16(c.m.Read(0x100 + uint16(c.r.SP)))
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
// T5
|
||||
addr |= (uint16(c.m.Read(0x100+uint16(c.r.SP))) << 8)
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func sbc(c *cpu, value byte) {
|
||||
if c.r.P&FLAG_D > 0 {
|
||||
sbc_d(c, value)
|
||||
return
|
||||
} else {
|
||||
c.r.A = sbc_bin(c, value)
|
||||
}
|
||||
}
|
||||
|
||||
// sbc_bin performs binary-mode subtract with carry. Broken out into a
|
||||
// separate routine so sbc_d can call it to determine flag values.
|
||||
func sbc_bin(c *cpu, value byte) byte {
|
||||
// Same as adc, except we take the ones complement of value
|
||||
value = ^value
|
||||
result16 := uint16(c.r.A) + uint16(value) + uint16(c.r.P&FLAG_C)
|
||||
result := byte(result16)
|
||||
c.r.P &^= (FLAG_C | FLAG_V)
|
||||
c.r.P |= uint8(result16 >> 8)
|
||||
if (c.r.A^result)&(value^result)&0x80 > 0 {
|
||||
c.r.P |= FLAG_V
|
||||
}
|
||||
c.SetNZ(result)
|
||||
return result
|
||||
}
|
||||
|
||||
// sdc_d performs decimal-mode subtract-with-carry.
|
||||
func sbc_d(c *cpu, value byte) {
|
||||
// See http://www.6502.org/tutorials/decimal_mode.html#A
|
||||
|
||||
carry := c.r.P & FLAG_C
|
||||
|
||||
// fmt.Printf("sbc_d: $%04X: A=$%02X value=$%02X carry=%d\n",
|
||||
// c.oldPC, c.r.A, value, carry)
|
||||
|
||||
// Compute normal sbc, and set all flags accordingly
|
||||
sbc_bin(c, value)
|
||||
|
||||
switch c.version {
|
||||
case VERSION_6502:
|
||||
al := int16(c.r.A&0x0F) - int16(value&0x0F) + int16(carry) - 1
|
||||
if al < 0 {
|
||||
al = ((al - 0x06) & 0x0F) - 0x10
|
||||
}
|
||||
// fmt.Printf(" al=$%04X\n", al)
|
||||
a := int16(c.r.A&0xF0) - int16(value&0xF0) + al
|
||||
if a < 0 {
|
||||
a = a - 0x60
|
||||
}
|
||||
// fmt.Printf(" a=$%04X\n", a)
|
||||
c.r.A = byte(a)
|
||||
case VERSION_65C02:
|
||||
al := int16(c.r.A&0x0F) - int16(value&0x0F) + int16(carry) - 1
|
||||
a := int16(c.r.A) - int16(value) + int16(carry) - 1
|
||||
// fmt.Printf(" al=$%04X\n", al)
|
||||
if a < 0 {
|
||||
a = a - 0x60
|
||||
}
|
||||
if al < 0 {
|
||||
a = a - 0x06
|
||||
}
|
||||
// fmt.Printf(" a=$%04X ($%02X)\n", a, byte(a))
|
||||
c.r.A = byte(a)
|
||||
c.t.Tick()
|
||||
c.SetNZ(c.r.A)
|
||||
default:
|
||||
panic("Unknown chip version")
|
||||
}
|
||||
}
|
||||
|
||||
func sta(c *cpu) byte {
|
||||
return c.r.A
|
||||
}
|
||||
|
||||
func stx(c *cpu) byte {
|
||||
return c.r.X
|
||||
}
|
||||
|
||||
func sty(c *cpu) byte {
|
||||
return c.r.Y
|
||||
}
|
||||
|
||||
func tax(c *cpu) {
|
||||
c.r.X = c.r.A
|
||||
c.SetNZ(c.r.X)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func tay(c *cpu) {
|
||||
c.r.Y = c.r.A
|
||||
c.SetNZ(c.r.Y)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func tsx(c *cpu) {
|
||||
c.r.X = c.r.SP
|
||||
c.SetNZ(c.r.X)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func txa(c *cpu) {
|
||||
c.r.A = c.r.X
|
||||
c.SetNZ(c.r.A)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func txs(c *cpu) {
|
||||
c.r.SP = c.r.X
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func tya(c *cpu) {
|
||||
c.r.A = c.r.Y
|
||||
c.SetNZ(c.r.A)
|
||||
c.t.Tick()
|
||||
}
|
||||
407
cpu/opcodemodes.go
Normal file
407
cpu/opcodemodes.go
Normal file
@ -0,0 +1,407 @@
|
||||
package cpu
|
||||
|
||||
// immediate2 performs 2-opcode, 2-cycle immediate mode instructions.
|
||||
func immediate2(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
value := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// absolute4r performs 3-opcode, 4-cycle absolute mode read instructions.
|
||||
func absolute4r(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
value := c.m.Read(addr)
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// absolute4w performs 3-opcode, 4-cycle absolute mode write instructions.
|
||||
func absolute4w(f func(*cpu) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.m.Write(addr, f(c))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zp3r performs 2-opcode, 3-cycle zero page read instructions.
|
||||
func zp3r(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
value := c.m.Read(addr)
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zp3w performs 2-opcode, 3-cycle zero page write instructions.
|
||||
func zp3w(f func(*cpu) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.m.Write(addr, f(c))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// absx4r performs 3-opcode, 4*-cycle abs,X read instructions.
|
||||
func absx4r(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
if !samePage(addr, addr+uint16(c.r.X)) {
|
||||
c.t.Tick()
|
||||
}
|
||||
// T3(cotd.) or T4
|
||||
value := c.m.Read(addr + uint16(c.r.X))
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// absy4r performs 3-opcode, 4*-cycle abs,Y read instructions.
|
||||
func absy4r(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
if !samePage(addr, addr+uint16(c.r.Y)) {
|
||||
c.t.Tick()
|
||||
}
|
||||
// T3(cotd.) or T4
|
||||
value := c.m.Read(addr + uint16(c.r.Y))
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// absx5w performs 3-opcode, 5-cycle abs,X write instructions.
|
||||
func absx5w(f func(*cpu) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(addr+uint16(c.r.X), f(c))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// absy5w performs 3-opcode, 5-cycle abs,Y write instructions.
|
||||
func absy5w(f func(*cpu) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(addr+uint16(c.r.Y), f(c))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpx4r performs 2-opcode, 4-cycle zp,X read instructions.
|
||||
func zpx4r(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr += c.r.X
|
||||
value := c.m.Read(uint16(addr))
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpx4w performs 2-opcode, 4-cycle zp,X write instructions.
|
||||
func zpx4w(f func(*cpu) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr += c.r.X
|
||||
c.m.Write(uint16(addr), f(c))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpy4r performs 2-opcode, 4-cycle zp,Y instructions.
|
||||
func zpy4r(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr += c.r.Y
|
||||
value := c.m.Read(uint16(addr))
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpy4w performs 2-opcode, 4-cycle zp,Y write instructions.
|
||||
func zpy4w(f func(*cpu) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr += c.r.Y
|
||||
c.m.Write(uint16(addr), f(c))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpiy5r performs 2-opcode, 5*-cycle zero-page indirect Y read instructions.
|
||||
func zpiy5r(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
iAddr := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr := uint16(uint16(c.m.Read(uint16(iAddr))))
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr |= (uint16(c.m.Read(uint16(iAddr+1))) << 8)
|
||||
c.t.Tick()
|
||||
// T4
|
||||
if !samePage(addr, addr+uint16(c.r.Y)) {
|
||||
c.t.Tick()
|
||||
}
|
||||
// T4(cotd.) or T5
|
||||
value := c.m.Read(addr + uint16(c.r.Y))
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpiy6w performs 2-opcode, 6-cycle zero-page indirect Y write instructions.
|
||||
func zpiy6w(f func(*cpu) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
iAddr := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr := uint16(uint16(c.m.Read(uint16(iAddr))))
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr |= (uint16(c.m.Read(uint16(iAddr+1))) << 8)
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.t.Tick()
|
||||
// T5
|
||||
c.m.Write(addr+uint16(c.r.Y), f(c))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpxi6r performs 2-opcode, 6-cycle zero-page X indirect read instructions.
|
||||
func zpxi6r(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
iAddr := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr := uint16(uint16(c.m.Read(uint16(iAddr + c.r.X))))
|
||||
c.t.Tick()
|
||||
// T4
|
||||
addr |= (uint16(c.m.Read(uint16(iAddr+c.r.X+1))) << 8)
|
||||
c.t.Tick()
|
||||
// T5
|
||||
value := c.m.Read(addr)
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpxi6w performs 2-opcode, 6-cycle zero-page X indirect write instructions.
|
||||
func zpxi6w(f func(*cpu) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
iAddr := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr := uint16(uint16(c.m.Read(uint16(iAddr + c.r.X))))
|
||||
c.t.Tick()
|
||||
// T4
|
||||
addr |= (uint16(c.m.Read(uint16(iAddr+c.r.X+1))) << 8)
|
||||
c.t.Tick()
|
||||
// T5
|
||||
c.m.Write(addr, f(c))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// acc2rmw performs 1-opcode, 2-cycle, accumulator rmw instructions.
|
||||
func acc2rmw(f func(*cpu, byte) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
c.r.A = f(c, c.r.A)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zp5rmw performs 2-opcode, 5-cycle, zp rmw instructions.
|
||||
func zp5rmw(f func(*cpu, byte) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
value := c.m.Read(addr)
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(addr, f(c, value))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// abs6rmw performs 3-opcode, 6-cycle, abs rmw instructions.
|
||||
func abs6rmw(f func(*cpu, byte) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
value := c.m.Read(addr)
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(addr, value) // Spurious write...
|
||||
c.t.Tick()
|
||||
// T5
|
||||
c.m.Write(addr, f(c, value))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// zpx6rmw performs 2-opcode, 6-cycle, zp,X rmw instructions.
|
||||
func zpx6rmw(f func(*cpu, byte) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr8 := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr := uint16(addr8 + c.r.X)
|
||||
value := c.m.Read(addr)
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(addr, value)
|
||||
c.t.Tick()
|
||||
// T5
|
||||
c.m.Write(addr, f(c, value))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
// absx7rmw performs 3-opcode, 7-cycle, abs,X rmw instructions.
|
||||
func absx7rmw(f func(*cpu, byte) byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T2
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.t.Tick()
|
||||
// T4
|
||||
value := c.m.Read(addr + uint16(c.r.X))
|
||||
c.t.Tick()
|
||||
// T5
|
||||
c.m.Write(addr+uint16(c.r.X), value) // Spurious write
|
||||
c.t.Tick()
|
||||
// T6
|
||||
c.m.Write(addr+uint16(c.r.X), f(c, value))
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
583
cpu/opcodes.go
583
cpu/opcodes.go
@ -4,363 +4,236 @@ import (
|
||||
_ "fmt"
|
||||
)
|
||||
|
||||
func samePage(a1 uint16, a2 uint16) bool {
|
||||
return a1^a2&0xFF00 == 0
|
||||
// Opcode addressing modes.
|
||||
const (
|
||||
MODE_IMPLIED = iota
|
||||
MODE_ABSOLUTE
|
||||
MODE_INDIRECT
|
||||
MODE_RELATIVE
|
||||
MODE_IMMEDIATE
|
||||
MODE_ABS_X
|
||||
MODE_ABS_Y
|
||||
MODE_ZP
|
||||
MODE_ZP_X
|
||||
MODE_ZP_Y
|
||||
MODE_INDIRECT_Y
|
||||
MODE_INDIRECT_X
|
||||
MODE_A
|
||||
)
|
||||
|
||||
// Lengths of instructions for each addressing mode.
|
||||
var ModeLengths = map[int]int{
|
||||
MODE_IMPLIED: 1,
|
||||
MODE_ABSOLUTE: 3,
|
||||
MODE_INDIRECT: 3,
|
||||
MODE_RELATIVE: 2,
|
||||
MODE_IMMEDIATE: 2,
|
||||
MODE_ABS_X: 3,
|
||||
MODE_ABS_Y: 3,
|
||||
MODE_ZP: 2,
|
||||
MODE_ZP_X: 2,
|
||||
MODE_ZP_Y: 2,
|
||||
MODE_INDIRECT_Y: 2,
|
||||
MODE_INDIRECT_X: 2,
|
||||
MODE_A: 1,
|
||||
}
|
||||
|
||||
// Simple, one-off instructions ----------------------------------------------
|
||||
|
||||
func clearFlag(flag byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
c.r.P &^= flag
|
||||
c.t.Tick()
|
||||
}
|
||||
// Opcode stores information about instructions.
|
||||
type Opcode struct {
|
||||
Name string
|
||||
Mode int
|
||||
function func(*cpu)
|
||||
}
|
||||
|
||||
func setFlag(flag byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
c.r.P |= flag
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
func dex(c *cpu) {
|
||||
c.r.X--
|
||||
c.SetNZ(c.r.X)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func dey(c *cpu) {
|
||||
c.r.Y--
|
||||
c.SetNZ(c.r.Y)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func inx(c *cpu) {
|
||||
c.r.X++
|
||||
c.SetNZ(c.r.X)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func iny(c *cpu) {
|
||||
c.r.Y++
|
||||
c.SetNZ(c.r.Y)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func pha(c *cpu) {
|
||||
c.t.Tick()
|
||||
c.m.Write(0x100+uint16(c.r.SP), c.r.A)
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func php(c *cpu) {
|
||||
c.t.Tick()
|
||||
c.m.Write(0x100+uint16(c.r.SP), c.r.P)
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
}
|
||||
func pla(c *cpu) {
|
||||
c.t.Tick()
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
c.r.A = c.m.Read(0x100 + uint16(c.r.SP))
|
||||
c.t.Tick()
|
||||
}
|
||||
func plp(c *cpu) {
|
||||
c.t.Tick()
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
c.r.P = c.m.Read(0x100 + uint16(c.r.SP))
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func nop(c *cpu) {
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func tax(c *cpu) {
|
||||
c.r.X = c.r.A
|
||||
c.SetNZ(c.r.X)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func tay(c *cpu) {
|
||||
c.r.Y = c.r.A
|
||||
c.SetNZ(c.r.Y)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func tsx(c *cpu) {
|
||||
c.r.X = c.r.SP
|
||||
c.SetNZ(c.r.X)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func txa(c *cpu) {
|
||||
c.r.A = c.r.X
|
||||
c.SetNZ(c.r.A)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func txs(c *cpu) {
|
||||
c.r.SP = c.r.X
|
||||
c.SetNZ(c.r.SP)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func tya(c *cpu) {
|
||||
c.r.A = c.r.Y
|
||||
c.SetNZ(c.r.A)
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func jmpAbsolute(c *cpu) {
|
||||
// T1
|
||||
c.r.PC++
|
||||
addr := uint16(c.m.Read(c.r.PC))
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.r.PC++
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func jmpIndirect(c *cpu) {
|
||||
// T1
|
||||
c.r.PC++
|
||||
iAddr := uint16(c.m.Read(c.r.PC))
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.r.PC++
|
||||
iAddr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr := uint16(c.m.Read(iAddr))
|
||||
c.t.Tick()
|
||||
// T4
|
||||
if (iAddr&0xff == 0xff) && OPTION_BUG_JMP_FF {
|
||||
addr |= (uint16(c.m.Read(iAddr&0xff00)) << 8)
|
||||
} else {
|
||||
addr |= (uint16(c.m.Read(iAddr+1)) << 8)
|
||||
}
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func jsr(c *cpu) {
|
||||
// T1
|
||||
c.r.PC++
|
||||
addr := uint16(c.m.Read(c.r.PC)) // We actually push PC(next) - 1
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.m.Write(0x100+uint16(c.r.SP), byte(c.r.PC>>8))
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(0x100+uint16(c.r.SP), byte(c.r.PC&0xff))
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T5
|
||||
addr |= (uint16(c.m.Read(c.r.PC)) << 8)
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func rts(c *cpu) {
|
||||
// T1
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
addr := uint16(c.m.Read(0x100 + uint16(c.r.SP)))
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
// T4
|
||||
addr |= (uint16(c.m.Read(0x100+uint16(c.r.SP))) << 8)
|
||||
c.t.Tick()
|
||||
// T5
|
||||
c.r.PC = addr + 1 // Since we pushed PC(next) - 1
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func rti(c *cpu) {
|
||||
// T1
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.r.P = c.m.Read(0x100 + uint16(c.r.SP))
|
||||
c.r.SP++
|
||||
// T4
|
||||
addr := uint16(c.m.Read(0x100 + uint16(c.r.SP)))
|
||||
c.r.SP++
|
||||
c.t.Tick()
|
||||
// T5
|
||||
addr |= (uint16(c.m.Read(0x100+uint16(c.r.SP))) << 8)
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
// Note that BRK skips the next instruction:
|
||||
// http://en.wikipedia.org/wiki/Interrupts_in_65xx_processors#Using_BRK_and_COP
|
||||
func brk(c *cpu) {
|
||||
// T1
|
||||
c.r.PC++
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T2
|
||||
c.m.Write(0x100+uint16(c.r.SP), byte(c.r.PC>>8))
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T3
|
||||
c.m.Write(0x100+uint16(c.r.SP), byte(c.r.PC&0xff))
|
||||
c.r.SP--
|
||||
c.t.Tick()
|
||||
// T4
|
||||
c.m.Write(0x100+uint16(c.r.SP), c.r.P|FLAG_B) // Set B flag
|
||||
c.r.P |= FLAG_I // Disable interrupts
|
||||
c.t.Tick()
|
||||
// T5
|
||||
addr := uint16(c.m.Read(IRQ_VECTOR))
|
||||
c.t.Tick()
|
||||
// T6
|
||||
addr |= (uint16(c.m.Read(IRQ_VECTOR+1)) << 8)
|
||||
c.r.PC = addr
|
||||
c.t.Tick()
|
||||
}
|
||||
|
||||
func branch(mask, value byte) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
offset := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
c.t.Tick()
|
||||
oldPC := c.r.PC
|
||||
if c.r.P&mask == value {
|
||||
c.t.Tick()
|
||||
c.r.PC = c.r.PC + uint16(offset)
|
||||
if offset >= 128 {
|
||||
c.r.PC = c.r.PC - 256
|
||||
}
|
||||
if !samePage(c.r.PC, oldPC) {
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
func immediate(f func(*cpu, byte)) func(*cpu) {
|
||||
return func(c *cpu) {
|
||||
// T1
|
||||
value := c.m.Read(c.r.PC)
|
||||
c.r.PC++
|
||||
f(c, value)
|
||||
c.t.Tick()
|
||||
}
|
||||
}
|
||||
|
||||
func lda(c *cpu, value byte) {
|
||||
c.r.A = value
|
||||
c.SetNZ(value)
|
||||
}
|
||||
|
||||
func ldx(c *cpu, value byte) {
|
||||
c.r.X = value
|
||||
c.SetNZ(value)
|
||||
}
|
||||
|
||||
func ldy(c *cpu, value byte) {
|
||||
c.r.Y = value
|
||||
c.SetNZ(value)
|
||||
}
|
||||
|
||||
func ora(c *cpu, value byte) {
|
||||
c.r.A |= value
|
||||
c.SetNZ(c.r.A)
|
||||
}
|
||||
|
||||
func and(c *cpu, value byte) {
|
||||
c.r.A &= value
|
||||
c.SetNZ(c.r.A)
|
||||
}
|
||||
|
||||
func eor(c *cpu, value byte) {
|
||||
c.r.A ^= value
|
||||
c.SetNZ(c.r.A)
|
||||
}
|
||||
|
||||
func cmp(c *cpu, value byte) {
|
||||
v := c.r.A - value
|
||||
c.SetNZ(v)
|
||||
}
|
||||
|
||||
func cpx(c *cpu, value byte) {
|
||||
v := c.r.X - value
|
||||
c.SetNZ(v)
|
||||
}
|
||||
|
||||
func cpy(c *cpu, value byte) {
|
||||
v := c.r.Y - value
|
||||
c.SetNZ(v)
|
||||
}
|
||||
|
||||
var opcodes = map[byte]func(*cpu){
|
||||
0x18: clearFlag(FLAG_C), // CLC
|
||||
0xD8: clearFlag(FLAG_D), // CLD
|
||||
0x58: clearFlag(FLAG_I), // CLI
|
||||
0xB8: clearFlag(FLAG_V), // CLV
|
||||
0x38: setFlag(FLAG_C), // SEC
|
||||
0xF8: setFlag(FLAG_D), // SED
|
||||
0x78: setFlag(FLAG_I), // SEI
|
||||
0xEA: nop,
|
||||
0xAA: tax,
|
||||
0xA8: tay,
|
||||
0xBA: tsx,
|
||||
0x8A: txa,
|
||||
0x9A: txs,
|
||||
0x98: tya,
|
||||
|
||||
0xCA: dex,
|
||||
0x88: dey,
|
||||
0xE8: inx,
|
||||
0xC8: iny,
|
||||
0x48: pha,
|
||||
0x08: php,
|
||||
0x68: pla,
|
||||
0x28: plp,
|
||||
|
||||
0x4C: jmpAbsolute,
|
||||
0x6C: jmpIndirect,
|
||||
0x20: jsr,
|
||||
0x60: rts,
|
||||
0x40: rti,
|
||||
0x00: brk,
|
||||
|
||||
0x90: branch(FLAG_C, 0), // BCC
|
||||
0xB0: branch(FLAG_C, FLAG_C), // BCS
|
||||
0xF0: branch(FLAG_Z, FLAG_Z), // BEQ
|
||||
0x30: branch(FLAG_N, FLAG_N), // BMI
|
||||
0xD0: branch(FLAG_Z, 0), // BNE
|
||||
0x10: branch(FLAG_N, 0), // BPL
|
||||
0x50: branch(FLAG_V, 0), // BVC
|
||||
0x70: branch(FLAG_V, FLAG_V), // BVS
|
||||
|
||||
0x09: immediate(ora),
|
||||
0x29: immediate(and),
|
||||
0x49: immediate(eor),
|
||||
// 0x69: immediate(adc),
|
||||
0xC0: immediate(cpy),
|
||||
0xC9: immediate(cmp),
|
||||
0xA0: immediate(ldy),
|
||||
0xA2: immediate(ldx),
|
||||
0xA9: immediate(lda),
|
||||
0xE0: immediate(cpx),
|
||||
// 0xE9: immediate(sbc),
|
||||
// Fake NoOp instruction used when disassembling.
|
||||
var NoOp = Opcode{"???", MODE_IMPLIED, nil}
|
||||
|
||||
// The list of Opcodes.
|
||||
var Opcodes = map[byte]Opcode{
|
||||
// Flag set and clear
|
||||
0x18: {"CLC", MODE_IMPLIED, clearFlag(FLAG_C)}, // CLC
|
||||
0xD8: {"CLD", MODE_IMPLIED, clearFlag(FLAG_D)}, // CLD
|
||||
0x58: {"CLI", MODE_IMPLIED, clearFlag(FLAG_I)}, // CLI
|
||||
0xB8: {"CLV", MODE_IMPLIED, clearFlag(FLAG_V)}, // CLV
|
||||
0x38: {"SEC", MODE_IMPLIED, setFlag(FLAG_C)}, // SEC
|
||||
0xF8: {"SED", MODE_IMPLIED, setFlag(FLAG_D)}, // SED
|
||||
0x78: {"SEI", MODE_IMPLIED, setFlag(FLAG_I)}, // SEI
|
||||
|
||||
// Very simple 1-opcode instructions
|
||||
0xEA: {"NOP", MODE_IMPLIED, nop},
|
||||
0xAA: {"TAX", MODE_IMPLIED, tax},
|
||||
0xA8: {"TAY", MODE_IMPLIED, tay},
|
||||
0xBA: {"TSX", MODE_IMPLIED, tsx},
|
||||
0x8A: {"TXA", MODE_IMPLIED, txa},
|
||||
0x9A: {"TXS", MODE_IMPLIED, txs},
|
||||
0x98: {"TYA", MODE_IMPLIED, tya},
|
||||
|
||||
// Slightly more complex 1-opcode instructions
|
||||
0xCA: {"DEX", MODE_IMPLIED, dex},
|
||||
0x88: {"DEY", MODE_IMPLIED, dey},
|
||||
0xE8: {"INX", MODE_IMPLIED, inx},
|
||||
0xC8: {"INY", MODE_IMPLIED, iny},
|
||||
0x48: {"PHA", MODE_IMPLIED, pha},
|
||||
0x08: {"PHP", MODE_IMPLIED, php},
|
||||
0x68: {"PLA", MODE_IMPLIED, pla},
|
||||
0x28: {"PLP", MODE_IMPLIED, plp},
|
||||
|
||||
// Jumps, returns, etc.
|
||||
0x4C: {"JMP", MODE_ABSOLUTE, jmpAbsolute},
|
||||
0x6C: {"JMP", MODE_INDIRECT, jmpIndirect},
|
||||
0x20: {"JSR", MODE_ABSOLUTE, jsr},
|
||||
0x60: {"RTS", MODE_IMPLIED, rts},
|
||||
0x40: {"RTI", MODE_IMPLIED, rti},
|
||||
0x00: {"BRK", MODE_IMPLIED, brk},
|
||||
|
||||
// Branches
|
||||
0x90: {"BCC", MODE_RELATIVE, branch(FLAG_C, 0)}, // BCC
|
||||
0xB0: {"BCS", MODE_RELATIVE, branch(FLAG_C, FLAG_C)}, // BCS
|
||||
0xF0: {"BEQ", MODE_RELATIVE, branch(FLAG_Z, FLAG_Z)}, // BEQ
|
||||
0x30: {"BMI", MODE_RELATIVE, branch(FLAG_N, FLAG_N)}, // BMI
|
||||
0xD0: {"BNE", MODE_RELATIVE, branch(FLAG_Z, 0)}, // BNE
|
||||
0x10: {"BPL", MODE_RELATIVE, branch(FLAG_N, 0)}, // BPL
|
||||
0x50: {"BVC", MODE_RELATIVE, branch(FLAG_V, 0)}, // BVC
|
||||
0x70: {"BVS", MODE_RELATIVE, branch(FLAG_V, FLAG_V)}, // BVS
|
||||
|
||||
// 2-opcode, 2-cycle immediate mode
|
||||
0x09: {"ORA", MODE_IMMEDIATE, immediate2(ora)},
|
||||
0x29: {"AND", MODE_IMMEDIATE, immediate2(and)},
|
||||
0x49: {"EOR", MODE_IMMEDIATE, immediate2(eor)},
|
||||
0x69: {"ADC", MODE_IMMEDIATE, immediate2(adc)},
|
||||
0xC0: {"CPY", MODE_IMMEDIATE, immediate2(cpy)},
|
||||
0xC9: {"CMP", MODE_IMMEDIATE, immediate2(cmp)},
|
||||
0xA0: {"LDY", MODE_IMMEDIATE, immediate2(ldy)},
|
||||
0xA2: {"LDX", MODE_IMMEDIATE, immediate2(ldx)},
|
||||
0xA9: {"LDA", MODE_IMMEDIATE, immediate2(lda)},
|
||||
0xE0: {"CPX", MODE_IMMEDIATE, immediate2(cpx)},
|
||||
0xE9: {"SBC", MODE_IMMEDIATE, immediate2(sbc)},
|
||||
|
||||
// 3-opcode, 4-cycle absolute mode
|
||||
0x8D: {"STA", MODE_ABSOLUTE, absolute4w(sta)},
|
||||
0x8E: {"STX", MODE_ABSOLUTE, absolute4w(stx)},
|
||||
0x8C: {"STY", MODE_ABSOLUTE, absolute4w(sty)},
|
||||
0x6D: {"ADC", MODE_ABSOLUTE, absolute4r(adc)},
|
||||
0x2D: {"AND", MODE_ABSOLUTE, absolute4r(and)},
|
||||
0x2C: {"BIT", MODE_ABSOLUTE, absolute4r(bit)},
|
||||
0xCD: {"CMP", MODE_ABSOLUTE, absolute4r(cmp)},
|
||||
0xEC: {"CPX", MODE_ABSOLUTE, absolute4r(cpx)},
|
||||
0xCC: {"CPY", MODE_ABSOLUTE, absolute4r(cpy)},
|
||||
0x4D: {"EOR", MODE_ABSOLUTE, absolute4r(eor)},
|
||||
0xAD: {"LDA", MODE_ABSOLUTE, absolute4r(lda)},
|
||||
0xAE: {"LDX", MODE_ABSOLUTE, absolute4r(ldx)},
|
||||
0xAC: {"LDY", MODE_ABSOLUTE, absolute4r(ldy)},
|
||||
0x0D: {"ORA", MODE_ABSOLUTE, absolute4r(ora)},
|
||||
0xED: {"SBC", MODE_ABSOLUTE, absolute4r(sbc)},
|
||||
|
||||
// 2-opcode, 3-cycle zero page
|
||||
0x05: {"ORA", MODE_ZP, zp3r(ora)},
|
||||
0x24: {"BIT", MODE_ZP, zp3r(bit)},
|
||||
0x25: {"AND", MODE_ZP, zp3r(and)},
|
||||
0x45: {"EOR", MODE_ZP, zp3r(eor)},
|
||||
0x65: {"ADC", MODE_ZP, zp3r(adc)},
|
||||
0x84: {"STY", MODE_ZP, zp3w(sty)},
|
||||
0x85: {"STA", MODE_ZP, zp3w(sta)},
|
||||
0x86: {"STX", MODE_ZP, zp3w(stx)},
|
||||
0xA4: {"LDY", MODE_ZP, zp3r(ldy)},
|
||||
0xA5: {"LDA", MODE_ZP, zp3r(lda)},
|
||||
0xA6: {"LDX", MODE_ZP, zp3r(ldx)},
|
||||
0xC4: {"CPY", MODE_ZP, zp3r(cpy)},
|
||||
0xC5: {"CMP", MODE_ZP, zp3r(cmp)},
|
||||
0xE4: {"CPX", MODE_ZP, zp3r(cpx)},
|
||||
0xE5: {"SBC", MODE_ZP, zp3r(sbc)},
|
||||
|
||||
// 3-opcode, 4*-cycle abs,X/Y
|
||||
0x1D: {"ORA", MODE_ABS_X, absx4r(ora)},
|
||||
0x19: {"ORA", MODE_ABS_X, absy4r(ora)},
|
||||
0x39: {"AND", MODE_ABS_X, absy4r(and)},
|
||||
0x3D: {"AND", MODE_ABS_X, absx4r(and)},
|
||||
0x59: {"EOR", MODE_ABS_X, absy4r(eor)},
|
||||
0x5D: {"EOR", MODE_ABS_X, absx4r(eor)},
|
||||
0x79: {"ADC", MODE_ABS_X, absy4r(adc)},
|
||||
0x7D: {"ADC", MODE_ABS_X, absx4r(adc)},
|
||||
0xBD: {"LDA", MODE_ABS_X, absx4r(lda)},
|
||||
0xB9: {"LDA", MODE_ABS_X, absy4r(lda)},
|
||||
0xD9: {"CMP", MODE_ABS_X, absy4r(cmp)},
|
||||
0xDD: {"CMP", MODE_ABS_X, absx4r(cmp)},
|
||||
0xF9: {"SBC", MODE_ABS_X, absy4r(sbc)},
|
||||
0xFD: {"SBC", MODE_ABS_X, absx4r(sbc)},
|
||||
0xBE: {"LDX", MODE_ABS_X, absy4r(ldx)},
|
||||
0xBC: {"LDY", MODE_ABS_X, absx4r(ldy)},
|
||||
|
||||
// 3-opcode, 5-cycle abs,X/Y
|
||||
0x99: {"STA", MODE_ABS_Y, absy5w(sta)},
|
||||
0x9D: {"STA", MODE_ABS_X, absx5w(sta)},
|
||||
|
||||
// 2-opcode, 4-cycle zp,X/Y
|
||||
0x15: {"ORA", MODE_ZP_X, zpx4r(ora)},
|
||||
0x35: {"AND", MODE_ZP_X, zpx4r(and)},
|
||||
0x55: {"EOR", MODE_ZP_X, zpx4r(eor)},
|
||||
0x75: {"ADC", MODE_ZP_X, zpx4r(adc)},
|
||||
0x95: {"STA", MODE_ZP_X, zpx4w(sta)},
|
||||
0xB5: {"LDA", MODE_ZP_X, zpx4r(lda)},
|
||||
0xD5: {"CMP", MODE_ZP_X, zpx4r(cmp)},
|
||||
0xF5: {"SBC", MODE_ZP_X, zpx4r(sbc)},
|
||||
0x96: {"STX", MODE_ZP_Y, zpy4w(stx)},
|
||||
0xB6: {"LDX", MODE_ZP_Y, zpy4r(ldx)},
|
||||
0x94: {"STY", MODE_ZP_X, zpx4w(sty)},
|
||||
0xB4: {"LDY", MODE_ZP_X, zpx4r(ldy)},
|
||||
|
||||
// 2-opcode, 5*-cycle zero-page indirect Y
|
||||
0x11: {"ORA", MODE_INDIRECT_Y, zpiy5r(ora)},
|
||||
0x31: {"AND", MODE_INDIRECT_Y, zpiy5r(and)},
|
||||
0x51: {"EOR", MODE_INDIRECT_Y, zpiy5r(eor)},
|
||||
0x71: {"ADC", MODE_INDIRECT_Y, zpiy5r(adc)},
|
||||
0x91: {"STA", MODE_INDIRECT_Y, zpiy6w(sta)},
|
||||
0xB1: {"LDA", MODE_INDIRECT_Y, zpiy5r(lda)},
|
||||
0xD1: {"CMP", MODE_INDIRECT_Y, zpiy5r(cmp)},
|
||||
0xF1: {"SBC", MODE_INDIRECT_Y, zpiy5r(sbc)},
|
||||
|
||||
// 2-opcode, 6-cycle zero-page X indirect
|
||||
0x01: {"ORA", MODE_INDIRECT_X, zpxi6r(ora)},
|
||||
0x21: {"AND", MODE_INDIRECT_X, zpxi6r(and)},
|
||||
0x41: {"EOR", MODE_INDIRECT_X, zpxi6r(eor)},
|
||||
0x61: {"ADC", MODE_INDIRECT_X, zpxi6r(adc)},
|
||||
0x81: {"STA", MODE_INDIRECT_X, zpxi6w(sta)},
|
||||
0xA1: {"LDA", MODE_INDIRECT_X, zpxi6r(lda)},
|
||||
0xC1: {"CMP", MODE_INDIRECT_X, zpxi6r(cmp)},
|
||||
0xE1: {"SBC", MODE_INDIRECT_X, zpxi6r(sbc)},
|
||||
|
||||
// 1-opcode, 2-cycle, accumulator rmw
|
||||
0x0A: {"ASL", MODE_A, acc2rmw(asl)},
|
||||
0x2A: {"ROL", MODE_A, acc2rmw(rol)},
|
||||
0x4A: {"LSR", MODE_A, acc2rmw(lsr)},
|
||||
0x6A: {"ROR", MODE_A, acc2rmw(ror)},
|
||||
|
||||
// 2-opcode, 5-cycle, zp rmw
|
||||
0x06: {"ASL", MODE_ZP, zp5rmw(asl)},
|
||||
0x26: {"ROL", MODE_ZP, zp5rmw(rol)},
|
||||
0x46: {"LSR", MODE_ZP, zp5rmw(lsr)},
|
||||
0x66: {"ROR", MODE_ZP, zp5rmw(ror)},
|
||||
0xC6: {"DEC", MODE_ZP, zp5rmw(dec)},
|
||||
0xE6: {"INC", MODE_ZP, zp5rmw(inc)},
|
||||
|
||||
// 3-opcode, 6-cycle, abs rmw
|
||||
0x0E: {"ASL", MODE_ABSOLUTE, abs6rmw(asl)},
|
||||
0x2E: {"ROL", MODE_ABSOLUTE, abs6rmw(rol)},
|
||||
0x4E: {"LSR", MODE_ABSOLUTE, abs6rmw(lsr)},
|
||||
0x6E: {"ROR", MODE_ABSOLUTE, abs6rmw(ror)},
|
||||
0xCE: {"DEC", MODE_ABSOLUTE, abs6rmw(dec)},
|
||||
0xEE: {"INC", MODE_ABSOLUTE, abs6rmw(inc)},
|
||||
|
||||
// 2-opcode, 6-cycle, zp,X rmw
|
||||
0x16: {"ASL", MODE_ZP_X, zpx6rmw(asl)},
|
||||
0x36: {"ROL", MODE_ZP_X, zpx6rmw(rol)},
|
||||
0x56: {"LSR", MODE_ZP_X, zpx6rmw(lsr)},
|
||||
0x76: {"ROR", MODE_ZP_X, zpx6rmw(ror)},
|
||||
0xD6: {"DEC", MODE_ZP_X, zpx6rmw(dec)},
|
||||
0xF6: {"INC", MODE_ZP_X, zpx6rmw(inc)},
|
||||
|
||||
// 3-opcode, 7-cycle, abs,X rmw
|
||||
0x1E: {"ASL", MODE_ABS_X, absx7rmw(asl)},
|
||||
0x3E: {"ROL", MODE_ABS_X, absx7rmw(rol)},
|
||||
0x5E: {"LSR", MODE_ABS_X, absx7rmw(lsr)},
|
||||
0x7E: {"ROR", MODE_ABS_X, absx7rmw(ror)},
|
||||
0xDE: {"DEC", MODE_ABS_X, absx7rmw(dec)},
|
||||
0xFE: {"INC", MODE_ABS_X, absx7rmw(inc)},
|
||||
}
|
||||
|
||||
@ -87,7 +87,7 @@ aaabbbcc
|
||||
| # | | | | | | | | | | | A2 | 2/2 | | | | |
|
||||
| zp | 06 | 2/5 | 26 | 2/5 | 46 | 2/5 | 66 | 2/5 | 86 | 2/3 | A6 | 2/3 | C6 | 2/5 | E6 | 2/5 |
|
||||
| A | 0A | 1/2 | 2A | 1/2 | 4A | 1/2 | 6A | 1/2 | | | | | | | | |
|
||||
| abs | 0E | 3/6 | 2E | 3/6 | 4E | 3/6 | 6E | 3/6 | 8E | 3/4 | AE | 3/4 | CE | 3/3 | EE | 3/6 |
|
||||
| abs | 0E | 3/6 | 2E | 3/6 | 4E | 3/6 | 6E | 3/6 | 8E | 3/4 | AE | 3/4 | CE | 3/6 | EE | 3/6 |
|
||||
| zp,X/zp,Y | 16 | 2/6 | 36 | 2/6 | 56 | 2/6 | 76 | 2/6 | 96 | 2/4 | B6 | 2/4 | D6 | 2/6 | F6 | 2/6 |
|
||||
| abs,X/abs,Y | 1E | 3/7 | 3E | 3/7 | 5E | 3/7 | 7E | 3/7 | ?? | | BE | 3/4* | DE | 3/7 | FE | 3/7 |
|
||||
|
||||
@ -121,3 +121,23 @@ aaabbbcc
|
||||
| abs | 2C | 3/4 | 4C | 3/3 | 6C | 3/5 | 8C | 3/4 | AC | 3/4 | CC | 3/4 | EC | 3/4 |
|
||||
| zp,X | | | | | | | 94 | 2/4 | B4 | 2/4 | | | | |
|
||||
| abs,X | | | | | | | | | BC | 3/4* | | | | |
|
||||
|
||||
* Opcodes remaining
|
||||
|
||||
| | 00 | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 | 0A | 0B | 0C | 0D | 0E | 0F |
|
||||
| 00 | | | - | - | - | | | - | | | | - | - | | | - |
|
||||
| 10 | | | - | - | - | | | - | | | - | - | - | ORA abs,X | ASL abs,X | - |
|
||||
| 20 | | | - | - | | | | - | | | | - | | | | - |
|
||||
| 30 | | | - | - | - | | | - | | | - | - | - | AND abs,X | ROL abs,X | - |
|
||||
| 40 | | | - | - | - | | | - | | | | - | | | | - |
|
||||
| 50 | | | - | - | - | | | - | | | - | - | - | EOR abs,X | LSR abs,X | - |
|
||||
| 60 | | | - | - | - | | | - | | | | - | | | | - |
|
||||
| 70 | | | - | - | - | | | - | | | - | - | - | ADC abs,X | ROR abs,X | - |
|
||||
| 80 | - | | - | - | | | | - | | - | | - | | | | - |
|
||||
| 90 | | | - | - | | | | - | | | | - | - | | - | - |
|
||||
| A0 | | | | - | | | | - | | | | - | | | | - |
|
||||
| B0 | | | - | - | | | | - | | | | - | LDY abs,X | LDA abs,X | LDX abs,Y | - |
|
||||
| C0 | | | - | - | | | | - | | | | - | | | | - |
|
||||
| D0 | | | - | - | - | | | - | | | - | - | - | CMP abs,X | DEC abs,X | - |
|
||||
| E0 | | SBC X,ind | - | - | | SBC zpg | | - | INX impl | SBC # | | - | | SBC abs | | - |
|
||||
| F0 | | | - | - | - | SBC zpg,X | | - | | SBC abs,Y | - | - | - | SBC abs,X | INC abs,X | ??? - |
|
||||
|
||||
@ -1,52 +0,0 @@
|
||||
package main
|
||||
|
||||
import (
|
||||
"fmt"
|
||||
"io/ioutil"
|
||||
|
||||
"github.com/zellyn/go6502/cpu"
|
||||
)
|
||||
|
||||
type K64 [65536]byte
|
||||
|
||||
func (m *K64) Read(address uint16) byte {
|
||||
return m[address]
|
||||
}
|
||||
|
||||
func (m *K64) Write(address uint16, value byte) {
|
||||
m[address] = value
|
||||
}
|
||||
|
||||
type CycleCount uint64
|
||||
|
||||
func (c *CycleCount) Tick() {
|
||||
*c += 1
|
||||
}
|
||||
|
||||
func main() {
|
||||
fmt.Println("Hello, world.")
|
||||
bytes, err := ioutil.ReadFile("6502_functional_test.bin")
|
||||
if err != nil {
|
||||
panic("Cannot read file")
|
||||
}
|
||||
var m K64
|
||||
var cc CycleCount
|
||||
OFFSET := 0xa
|
||||
copy(m[OFFSET:len(bytes)+OFFSET], bytes)
|
||||
c := cpu.NewCPU(&m, &cc)
|
||||
c.Reset()
|
||||
c.SetPC(0x1000)
|
||||
for {
|
||||
oldPC := c.PC()
|
||||
err := c.Step()
|
||||
if err != nil {
|
||||
fmt.Println(err)
|
||||
break
|
||||
}
|
||||
if c.PC() == oldPC {
|
||||
fmt.Printf("Stuck at 0x%X: 0x%X\n", oldPC, m[oldPC])
|
||||
break
|
||||
}
|
||||
}
|
||||
fmt.Println("Goodbye, world.")
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
324
tests/decimal_mode.a65
Normal file
324
tests/decimal_mode.a65
Normal file
@ -0,0 +1,324 @@
|
||||
; Decimal mode tests from Bruce Clark's fantastic Decimal Mode
|
||||
; tutorial on 6502.org. Modified very slightly to allow choosing the
|
||||
; CPU architecture (6502 or 65C02) without recompiling.
|
||||
; http://www.6502.org/tutorials/decimal_mode.html#B
|
||||
|
||||
bss
|
||||
org 0
|
||||
ERROR ds 1
|
||||
MODE ds 1 ; 0 for 6502, 1 for 65C02
|
||||
AR ds 1
|
||||
CF ds 1
|
||||
DA ds 1
|
||||
DNVZC ds 1
|
||||
HA ds 1
|
||||
HNVZC ds 1
|
||||
N1 ds 1
|
||||
N1H ds 1
|
||||
N1L ds 1
|
||||
N2 ds 1
|
||||
N2L ds 1
|
||||
NF ds 1
|
||||
VF ds 1
|
||||
ZF ds 1
|
||||
N2H ds 2
|
||||
|
||||
code
|
||||
org $1000
|
||||
|
||||
lda MODE
|
||||
bne INIT65C02
|
||||
INIT6502
|
||||
lda #lo(A6502)
|
||||
sta ADD_ADDR + 1
|
||||
lda #hi(A6502)
|
||||
sta ADD_ADDR + 2
|
||||
lda #lo(S6502)
|
||||
sta SUB_ADDR + 1
|
||||
lda #hi(S6502)
|
||||
sta SUB_ADDR + 2
|
||||
jmp INITDONE
|
||||
INIT65C02
|
||||
lda #lo(A65C02)
|
||||
sta ADD_ADDR + 1
|
||||
lda #hi(A65C02)
|
||||
sta ADD_ADDR + 2
|
||||
lda #lo(S65C02)
|
||||
sta SUB_ADDR + 1
|
||||
lda #hi(S65C02)
|
||||
sta SUB_ADDR + 2
|
||||
jmp INITDONE
|
||||
INITDONE
|
||||
jsr TEST
|
||||
lda #0
|
||||
beq * ; done
|
||||
|
||||
; Verify decimal mode behavior
|
||||
;
|
||||
; Returns:
|
||||
; ERROR = 0 if the test passed
|
||||
; ERROR = 1 if the test failed
|
||||
;
|
||||
; This routine requires 17 bytes of RAM -- 1 byte each for:
|
||||
; AR, CF, DA, DNVZC, ERROR, HA, HNVZC, N1, N1H, N1L, N2, N2L, NF, VF, and ZF
|
||||
; and 2 bytes for N2H
|
||||
;
|
||||
; Variables:
|
||||
; N1 and N2 are the two numbers to be added or subtracted
|
||||
; N1H, N1L, N2H, and N2L are the upper 4 bits and lower 4 bits of N1 and N2
|
||||
; DA and DNVZC are the actual accumulator and flag results in decimal mode
|
||||
; HA and HNVZC are the accumulator and flag results when N1 and N2 are
|
||||
; added or subtracted using binary arithmetic
|
||||
; AR, NF, VF, ZF, and CF are the predicted decimal mode accumulator and
|
||||
; flag results, calculated using binary arithmetic
|
||||
;
|
||||
; This program takes approximately 1 minute at 1 MHz (a few seconds more on
|
||||
; a 65C02 than a 6502 or 65816)
|
||||
;
|
||||
TEST ldy #1 ; initialize y (used to loop through carry flag values)
|
||||
sty ERROR ; store 1 in ERROR until the test passes
|
||||
lda #0 ; initialize N1 and N2
|
||||
sta N1
|
||||
sta N2
|
||||
LOOP1 lda N2 ; N2L = N2 & $0F
|
||||
and #$0F ; [1] see text
|
||||
sta N2L
|
||||
lda N2 ; N2H = N2 & $F0
|
||||
and #$F0 ; [2] see text
|
||||
sta N2H
|
||||
ora #$0F ; N2H+1 = (N2 & $F0) + $0F
|
||||
sta N2H+1
|
||||
LOOP2 lda N1 ; N1L = N1 & $0F
|
||||
and #$0F ; [3] see text
|
||||
sta N1L
|
||||
lda N1 ; N1H = N1 & $F0
|
||||
and #$F0 ; [4] see text
|
||||
sta N1H
|
||||
jsr ADD
|
||||
ADD_ADDR = *
|
||||
jsr A6502
|
||||
jsr COMPARE
|
||||
bne DONE
|
||||
jsr SUB
|
||||
SUB_ADDR = *
|
||||
jsr S6502
|
||||
jsr COMPARE
|
||||
bne DONE
|
||||
inc N1 ; [5] see text
|
||||
bne LOOP2 ; loop through all 256 values of N1
|
||||
inc N2 ; [6] see text
|
||||
bne LOOP1 ; loop through all 256 values of N2
|
||||
dey
|
||||
bpl LOOP1 ; loop through both values of the carry flag
|
||||
lda #0 ; test passed, so store 0 in ERROR
|
||||
sta ERROR
|
||||
DONE rts
|
||||
|
||||
; Calculate the actual decimal mode accumulator and flags, the accumulator
|
||||
; and flag results when N1 is added to N2 using binary arithmetic, the
|
||||
; predicted accumulator result, the predicted carry flag, and the predicted
|
||||
; V flag
|
||||
;
|
||||
ADD sed ; decimal mode
|
||||
cpy #1 ; set carry if Y = 1, clear carry if Y = 0
|
||||
lda N1
|
||||
adc N2
|
||||
sta DA ; actual accumulator result in decimal mode
|
||||
php
|
||||
pla
|
||||
sta DNVZC ; actual flags result in decimal mode
|
||||
cld ; binary mode
|
||||
cpy #1 ; set carry if Y = 1, clear carry if Y = 0
|
||||
lda N1
|
||||
adc N2
|
||||
sta HA ; accumulator result of N1+N2 using binary arithmetic
|
||||
|
||||
php
|
||||
pla
|
||||
sta HNVZC ; flags result of N1+N2 using binary arithmetic
|
||||
cpy #1
|
||||
lda N1L
|
||||
adc N2L
|
||||
cmp #$0A
|
||||
ldx #0
|
||||
bcc A1
|
||||
inx
|
||||
adc #5 ; add 6 (carry is set)
|
||||
and #$0F
|
||||
sec
|
||||
A1 ora N1H
|
||||
;
|
||||
; if N1L + N2L < $0A, then add N2 & $F0
|
||||
; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set)
|
||||
;
|
||||
adc N2H,x
|
||||
php
|
||||
bcs A2
|
||||
cmp #$A0
|
||||
bcc A3
|
||||
A2 adc #$5F ; add $60 (carry is set)
|
||||
sec
|
||||
A3 sta AR ; predicted accumulator result
|
||||
php
|
||||
pla
|
||||
sta CF ; predicted carry result
|
||||
pla
|
||||
;
|
||||
; note that all 8 bits of the P register are stored in VF
|
||||
;
|
||||
sta VF ; predicted V flags
|
||||
rts
|
||||
|
||||
; Calculate the actual decimal mode accumulator and flags, and the
|
||||
; accumulator and flag results when N2 is subtracted from N1 using binary
|
||||
; arithmetic
|
||||
;
|
||||
SUB sed ; decimal mode
|
||||
cpy #1 ; set carry if Y = 1, clear carry if Y = 0
|
||||
lda N1
|
||||
sbc N2
|
||||
sta DA ; actual accumulator result in decimal mode
|
||||
php
|
||||
pla
|
||||
sta DNVZC ; actual flags result in decimal mode
|
||||
cld ; binary mode
|
||||
cpy #1 ; set carry if Y = 1, clear carry if Y = 0
|
||||
lda N1
|
||||
sbc N2
|
||||
sta HA ; accumulator result of N1-N2 using binary arithmetic
|
||||
|
||||
php
|
||||
pla
|
||||
sta HNVZC ; flags result of N1-N2 using binary arithmetic
|
||||
rts
|
||||
|
||||
; Calculate the predicted SBC accumulator result for the 6502 and 65816
|
||||
|
||||
;
|
||||
SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0
|
||||
lda N1L
|
||||
sbc N2L
|
||||
ldx #0
|
||||
bcs S11
|
||||
inx
|
||||
sbc #5 ; subtract 6 (carry is clear)
|
||||
and #$0F
|
||||
clc
|
||||
S11 ora N1H
|
||||
;
|
||||
; if N1L - N2L >= 0, then subtract N2 & $F0
|
||||
; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear)
|
||||
;
|
||||
sbc N2H,x
|
||||
bcs S12
|
||||
sbc #$5F ; subtract $60 (carry is clear)
|
||||
S12 sta AR
|
||||
rts
|
||||
|
||||
; Calculate the predicted SBC accumulator result for the 6502 and 65C02
|
||||
|
||||
;
|
||||
SUB2 cpy #1 ; set carry if Y = 1, clear carry if Y = 0
|
||||
lda N1L
|
||||
sbc N2L
|
||||
ldx #0
|
||||
bcs S21
|
||||
inx
|
||||
and #$0F
|
||||
clc
|
||||
S21 ora N1H
|
||||
;
|
||||
; if N1L - N2L >= 0, then subtract N2 & $F0
|
||||
; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear)
|
||||
;
|
||||
sbc N2H,x
|
||||
bcs S22
|
||||
sbc #$5F ; subtract $60 (carry is clear)
|
||||
S22 cpx #0
|
||||
beq S23
|
||||
sbc #6
|
||||
S23 sta AR ; predicted accumulator result
|
||||
rts
|
||||
|
||||
; Compare accumulator actual results to predicted results
|
||||
;
|
||||
; Return:
|
||||
; Z flag = 1 (BEQ branch) if same
|
||||
; Z flag = 0 (BNE branch) if different
|
||||
;
|
||||
COMPARE lda DA
|
||||
cmp AR
|
||||
bne C1
|
||||
lda DNVZC ; [7] see text
|
||||
eor NF
|
||||
and #$80 ; mask off N flag
|
||||
bne C1
|
||||
lda DNVZC ; [8] see text
|
||||
eor VF
|
||||
and #$40 ; mask off V flag
|
||||
bne C1 ; [9] see text
|
||||
lda DNVZC
|
||||
eor ZF ; mask off Z flag
|
||||
and #2
|
||||
bne C1 ; [10] see text
|
||||
lda DNVZC
|
||||
eor CF
|
||||
and #1 ; mask off C flag
|
||||
C1 rts
|
||||
|
||||
; These routines store the predicted values for ADC and SBC for the 6502,
|
||||
; 65C02, and 65816 in AR, CF, NF, VF, and ZF
|
||||
|
||||
A6502 lda VF
|
||||
;
|
||||
; since all 8 bits of the P register were stored in VF, bit 7 of VF contains
|
||||
; the N flag for NF
|
||||
;
|
||||
sta NF
|
||||
lda HNVZC
|
||||
sta ZF
|
||||
rts
|
||||
|
||||
S6502 jsr SUB1
|
||||
lda HNVZC
|
||||
sta NF
|
||||
sta VF
|
||||
sta ZF
|
||||
sta CF
|
||||
rts
|
||||
|
||||
A65C02 lda AR
|
||||
php
|
||||
pla
|
||||
sta NF
|
||||
sta ZF
|
||||
rts
|
||||
|
||||
S65C02 jsr SUB2
|
||||
lda AR
|
||||
php
|
||||
pla
|
||||
sta NF
|
||||
sta ZF
|
||||
lda HNVZC
|
||||
sta VF
|
||||
sta CF
|
||||
rts
|
||||
|
||||
A65816 lda AR
|
||||
php
|
||||
pla
|
||||
sta NF
|
||||
sta ZF
|
||||
rts
|
||||
|
||||
S65816 jsr SUB1
|
||||
lda AR
|
||||
php
|
||||
pla
|
||||
sta NF
|
||||
sta ZF
|
||||
lda HNVZC
|
||||
sta VF
|
||||
sta CF
|
||||
rts
|
||||
BIN
tests/decimal_mode.bin
Normal file
BIN
tests/decimal_mode.bin
Normal file
Binary file not shown.
5
tests/filter.sh
Executable file
5
tests/filter.sh
Executable file
@ -0,0 +1,5 @@
|
||||
cat writes.txt |
|
||||
grep Wrote |
|
||||
sed -e 's/:.*//' |
|
||||
grep -ve '1094\|01..\|005[DE]\|023[34567]\|000F\|001[0123]\|3513\|3534' |
|
||||
head -10
|
||||
139
tests/functional_test.go
Normal file
139
tests/functional_test.go
Normal file
@ -0,0 +1,139 @@
|
||||
/*
|
||||
Tests for the 6502 CPU emulator.
|
||||
*/
|
||||
package tests
|
||||
|
||||
import (
|
||||
"fmt"
|
||||
"io/ioutil"
|
||||
"testing"
|
||||
|
||||
"github.com/zellyn/go6502/asm"
|
||||
"github.com/zellyn/go6502/cpu"
|
||||
)
|
||||
|
||||
// Memory for the tests. Satisfies the cpu.Memory interface.
|
||||
type K64 [65536]byte
|
||||
|
||||
func (m *K64) Read(address uint16) byte {
|
||||
return m[address]
|
||||
}
|
||||
func (m *K64) Write(address uint16, value byte) {
|
||||
m[address] = value
|
||||
}
|
||||
|
||||
// Cycle counter for the tests. Satisfies the cpu.Ticker interface.
|
||||
type CycleCount uint64
|
||||
|
||||
func (c *CycleCount) Tick() {
|
||||
*c += 1
|
||||
}
|
||||
|
||||
// printStatus prints out the current CPU instruction and register status.
|
||||
func printStatus(c cpu.Cpu, m K64, cc CycleCount) {
|
||||
bytes, text, _ := asm.Disasm(c.PC(), m[c.PC()], m[c.PC()+1], m[c.PC()+2])
|
||||
fmt.Printf("$%04X: %s %s A=$%02X X=$%02X Y=$%02X SP=$%02X P=$%08b - %d\n",
|
||||
c.PC(), bytes, text, c.A(), c.X(), c.Y(), c.SP(), c.P(), cc)
|
||||
}
|
||||
|
||||
// Run Klaus Dormann's amazing comprehensive test.
|
||||
func TestFunctionalTest(t *testing.T) {
|
||||
bytes, err := ioutil.ReadFile("6502_functional_test.bin")
|
||||
if err != nil {
|
||||
panic("Cannot read file")
|
||||
}
|
||||
var m K64
|
||||
var cc CycleCount
|
||||
OFFSET := 0xa
|
||||
copy(m[OFFSET:len(bytes)+OFFSET], bytes)
|
||||
c := cpu.NewCPU(&m, &cc, cpu.VERSION_6502)
|
||||
c.Reset()
|
||||
c.SetPC(0x1000)
|
||||
for {
|
||||
oldPC := c.PC()
|
||||
// printStatus(c, m, cc)
|
||||
err := c.Step()
|
||||
if err != nil {
|
||||
t.Error(err)
|
||||
break
|
||||
}
|
||||
if c.PC() == oldPC {
|
||||
if c.PC() != 0x3BB5 {
|
||||
t.Errorf("Stuck at 0x%X: 0x%X\n", oldPC, m[oldPC])
|
||||
}
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Run Bruce Clark's decimal test in 6502 mode.
|
||||
func TestDecimalMode6502(t *testing.T) {
|
||||
bytes, err := ioutil.ReadFile("decimal_mode.bin")
|
||||
if err != nil {
|
||||
panic("Cannot read file")
|
||||
}
|
||||
var m K64
|
||||
var cc CycleCount
|
||||
OFFSET := 0x1000
|
||||
copy(m[OFFSET:len(bytes)+OFFSET], bytes)
|
||||
m[1] = 0 // 6502
|
||||
c := cpu.NewCPU(&m, &cc, cpu.VERSION_6502)
|
||||
c.Reset()
|
||||
c.SetPC(0x1000)
|
||||
for {
|
||||
oldPC := c.PC()
|
||||
// printStatus(c, m, cc)
|
||||
err := c.Step()
|
||||
if err != nil {
|
||||
t.Error(err)
|
||||
break
|
||||
}
|
||||
if c.PC() == oldPC {
|
||||
if c.PC() != 0x1037 {
|
||||
t.Errorf("Stuck at 0x%X: 0x%X\n", oldPC, m[oldPC])
|
||||
}
|
||||
break
|
||||
}
|
||||
}
|
||||
error := m[0]
|
||||
if error > 0 {
|
||||
t.Errorf("Decimal mode test failed: error=%d", error)
|
||||
}
|
||||
}
|
||||
|
||||
// Run Bruce Clark's decimal test in 65C02 mode.
|
||||
func TestDecimalMode65C02(t *testing.T) {
|
||||
bytes, err := ioutil.ReadFile("decimal_mode.bin")
|
||||
if err != nil {
|
||||
panic("Cannot read file")
|
||||
}
|
||||
var m K64
|
||||
var cc CycleCount
|
||||
OFFSET := 0x1000
|
||||
copy(m[OFFSET:len(bytes)+OFFSET], bytes)
|
||||
m[1] = 1 // 65C02
|
||||
c := cpu.NewCPU(&m, &cc, cpu.VERSION_65C02)
|
||||
c.Reset()
|
||||
c.SetPC(0x1000)
|
||||
for {
|
||||
oldPC := c.PC()
|
||||
// printStatus(c, m, cc)
|
||||
err := c.Step()
|
||||
if err != nil {
|
||||
t.Error(err)
|
||||
break
|
||||
}
|
||||
if c.PC() == oldPC {
|
||||
if c.PC() != 0x1037 {
|
||||
t.Errorf("Stuck at 0x%X: 0x%X\n", oldPC, m[oldPC])
|
||||
}
|
||||
break
|
||||
}
|
||||
}
|
||||
error := m[0]
|
||||
if error > 0 {
|
||||
fmt.Printf("N1=$%02X N2=$%02X DA=$%02X DNVZC=$%02X - AR=$%02X NF=$%02X VF=$%02X ZF=$%02X CF=$%02X\n",
|
||||
m[0x08], m[0x0B], m[0x04], m[0x05], m[0x02], m[0x0D], m[0x0E], m[0x0F], m[0x03])
|
||||
t.Errorf("Decimal mode test failed: error=%d", error)
|
||||
}
|
||||
}
|
||||
230
tests/output.txt
Normal file
230
tests/output.txt
Normal file
@ -0,0 +1,230 @@
|
||||
Hello, world.
|
||||
0
|
||||
2
|
||||
4
|
||||
6
|
||||
8
|
||||
1000001
|
||||
2000000
|
||||
3000000
|
||||
4000000
|
||||
5000000
|
||||
6000002
|
||||
7000001
|
||||
8000001
|
||||
9000000
|
||||
10000000
|
||||
11000001
|
||||
12000002
|
||||
13000001
|
||||
14000000
|
||||
14000003
|
||||
14000005
|
||||
14000009
|
||||
15000001
|
||||
15000007
|
||||
16000001
|
||||
16000004
|
||||
16000007
|
||||
16000009
|
||||
17000000
|
||||
17000004
|
||||
17000007
|
||||
18000000
|
||||
18000002
|
||||
18000006
|
||||
18000008
|
||||
19000001
|
||||
19000004
|
||||
19000006
|
||||
20000000
|
||||
20000004
|
||||
20000007
|
||||
21000000
|
||||
21000003
|
||||
21000005
|
||||
21000009
|
||||
22000004
|
||||
22000007
|
||||
23000002
|
||||
23000005
|
||||
24000001
|
||||
24000004
|
||||
24000008
|
||||
25000004
|
||||
25000007
|
||||
25000009
|
||||
26000001
|
||||
26000005
|
||||
26000008
|
||||
27000000
|
||||
27000004
|
||||
27000007
|
||||
28000003
|
||||
28000006
|
||||
28000009
|
||||
29000002
|
||||
29000005
|
||||
29000008
|
||||
30000002
|
||||
30000004
|
||||
30000007
|
||||
30000009
|
||||
31000001
|
||||
31000005
|
||||
31000008
|
||||
32000001
|
||||
32000004
|
||||
32000007
|
||||
33000000
|
||||
33000004
|
||||
33000007
|
||||
34000000
|
||||
34000003
|
||||
34000006
|
||||
35000000
|
||||
35000003
|
||||
35000007
|
||||
36000000
|
||||
36000002
|
||||
36000006
|
||||
36000008
|
||||
37000000
|
||||
37000002
|
||||
37000006
|
||||
37000008
|
||||
38000000
|
||||
38000003
|
||||
38000005
|
||||
38000008
|
||||
39000002
|
||||
39000008
|
||||
40000000
|
||||
40000003
|
||||
40000006
|
||||
41000002
|
||||
41000005
|
||||
41000008
|
||||
42000002
|
||||
42000004
|
||||
42000008
|
||||
43000002
|
||||
43000005
|
||||
43000008
|
||||
44000001
|
||||
44000004
|
||||
44000006
|
||||
45000003
|
||||
45000006
|
||||
45000009
|
||||
46000001
|
||||
46000005
|
||||
46000008
|
||||
47000000
|
||||
47000003
|
||||
47000005
|
||||
47000009
|
||||
48000002
|
||||
48000005
|
||||
48000009
|
||||
49000001
|
||||
49000004
|
||||
49000007
|
||||
50000002
|
||||
50000005
|
||||
50000009
|
||||
51000001
|
||||
51000004
|
||||
51000007
|
||||
52000000
|
||||
52000003
|
||||
52000006
|
||||
53000000
|
||||
53000003
|
||||
53000005
|
||||
53000009
|
||||
54000001
|
||||
54000004
|
||||
54000007
|
||||
55000001
|
||||
55000003
|
||||
55000006
|
||||
55000008
|
||||
56000000
|
||||
56000004
|
||||
56000007
|
||||
57000000
|
||||
57000004
|
||||
57000007
|
||||
58000000
|
||||
58000002
|
||||
58000006
|
||||
58000009
|
||||
59000003
|
||||
59000006
|
||||
59000009
|
||||
60000001
|
||||
60000004
|
||||
60000007
|
||||
61000003
|
||||
61000006
|
||||
61000009
|
||||
62000003
|
||||
62000007
|
||||
63000000
|
||||
63000004
|
||||
63000007
|
||||
64000000
|
||||
64000004
|
||||
64000006
|
||||
64000009
|
||||
65000002
|
||||
65000004
|
||||
65000008
|
||||
66000000
|
||||
66000003
|
||||
66000005
|
||||
66000009
|
||||
67000002
|
||||
67000004
|
||||
67000008
|
||||
68000002
|
||||
68000008
|
||||
69000002
|
||||
69000004
|
||||
69000007
|
||||
69000009
|
||||
70000001
|
||||
70000004
|
||||
70000008
|
||||
71000002
|
||||
71000006
|
||||
71000009
|
||||
72000002
|
||||
72000004
|
||||
73000000
|
||||
73000004
|
||||
73000008
|
||||
74000002
|
||||
74000004
|
||||
74000007
|
||||
74000009
|
||||
75000002
|
||||
75000004
|
||||
75000008
|
||||
76000001
|
||||
76000003
|
||||
76000007
|
||||
77000001
|
||||
77000005
|
||||
77000007
|
||||
78000002
|
||||
78000004
|
||||
78000007
|
||||
79000001
|
||||
79000005
|
||||
79000008
|
||||
80000001
|
||||
80000003
|
||||
80000007
|
||||
80000009
|
||||
1100533
tests/writes.txt
Normal file
1100533
tests/writes.txt
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user