i6502/acia6551.go

102 lines
1.4 KiB
Go
Raw Normal View History

2014-08-17 14:49:22 +00:00
package i6502
2014-08-17 15:18:14 +00:00
const (
aciaData = iota
aciaStatus
aciaCommand
aciaControl
)
2014-08-17 14:49:22 +00:00
/*
ACIA 6551 Serial IO
*/
type Acia6551 struct {
2014-08-17 15:18:14 +00:00
Rx chan byte // Reading (Acia Input) line
Tx chan byte // Transmitting (Acia Output) line
2014-08-17 20:36:01 +00:00
rxData byte
txData byte
2014-08-17 15:18:14 +00:00
commandData byte
controlData byte
rxFull bool
txEmpty bool
rxIrqEnabled bool
txIrqEnabled bool
2014-08-17 20:36:01 +00:00
overrun bool
2014-08-17 14:49:22 +00:00
}
func NewAcia6551(rx chan byte, tx chan byte) (*Acia6551, error) {
2014-08-17 15:18:14 +00:00
acia := &Acia6551{Tx: tx, Rx: rx}
acia.Reset()
go func() {
// Handle rx data channel
}()
go func() {
// Handle tx data channel
}()
return acia, nil
2014-08-17 14:49:22 +00:00
}
2014-08-17 15:18:14 +00:00
func (a *Acia6551) Size() uint16 {
// We have a only 4 addresses, Data, Status, Command and Control
2014-08-17 14:49:22 +00:00
return 0x04
}
2014-08-17 20:36:01 +00:00
// Emulates a hardware reset
2014-08-17 15:18:14 +00:00
func (a *Acia6551) Reset() {
a.rxData = 0
a.rxFull = false
a.txData = 0
a.txEmpty = true
a.rxIrqEnabled = false
a.txIrqEnabled = false
2014-08-17 20:36:01 +00:00
a.overrun = false
a.setControl(0)
a.setCommand(0)
2014-08-17 15:18:14 +00:00
}
2014-08-17 20:36:01 +00:00
func (a *Acia6551) setControl(data byte) {
2014-08-17 14:49:22 +00:00
}
2014-08-17 20:36:01 +00:00
func (a *Acia6551) setCommand(data byte) {
}
func (a *Acia6551) Read(address uint16) byte {
switch address {
case aciaData:
// Read Rx
case aciaStatus:
// Read Status reg.
case aciaCommand:
// Read command
case aciaControl:
// Read control
}
return 0x00
}
func (a *Acia6551) Write(address uint16, data byte) {
switch address {
case aciaData:
// Write Tx
case aciaStatus:
// Reset
case aciaCommand:
// Write command
case aciaControl:
// Write control
}
2014-08-17 14:49:22 +00:00
}