mirror of https://github.com/ariejan/i6502.git
263 lines
4.9 KiB
Go
263 lines
4.9 KiB
Go
package i6502
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import "fmt"
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type Cpu struct {
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bus *AddressBus // The address bus
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PC uint16 // 16-bit program counter
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P byte // Status Register
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SP byte // Stack Pointer
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A byte // Accumulator
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X byte // X index register
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Y byte // Y index register
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}
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const (
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ResetVector = 0xFFFC // 0xFFFC-FFFD
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IrqVector = 0xFFFE // 0xFFFE-FFFF
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)
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// Create an new Cpu instance with the specified AddressBus
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func NewCpu(bus *AddressBus) (*Cpu, error) {
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return &Cpu{bus: bus}, nil
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}
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func (c *Cpu) String() string {
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str := ">>> CPU [ A ] [ X ] [ Y ] [ SP ] [ PC ] NVxBDIZC\n>>> 0x%02X 0x%02X 0x%02X 0x%02X 0x%04X %08b\n"
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return fmt.Sprintf(str, c.A, c.X, c.Y, c.SP, c.PC, c.P)
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}
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func (c *Cpu) HasAddressBus() bool {
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return c.bus != nil
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}
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// Reset the CPU, emulating the RESB pin.
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func (c *Cpu) Reset() {
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c.PC = c.bus.Read16(ResetVector)
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c.P = 0x34
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// Not specified, but let's clean up
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c.A = 0x00
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c.X = 0x00
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c.Y = 0x00
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c.SP = 0xFF
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}
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// Simulate the IRQ pin
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func (c *Cpu) Interrupt() {
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c.handleIrq(c.PC)
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}
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func (c *Cpu) handleIrq(PC uint16) {
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c.stackPush(byte(PC >> 8))
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c.stackPush(byte(PC))
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c.stackPush(c.P)
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c.setIrqDisable(true)
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c.PC = c.bus.Read16(IrqVector)
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}
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// Load the specified program data at the given memory location
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// and point the Program Counter to the beginning of the program
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func (c *Cpu) LoadProgram(data []byte, location uint16) {
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for i, b := range data {
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c.bus.Write(location+uint16(i), b)
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}
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c.PC = location
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}
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// Execute the instruction pointed to by the Program Counter (PC)
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func (c *Cpu) Step() {
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// fmt.Println(c)
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instruction := c.readNextInstruction()
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c.PC += uint16(instruction.Size)
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// fmt.Println(instruction)
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c.execute(instruction)
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}
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func (c *Cpu) execute(instruction Instruction) {
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switch instruction.opcodeId {
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case nop:
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break
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case adc:
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c.ADC(instruction)
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case sbc:
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c.SBC(instruction)
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case sec:
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c.setCarry(true)
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case sed:
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c.setDecimal(true)
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case sei:
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c.setIrqDisable(true)
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case clc:
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c.setCarry(false)
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case cld:
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c.setDecimal(false)
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case cli:
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c.setIrqDisable(false)
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case clv:
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c.setOverflow(false)
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case inx:
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c.setX(c.X + 1)
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case iny:
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c.setY(c.Y + 1)
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case inc:
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c.INC(instruction)
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case dex:
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c.setX(c.X - 1)
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case dey:
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c.setY(c.Y - 1)
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case dec:
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c.DEC(instruction)
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case lda:
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c.LDA(instruction)
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case ldx:
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c.LDX(instruction)
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case ldy:
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c.LDY(instruction)
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case ora:
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c.ORA(instruction)
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case and:
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c.AND(instruction)
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case eor:
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c.EOR(instruction)
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case sta:
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c.STA(instruction)
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case stx:
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c.STX(instruction)
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case sty:
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c.STY(instruction)
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case tax:
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c.setX(c.A)
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case tay:
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c.setY(c.A)
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case txa:
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c.setA(c.X)
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case tya:
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c.setA(c.Y)
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case tsx:
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c.setX(c.SP)
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case txs:
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c.SP = c.X
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case asl:
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c.ASL(instruction)
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case lsr:
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c.LSR(instruction)
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case rol:
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c.ROL(instruction)
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case ror:
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c.ROR(instruction)
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case cmp:
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c.CMP(instruction)
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case cpx:
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c.CPX(instruction)
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case cpy:
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c.CPY(instruction)
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case brk:
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c.BRK()
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case bcc:
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if !c.getCarry() {
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c.branch(instruction)
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}
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case bcs:
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if c.getCarry() {
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c.branch(instruction)
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}
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case bne:
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if !c.getZero() {
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c.branch(instruction)
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}
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case beq:
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if c.getZero() {
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c.branch(instruction)
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}
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case bpl:
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if !c.getNegative() {
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c.branch(instruction)
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}
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case bmi:
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if c.getNegative() {
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c.branch(instruction)
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}
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case bvc:
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if !c.getOverflow() {
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c.branch(instruction)
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}
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case bvs:
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if c.getOverflow() {
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c.branch(instruction)
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}
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case bit:
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c.BIT(instruction)
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case php:
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c.stackPush(c.P | 0x30)
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case plp:
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c.setP(c.stackPop())
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case pha:
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c.stackPush(c.A)
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case pla:
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value := c.stackPop()
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c.setA(value)
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case jmp:
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c.JMP(instruction)
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case jsr:
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c.JSR(instruction)
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case rts:
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c.PC = (uint16(c.stackPop()) | uint16(c.stackPop())<<8) + 1
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case rti:
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c.setP(c.stackPop())
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c.PC = uint16(c.stackPop()) | uint16(c.stackPop())<<8
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default:
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panic(fmt.Errorf("Unimplemented instruction: %s", instruction))
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}
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}
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func (c *Cpu) branch(in Instruction) {
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relative := int8(in.Op8) // Signed!
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if relative >= 0 {
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c.PC += uint16(relative)
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} else {
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c.PC -= -uint16(relative)
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}
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}
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func (c *Cpu) resolveOperand(in Instruction) uint8 {
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switch in.addressingId {
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case immediate:
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return in.Op8
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default:
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return c.bus.Read(c.memoryAddress(in))
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}
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}
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func (c *Cpu) memoryAddress(in Instruction) uint16 {
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switch in.addressingId {
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case absolute:
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return in.Op16
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case absoluteX:
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return in.Op16 + uint16(c.X)
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case absoluteY:
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return in.Op16 + uint16(c.Y)
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case indirect:
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return c.bus.Read16(in.Op16)
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case indirectX:
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return c.bus.Read16(uint16(in.Op8 + c.X))
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case indirectY:
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return c.bus.Read16(uint16(in.Op8)) + uint16(c.Y)
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case relative:
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panic("Relative addressing not yet implemented.")
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case zeropage:
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return uint16(in.Op8)
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case zeropageX:
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return uint16(in.Op8 + c.X)
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case zeropageY:
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return uint16(in.Op8 + c.Y)
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default:
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panic(fmt.Errorf("Unhandled addressing mode. Are you sure you are running a 6502 ROM?"))
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}
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}
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