mirror of https://github.com/ariejan/i6502.git
70 lines
1.2 KiB
Go
70 lines
1.2 KiB
Go
/*
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i6502 is a software emulator of my i6502 home-built computer. It uses
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the 65C02 microprocessor, 32kB RAM and 16kB ROM.
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*/
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package main
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import (
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"fmt"
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"github.com/ariejan/i6502/bus"
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"github.com/ariejan/i6502/cpu"
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"github.com/ariejan/i6502/memory"
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"os"
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"os/signal"
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)
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func main() {
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os.Exit(mainReturningStatus())
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}
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func mainReturningStatus() int {
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// 32kB RAM
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ram := memory.CreateRam()
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// 16kB ROM, filled from file
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rom, err := memory.LoadRomFromFile("rom/test.rom")
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if err != nil {
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panic(err)
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}
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// 16-bit address bus
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bus, _ := bus.CreateBus()
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bus.Attach(ram, "32kB RAM", 0x0000)
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bus.Attach(rom, "16kB ROM", 0xC000)
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fmt.Println(bus)
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exitChan := make(chan int, 0)
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cpu := &cpu.Cpu{Bus: bus, ExitChan: exitChan}
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cpu.Reset()
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go func() {
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for {
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cpu.Step()
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}
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}()
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var (
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sig os.Signal
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exitStatus int
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)
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sigChan := make(chan os.Signal, 1)
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signal.Notify(sigChan, os.Interrupt)
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select {
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case exitStatus = <-exitChan:
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// Okay, handle the rest of the code
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case sig = <-sigChan:
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fmt.Println("\nGot signal: ", sig)
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exitStatus = 1
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}
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fmt.Println(cpu)
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fmt.Println("Dumping RAM into `core` file")
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ram.Dump("core")
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return exitStatus
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}
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