mirror of https://github.com/ariejan/i6502.git
94 lines
1.7 KiB
Go
94 lines
1.7 KiB
Go
package main
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import (
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"github.com/ariejan/i6502/bus"
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"github.com/ariejan/i6502/cpu"
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"github.com/ariejan/i6502/devices"
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"github.com/ariejan/i6502/memory"
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"os"
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)
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type Machine struct {
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// Outgoing bytes, using the serial interface
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SerialTx chan byte
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// Incoming bytes, using the serial interface
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SerialRx chan byte
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// The cpu, bus etc.
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cpu *cpu.Cpu
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bus *bus.Bus
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}
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// Creates a new i6502 Machine instance
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func CreateMachine() *Machine {
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// Channel for handling interrupts
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irqChan := make(chan bool, 0)
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nmiChan := make(chan bool, 0)
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ram := memory.CreateRam()
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rom, err := memory.LoadRomFromFile("rom/ehbasic.rom")
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if err != nil {
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panic(err)
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}
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acia6551 := devices.NewAcia6551(irqChan)
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via6522 := devices.NewVia6522(irqChan)
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bus, _ := bus.CreateBus()
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bus.Attach(ram, "32kB RAM", 0x0000)
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bus.Attach(rom, "16kB ROM", 0xC000)
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bus.Attach(via6522, "VIA 6522 Parallel", 0x8000)
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bus.Attach(acia6551, "ACIA 6551 Serial", 0x8800)
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cpu := &cpu.Cpu{Bus: bus, IrqChan: irqChan, NmiChan: nmiChan, ExitChan: make(chan int, 0)}
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machine := &Machine{SerialTx: make(chan byte, 256), SerialRx: make(chan byte, 256), cpu: cpu, bus: bus}
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// Run the CPU
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go func() {
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for {
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cpu.Step()
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}
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}()
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// Connect acia6551 Tx to SerialTx
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go func() {
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for {
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select {
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case data := <-acia6551.TxChan:
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machine.SerialTx <- data
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}
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}
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}()
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// Connect SerialRx to acia6551 Rx
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go func() {
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for {
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select {
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case data := <-machine.SerialRx:
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acia6551.RxWrite(data)
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}
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}
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}()
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go func() {
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for {
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select {
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case <-machine.cpu.ExitChan:
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ram.Dump("intcore")
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os.Exit(42)
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}
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}
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}()
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cpu.Reset()
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return machine
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}
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func (m *Machine) Reset() {
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m.cpu.Reset()
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}
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