Inlined call vicSelectGfxBank::$0 = call toDd00(vicSelectGfxBank::gfx)
Inlined call main::$0 = call toD018(SCREEN, LOGO)
Inlined call call __init
Eliminating unused variable with no statement sin16s_gen2::$0
Eliminating unused variable with no statement sin16s_gen2::$2
Eliminating unused variable with no statement sin16s_gen2::$3
Eliminating unused variable with no statement sin16s::$5
Eliminating unused variable with no statement sin16s::$6
Eliminating unused variable with no statement sin16s::$7
Eliminating unused variable with no statement sin16s::$8
Eliminating unused variable with no statement sin16s::$9
Eliminating unused variable with no statement sin16s::$10
Eliminating unused variable with no statement sin16s::$11
Eliminating unused variable with no statement sin16s::$12
Eliminating unused variable with no statement div32u16u::$1
Eliminating unused variable with no statement div32u16u::$3
Eliminating unused variable with no statement div32u16u::$4
Eliminating unused variable with no statement mul16s::$0
Eliminating unused variable with no statement memset::$2

CONTROL FLOW GRAPH SSA

void sin16s_gen2(int *sintab , unsigned int wavelength , int min , int max)
sin16s_gen2: scope:[sin16s_gen2]  from main::@2
  sin16s_gen2::sintab#7 = phi( main::@2/sin16s_gen2::sintab#1 )
  rem16u#22 = phi( main::@2/rem16u#25 )
  sin16s_gen2::wavelength#1 = phi( main::@2/sin16s_gen2::wavelength#0 )
  sin16s_gen2::min#1 = phi( main::@2/sin16s_gen2::min#0 )
  sin16s_gen2::max#1 = phi( main::@2/sin16s_gen2::max#0 )
  sin16s_gen2::ampl#0 = sin16s_gen2::max#1 - sin16s_gen2::min#1
  sin16s_gen2::$1 = sin16s_gen2::ampl#0 >> 1
  sin16s_gen2::offs#0 = sin16s_gen2::min#1 + sin16s_gen2::$1
  div32u16u::dividend#0 = PI2_u4f28
  div32u16u::divisor#0 = sin16s_gen2::wavelength#1
  call div32u16u
  div32u16u::return#0 = div32u16u::return#2
  to:sin16s_gen2::@3
sin16s_gen2::@3: scope:[sin16s_gen2]  from sin16s_gen2
  sin16s_gen2::sintab#6 = phi( sin16s_gen2/sin16s_gen2::sintab#7 )
  sin16s_gen2::offs#5 = phi( sin16s_gen2/sin16s_gen2::offs#0 )
  sin16s_gen2::ampl#4 = phi( sin16s_gen2/sin16s_gen2::ampl#0 )
  sin16s_gen2::wavelength#3 = phi( sin16s_gen2/sin16s_gen2::wavelength#1 )
  rem16u#12 = phi( sin16s_gen2/rem16u#6 )
  div32u16u::return#3 = phi( sin16s_gen2/div32u16u::return#0 )
  sin16s_gen2::step#0 = div32u16u::return#3
  rem16u#0 = rem16u#12
  sin16s_gen2::x#0 = 0
  sin16s_gen2::i#0 = 0
  to:sin16s_gen2::@1
sin16s_gen2::@1: scope:[sin16s_gen2]  from sin16s_gen2::@3 sin16s_gen2::@5
  sin16s_gen2::step#4 = phi( sin16s_gen2::@3/sin16s_gen2::step#0, sin16s_gen2::@5/sin16s_gen2::step#1 )
  sin16s_gen2::sintab#5 = phi( sin16s_gen2::@3/sin16s_gen2::sintab#6, sin16s_gen2::@5/sin16s_gen2::sintab#0 )
  sin16s_gen2::offs#4 = phi( sin16s_gen2::@3/sin16s_gen2::offs#5, sin16s_gen2::@5/sin16s_gen2::offs#1 )
  sin16s_gen2::ampl#3 = phi( sin16s_gen2::@3/sin16s_gen2::ampl#4, sin16s_gen2::@5/sin16s_gen2::ampl#5 )
  rem16u#23 = phi( sin16s_gen2::@3/rem16u#0, sin16s_gen2::@5/rem16u#28 )
  sin16s_gen2::x#4 = phi( sin16s_gen2::@3/sin16s_gen2::x#0, sin16s_gen2::@5/sin16s_gen2::x#1 )
  sin16s_gen2::wavelength#2 = phi( sin16s_gen2::@3/sin16s_gen2::wavelength#3, sin16s_gen2::@5/sin16s_gen2::wavelength#4 )
  sin16s_gen2::i#2 = phi( sin16s_gen2::@3/sin16s_gen2::i#0, sin16s_gen2::@5/sin16s_gen2::i#1 )
  sin16s_gen2::$4 = sin16s_gen2::i#2 < sin16s_gen2::wavelength#2
  if(sin16s_gen2::$4) goto sin16s_gen2::@2
  to:sin16s_gen2::@return
sin16s_gen2::@2: scope:[sin16s_gen2]  from sin16s_gen2::@1
  rem16u#32 = phi( sin16s_gen2::@1/rem16u#23 )
  sin16s_gen2::wavelength#6 = phi( sin16s_gen2::@1/sin16s_gen2::wavelength#2 )
  sin16s_gen2::i#5 = phi( sin16s_gen2::@1/sin16s_gen2::i#2 )
  sin16s_gen2::step#3 = phi( sin16s_gen2::@1/sin16s_gen2::step#4 )
  sin16s_gen2::sintab#4 = phi( sin16s_gen2::@1/sin16s_gen2::sintab#5 )
  sin16s_gen2::offs#3 = phi( sin16s_gen2::@1/sin16s_gen2::offs#4 )
  sin16s_gen2::ampl#2 = phi( sin16s_gen2::@1/sin16s_gen2::ampl#3 )
  sin16s_gen2::x#2 = phi( sin16s_gen2::@1/sin16s_gen2::x#4 )
  sin16s::x#0 = sin16s_gen2::x#2
  call sin16s
  sin16s::return#0 = sin16s::return#2
  to:sin16s_gen2::@4
sin16s_gen2::@4: scope:[sin16s_gen2]  from sin16s_gen2::@2
  rem16u#30 = phi( sin16s_gen2::@2/rem16u#32 )
  sin16s_gen2::wavelength#5 = phi( sin16s_gen2::@2/sin16s_gen2::wavelength#6 )
  sin16s_gen2::i#4 = phi( sin16s_gen2::@2/sin16s_gen2::i#5 )
  sin16s_gen2::step#2 = phi( sin16s_gen2::@2/sin16s_gen2::step#3 )
  sin16s_gen2::x#5 = phi( sin16s_gen2::@2/sin16s_gen2::x#2 )
  sin16s_gen2::sintab#3 = phi( sin16s_gen2::@2/sin16s_gen2::sintab#4 )
  sin16s_gen2::offs#2 = phi( sin16s_gen2::@2/sin16s_gen2::offs#3 )
  sin16s_gen2::ampl#1 = phi( sin16s_gen2::@2/sin16s_gen2::ampl#2 )
  sin16s::return#3 = phi( sin16s_gen2::@2/sin16s::return#0 )
  sin16s_gen2::$5 = sin16s::return#3
  mul16s::a#0 = sin16s_gen2::$5
  mul16s::b#0 = sin16s_gen2::ampl#1
  call mul16s
  mul16s::return#0 = mul16s::return#2
  to:sin16s_gen2::@5
sin16s_gen2::@5: scope:[sin16s_gen2]  from sin16s_gen2::@4
  sin16s_gen2::ampl#5 = phi( sin16s_gen2::@4/sin16s_gen2::ampl#1 )
  rem16u#28 = phi( sin16s_gen2::@4/rem16u#30 )
  sin16s_gen2::wavelength#4 = phi( sin16s_gen2::@4/sin16s_gen2::wavelength#5 )
  sin16s_gen2::i#3 = phi( sin16s_gen2::@4/sin16s_gen2::i#4 )
  sin16s_gen2::step#1 = phi( sin16s_gen2::@4/sin16s_gen2::step#2 )
  sin16s_gen2::x#3 = phi( sin16s_gen2::@4/sin16s_gen2::x#5 )
  sin16s_gen2::sintab#2 = phi( sin16s_gen2::@4/sin16s_gen2::sintab#3 )
  sin16s_gen2::offs#1 = phi( sin16s_gen2::@4/sin16s_gen2::offs#2 )
  mul16s::return#3 = phi( sin16s_gen2::@4/mul16s::return#0 )
  sin16s_gen2::$6 = mul16s::return#3
  sin16s_gen2::$7 = word1  sin16s_gen2::$6
  sin16s_gen2::$10 = (int)sin16s_gen2::$7
  sin16s_gen2::$8 = sin16s_gen2::offs#1 + sin16s_gen2::$10
  *sin16s_gen2::sintab#2 = sin16s_gen2::$8
  sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_INT
  sin16s_gen2::$9 = sin16s_gen2::x#3 + sin16s_gen2::step#1
  sin16s_gen2::x#1 = sin16s_gen2::$9
  sin16s_gen2::i#1 = ++ sin16s_gen2::i#3
  to:sin16s_gen2::@1
sin16s_gen2::@return: scope:[sin16s_gen2]  from sin16s_gen2::@1
  rem16u#13 = phi( sin16s_gen2::@1/rem16u#23 )
  rem16u#1 = rem16u#13
  return 
  to:@return

int sin16s(unsigned long x)
sin16s: scope:[sin16s]  from sin16s_gen2::@2
  sin16s::x#3 = phi( sin16s_gen2::@2/sin16s::x#0 )
  sin16s::isUpper#0 = 0
  sin16s::$0 = sin16s::x#3 >= PI_u4f28
  sin16s::$1 = ! sin16s::$0
  if(sin16s::$1) goto sin16s::@1
  to:sin16s::@4
sin16s::@1: scope:[sin16s]  from sin16s sin16s::@4
  sin16s::isUpper#8 = phi( sin16s/sin16s::isUpper#0, sin16s::@4/sin16s::isUpper#1 )
  sin16s::x#4 = phi( sin16s/sin16s::x#3, sin16s::@4/sin16s::x#1 )
  sin16s::$2 = sin16s::x#4 >= PI_HALF_u4f28
  sin16s::$3 = ! sin16s::$2
  if(sin16s::$3) goto sin16s::@2
  to:sin16s::@5
sin16s::@4: scope:[sin16s]  from sin16s
  sin16s::x#5 = phi( sin16s/sin16s::x#3 )
  sin16s::$16 = sin16s::x#5 - PI_u4f28
  sin16s::x#1 = sin16s::$16
  sin16s::isUpper#1 = 1
  to:sin16s::@1
sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
  sin16s::isUpper#7 = phi( sin16s::@1/sin16s::isUpper#8, sin16s::@5/sin16s::isUpper#9 )
  sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
  sin16s::$4 = sin16s::x#6 << 3
  sin16s::x1#0 = word1  sin16s::$4
  mulu16_sel::v1#0 = sin16s::x1#0
  mulu16_sel::v2#0 = sin16s::x1#0
  mulu16_sel::select#0 = 0
  call mulu16_sel
  mulu16_sel::return#0 = mulu16_sel::return#6
  to:sin16s::@7
sin16s::@7: scope:[sin16s]  from sin16s::@2
  sin16s::isUpper#6 = phi( sin16s::@2/sin16s::isUpper#7 )
  sin16s::x1#1 = phi( sin16s::@2/sin16s::x1#0 )
  mulu16_sel::return#7 = phi( sin16s::@2/mulu16_sel::return#0 )
  sin16s::x2#0 = mulu16_sel::return#7
  mulu16_sel::v1#1 = sin16s::x2#0
  mulu16_sel::v2#1 = sin16s::x1#1
  mulu16_sel::select#1 = 1
  call mulu16_sel
  mulu16_sel::return#1 = mulu16_sel::return#6
  to:sin16s::@8
sin16s::@8: scope:[sin16s]  from sin16s::@7
  sin16s::isUpper#5 = phi( sin16s::@7/sin16s::isUpper#6 )
  sin16s::x1#4 = phi( sin16s::@7/sin16s::x1#1 )
  mulu16_sel::return#8 = phi( sin16s::@7/mulu16_sel::return#1 )
  sin16s::x3#0 = mulu16_sel::return#8
  mulu16_sel::v1#2 = sin16s::x3#0
  mulu16_sel::v2#2 = $10000/6
  mulu16_sel::select#2 = 1
  call mulu16_sel
  mulu16_sel::return#2 = mulu16_sel::return#6
  to:sin16s::@9
sin16s::@9: scope:[sin16s]  from sin16s::@8
  sin16s::isUpper#4 = phi( sin16s::@8/sin16s::isUpper#5 )
  sin16s::x3#1 = phi( sin16s::@8/sin16s::x3#0 )
  sin16s::x1#2 = phi( sin16s::@8/sin16s::x1#4 )
  mulu16_sel::return#9 = phi( sin16s::@8/mulu16_sel::return#2 )
  sin16s::x3_6#0 = mulu16_sel::return#9
  sin16s::usinx#0 = sin16s::x1#2 - sin16s::x3_6#0
  mulu16_sel::v1#3 = sin16s::x3#1
  mulu16_sel::v2#3 = sin16s::x1#2
  mulu16_sel::select#3 = 0
  call mulu16_sel
  mulu16_sel::return#3 = mulu16_sel::return#6
  to:sin16s::@10
sin16s::@10: scope:[sin16s]  from sin16s::@9
  sin16s::isUpper#3 = phi( sin16s::@9/sin16s::isUpper#4 )
  sin16s::usinx#4 = phi( sin16s::@9/sin16s::usinx#0 )
  sin16s::x1#3 = phi( sin16s::@9/sin16s::x1#2 )
  mulu16_sel::return#10 = phi( sin16s::@9/mulu16_sel::return#3 )
  sin16s::x4#0 = mulu16_sel::return#10
  mulu16_sel::v1#4 = sin16s::x4#0
  mulu16_sel::v2#4 = sin16s::x1#3
  mulu16_sel::select#4 = 0
  call mulu16_sel
  mulu16_sel::return#4 = mulu16_sel::return#6
  to:sin16s::@11
sin16s::@11: scope:[sin16s]  from sin16s::@10
  sin16s::isUpper#2 = phi( sin16s::@10/sin16s::isUpper#3 )
  sin16s::usinx#2 = phi( sin16s::@10/sin16s::usinx#4 )
  mulu16_sel::return#11 = phi( sin16s::@10/mulu16_sel::return#4 )
  sin16s::x5#0 = mulu16_sel::return#11
  sin16s::x5_128#0 = sin16s::x5#0 >> 4
  sin16s::$13 = sin16s::usinx#2 + sin16s::x5_128#0
  sin16s::usinx#1 = sin16s::$13
  sin16s::sinx#0 = (int)sin16s::usinx#1
  sin16s::$14 = sin16s::isUpper#2 != 0
  sin16s::$15 = ! sin16s::$14
  if(sin16s::$15) goto sin16s::@3
  to:sin16s::@6
sin16s::@5: scope:[sin16s]  from sin16s::@1
  sin16s::isUpper#9 = phi( sin16s::@1/sin16s::isUpper#8 )
  sin16s::x#7 = phi( sin16s::@1/sin16s::x#4 )
  sin16s::$17 = PI_u4f28 - sin16s::x#7
  sin16s::x#2 = sin16s::$17
  to:sin16s::@2
sin16s::@3: scope:[sin16s]  from sin16s::@11 sin16s::@6
  sin16s::sinx#2 = phi( sin16s::@11/sin16s::sinx#0, sin16s::@6/sin16s::sinx#1 )
  sin16s::return#1 = sin16s::sinx#2
  to:sin16s::@return
sin16s::@6: scope:[sin16s]  from sin16s::@11
  sin16s::usinx#3 = phi( sin16s::@11/sin16s::usinx#1 )
  sin16s::$18 = - (int)sin16s::usinx#3
  sin16s::sinx#1 = sin16s::$18
  to:sin16s::@3
sin16s::@return: scope:[sin16s]  from sin16s::@3
  sin16s::return#4 = phi( sin16s::@3/sin16s::return#1 )
  sin16s::return#2 = sin16s::return#4
  return 
  to:@return

unsigned int mulu16_sel(unsigned int v1 , unsigned int v2 , char select)
mulu16_sel: scope:[mulu16_sel]  from sin16s::@10 sin16s::@2 sin16s::@7 sin16s::@8 sin16s::@9
  mulu16_sel::select#6 = phi( sin16s::@10/mulu16_sel::select#4, sin16s::@2/mulu16_sel::select#0, sin16s::@7/mulu16_sel::select#1, sin16s::@8/mulu16_sel::select#2, sin16s::@9/mulu16_sel::select#3 )
  mulu16_sel::v2#5 = phi( sin16s::@10/mulu16_sel::v2#4, sin16s::@2/mulu16_sel::v2#0, sin16s::@7/mulu16_sel::v2#1, sin16s::@8/mulu16_sel::v2#2, sin16s::@9/mulu16_sel::v2#3 )
  mulu16_sel::v1#5 = phi( sin16s::@10/mulu16_sel::v1#4, sin16s::@2/mulu16_sel::v1#0, sin16s::@7/mulu16_sel::v1#1, sin16s::@8/mulu16_sel::v1#2, sin16s::@9/mulu16_sel::v1#3 )
  mul16u::a#0 = mulu16_sel::v1#5
  mul16u::b#0 = mulu16_sel::v2#5
  call mul16u
  mul16u::return#0 = mul16u::return#2
  to:mulu16_sel::@1
mulu16_sel::@1: scope:[mulu16_sel]  from mulu16_sel
  mulu16_sel::select#5 = phi( mulu16_sel/mulu16_sel::select#6 )
  mul16u::return#4 = phi( mulu16_sel/mul16u::return#0 )
  mulu16_sel::$0 = mul16u::return#4
  mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
  mulu16_sel::$2 = word1  mulu16_sel::$1
  mulu16_sel::return#5 = mulu16_sel::$2
  to:mulu16_sel::@return
mulu16_sel::@return: scope:[mulu16_sel]  from mulu16_sel::@1
  mulu16_sel::return#12 = phi( mulu16_sel::@1/mulu16_sel::return#5 )
  mulu16_sel::return#6 = mulu16_sel::return#12
  return 
  to:@return

unsigned int divr16u(unsigned int dividend , unsigned int divisor , unsigned int rem)
divr16u: scope:[divr16u]  from div32u16u div32u16u::@1
  divr16u::divisor#6 = phi( div32u16u/divr16u::divisor#0, div32u16u::@1/divr16u::divisor#1 )
  divr16u::dividend#5 = phi( div32u16u/divr16u::dividend#1, div32u16u::@1/divr16u::dividend#2 )
  divr16u::rem#10 = phi( div32u16u/divr16u::rem#3, div32u16u::@1/divr16u::rem#4 )
  divr16u::quotient#0 = 0
  divr16u::i#0 = 0
  to:divr16u::@1
divr16u::@1: scope:[divr16u]  from divr16u divr16u::@3
  divr16u::i#5 = phi( divr16u/divr16u::i#0, divr16u::@3/divr16u::i#1 )
  divr16u::divisor#4 = phi( divr16u/divr16u::divisor#6, divr16u::@3/divr16u::divisor#7 )
  divr16u::quotient#6 = phi( divr16u/divr16u::quotient#0, divr16u::@3/divr16u::quotient#8 )
  divr16u::dividend#3 = phi( divr16u/divr16u::dividend#5, divr16u::@3/divr16u::dividend#6 )
  divr16u::rem#5 = phi( divr16u/divr16u::rem#10, divr16u::@3/divr16u::rem#11 )
  divr16u::$0 = divr16u::rem#5 << 1
  divr16u::rem#0 = divr16u::$0
  divr16u::$1 = byte1  divr16u::dividend#3
  divr16u::$2 = divr16u::$1 & $80
  divr16u::$3 = divr16u::$2 != 0
  divr16u::$4 = ! divr16u::$3
  if(divr16u::$4) goto divr16u::@2
  to:divr16u::@4
divr16u::@2: scope:[divr16u]  from divr16u::@1 divr16u::@4
  divr16u::i#3 = phi( divr16u::@1/divr16u::i#5, divr16u::@4/divr16u::i#6 )
  divr16u::divisor#2 = phi( divr16u::@1/divr16u::divisor#4, divr16u::@4/divr16u::divisor#5 )
  divr16u::rem#6 = phi( divr16u::@1/divr16u::rem#0, divr16u::@4/divr16u::rem#1 )
  divr16u::quotient#3 = phi( divr16u::@1/divr16u::quotient#6, divr16u::@4/divr16u::quotient#7 )
  divr16u::dividend#4 = phi( divr16u::@1/divr16u::dividend#3, divr16u::@4/divr16u::dividend#7 )
  divr16u::$6 = divr16u::dividend#4 << 1
  divr16u::dividend#0 = divr16u::$6
  divr16u::$7 = divr16u::quotient#3 << 1
  divr16u::quotient#1 = divr16u::$7
  divr16u::$8 = divr16u::rem#6 >= divr16u::divisor#2
  divr16u::$9 = ! divr16u::$8
  if(divr16u::$9) goto divr16u::@3
  to:divr16u::@5
divr16u::@4: scope:[divr16u]  from divr16u::@1
  divr16u::i#6 = phi( divr16u::@1/divr16u::i#5 )
  divr16u::divisor#5 = phi( divr16u::@1/divr16u::divisor#4 )
  divr16u::quotient#7 = phi( divr16u::@1/divr16u::quotient#6 )
  divr16u::dividend#7 = phi( divr16u::@1/divr16u::dividend#3 )
  divr16u::rem#7 = phi( divr16u::@1/divr16u::rem#0 )
  divr16u::$5 = divr16u::rem#7 | 1
  divr16u::rem#1 = divr16u::$5
  to:divr16u::@2
divr16u::@3: scope:[divr16u]  from divr16u::@2 divr16u::@5
  divr16u::divisor#7 = phi( divr16u::@2/divr16u::divisor#2, divr16u::@5/divr16u::divisor#3 )
  divr16u::quotient#8 = phi( divr16u::@2/divr16u::quotient#1, divr16u::@5/divr16u::quotient#2 )
  divr16u::dividend#6 = phi( divr16u::@2/divr16u::dividend#0, divr16u::@5/divr16u::dividend#8 )
  divr16u::rem#11 = phi( divr16u::@2/divr16u::rem#6, divr16u::@5/divr16u::rem#2 )
  divr16u::i#2 = phi( divr16u::@2/divr16u::i#3, divr16u::@5/divr16u::i#4 )
  divr16u::i#1 = divr16u::i#2 + rangenext(0,$f)
  divr16u::$11 = divr16u::i#1 != rangelast(0,$f)
  if(divr16u::$11) goto divr16u::@1
  to:divr16u::@6
divr16u::@5: scope:[divr16u]  from divr16u::@2
  divr16u::dividend#8 = phi( divr16u::@2/divr16u::dividend#0 )
  divr16u::i#4 = phi( divr16u::@2/divr16u::i#3 )
  divr16u::divisor#3 = phi( divr16u::@2/divr16u::divisor#2 )
  divr16u::rem#8 = phi( divr16u::@2/divr16u::rem#6 )
  divr16u::quotient#4 = phi( divr16u::@2/divr16u::quotient#1 )
  divr16u::quotient#2 = ++ divr16u::quotient#4
  divr16u::$10 = divr16u::rem#8 - divr16u::divisor#3
  divr16u::rem#2 = divr16u::$10
  to:divr16u::@3
divr16u::@6: scope:[divr16u]  from divr16u::@3
  divr16u::quotient#5 = phi( divr16u::@3/divr16u::quotient#8 )
  divr16u::rem#9 = phi( divr16u::@3/divr16u::rem#11 )
  rem16u#2 = divr16u::rem#9
  divr16u::return#0 = divr16u::quotient#5
  to:divr16u::@return
divr16u::@return: scope:[divr16u]  from divr16u::@6
  rem16u#14 = phi( divr16u::@6/rem16u#2 )
  divr16u::return#4 = phi( divr16u::@6/divr16u::return#0 )
  divr16u::return#1 = divr16u::return#4
  rem16u#3 = rem16u#14
  return 
  to:@return

unsigned long div32u16u(unsigned long dividend , unsigned int divisor)
div32u16u: scope:[div32u16u]  from sin16s_gen2
  rem16u#24 = phi( sin16s_gen2/rem16u#22 )
  div32u16u::divisor#1 = phi( sin16s_gen2/div32u16u::divisor#0 )
  div32u16u::dividend#1 = phi( sin16s_gen2/div32u16u::dividend#0 )
  div32u16u::$0 = word1  div32u16u::dividend#1
  divr16u::dividend#1 = div32u16u::$0
  divr16u::divisor#0 = div32u16u::divisor#1
  divr16u::rem#3 = 0
  call divr16u
  divr16u::return#2 = divr16u::return#1
  to:div32u16u::@1
div32u16u::@1: scope:[div32u16u]  from div32u16u
  div32u16u::divisor#2 = phi( div32u16u/div32u16u::divisor#1 )
  div32u16u::dividend#2 = phi( div32u16u/div32u16u::dividend#1 )
  rem16u#15 = phi( div32u16u/rem16u#3 )
  divr16u::return#5 = phi( div32u16u/divr16u::return#2 )
  div32u16u::quotient_hi#0 = divr16u::return#5
  rem16u#4 = rem16u#15
  div32u16u::$2 = word0  div32u16u::dividend#2
  divr16u::dividend#2 = div32u16u::$2
  divr16u::divisor#1 = div32u16u::divisor#2
  divr16u::rem#4 = rem16u#4
  call divr16u
  divr16u::return#3 = divr16u::return#1
  to:div32u16u::@2
div32u16u::@2: scope:[div32u16u]  from div32u16u::@1
  div32u16u::quotient_hi#1 = phi( div32u16u::@1/div32u16u::quotient_hi#0 )
  rem16u#16 = phi( div32u16u::@1/rem16u#3 )
  divr16u::return#6 = phi( div32u16u::@1/divr16u::return#3 )
  div32u16u::quotient_lo#0 = divr16u::return#6
  rem16u#5 = rem16u#16
  div32u16u::quotient#0 = div32u16u::quotient_hi#1 dw= div32u16u::quotient_lo#0
  div32u16u::return#1 = div32u16u::quotient#0
  to:div32u16u::@return
div32u16u::@return: scope:[div32u16u]  from div32u16u::@2
  rem16u#17 = phi( div32u16u::@2/rem16u#5 )
  div32u16u::return#4 = phi( div32u16u::@2/div32u16u::return#1 )
  div32u16u::return#2 = div32u16u::return#4
  rem16u#6 = rem16u#17
  return 
  to:@return

unsigned long mul16u(unsigned int a , unsigned int b)
mul16u: scope:[mul16u]  from mul16s mulu16_sel
  mul16u::a#6 = phi( mul16s/mul16u::a#2, mulu16_sel/mul16u::a#0 )
  mul16u::b#2 = phi( mul16s/mul16u::b#1, mulu16_sel/mul16u::b#0 )
  mul16u::res#0 = 0
  mul16u::mb#0 = (unsigned long)mul16u::b#2
  to:mul16u::@1
mul16u::@1: scope:[mul16u]  from mul16u mul16u::@4
  mul16u::mb#5 = phi( mul16u/mul16u::mb#0, mul16u::@4/mul16u::mb#1 )
  mul16u::res#4 = phi( mul16u/mul16u::res#0, mul16u::@4/mul16u::res#6 )
  mul16u::a#3 = phi( mul16u/mul16u::a#6, mul16u::@4/mul16u::a#1 )
  mul16u::$0 = mul16u::a#3 != 0
  if(mul16u::$0) goto mul16u::@2
  to:mul16u::@3
mul16u::@2: scope:[mul16u]  from mul16u::@1
  mul16u::res#5 = phi( mul16u::@1/mul16u::res#4 )
  mul16u::mb#4 = phi( mul16u::@1/mul16u::mb#5 )
  mul16u::a#4 = phi( mul16u::@1/mul16u::a#3 )
  mul16u::$1 = mul16u::a#4 & 1
  mul16u::$2 = mul16u::$1 != 0
  mul16u::$3 = ! mul16u::$2
  if(mul16u::$3) goto mul16u::@4
  to:mul16u::@5
mul16u::@3: scope:[mul16u]  from mul16u::@1
  mul16u::res#2 = phi( mul16u::@1/mul16u::res#4 )
  mul16u::return#1 = mul16u::res#2
  to:mul16u::@return
mul16u::@4: scope:[mul16u]  from mul16u::@2 mul16u::@5
  mul16u::res#6 = phi( mul16u::@2/mul16u::res#5, mul16u::@5/mul16u::res#1 )
  mul16u::mb#2 = phi( mul16u::@2/mul16u::mb#4, mul16u::@5/mul16u::mb#3 )
  mul16u::a#5 = phi( mul16u::@2/mul16u::a#4, mul16u::@5/mul16u::a#7 )
  mul16u::$5 = mul16u::a#5 >> 1
  mul16u::a#1 = mul16u::$5
  mul16u::$6 = mul16u::mb#2 << 1
  mul16u::mb#1 = mul16u::$6
  to:mul16u::@1
mul16u::@5: scope:[mul16u]  from mul16u::@2
  mul16u::a#7 = phi( mul16u::@2/mul16u::a#4 )
  mul16u::mb#3 = phi( mul16u::@2/mul16u::mb#4 )
  mul16u::res#3 = phi( mul16u::@2/mul16u::res#5 )
  mul16u::$4 = mul16u::res#3 + mul16u::mb#3
  mul16u::res#1 = mul16u::$4
  to:mul16u::@4
mul16u::@return: scope:[mul16u]  from mul16u::@3
  mul16u::return#5 = phi( mul16u::@3/mul16u::return#1 )
  mul16u::return#2 = mul16u::return#5
  return 
  to:@return

long mul16s(int a , int b)
mul16s: scope:[mul16s]  from sin16s_gen2::@4
  mul16s::b#1 = phi( sin16s_gen2::@4/mul16s::b#0 )
  mul16s::a#1 = phi( sin16s_gen2::@4/mul16s::a#0 )
  mul16u::a#2 = (unsigned int)mul16s::a#1
  mul16u::b#1 = (unsigned int)mul16s::b#1
  call mul16u
  mul16u::return#3 = mul16u::return#2
  to:mul16s::@5
mul16s::@5: scope:[mul16s]  from mul16s
  mul16s::b#4 = phi( mul16s/mul16s::b#1 )
  mul16s::a#2 = phi( mul16s/mul16s::a#1 )
  mul16u::return#6 = phi( mul16s/mul16u::return#3 )
  mul16s::m#0 = mul16u::return#6
  mul16s::$1 = mul16s::a#2 < 0
  mul16s::$2 = ! mul16s::$1
  if(mul16s::$2) goto mul16s::@1
  to:mul16s::@3
mul16s::@1: scope:[mul16s]  from mul16s::@3 mul16s::@5
  mul16s::a#4 = phi( mul16s::@3/mul16s::a#5, mul16s::@5/mul16s::a#2 )
  mul16s::m#6 = phi( mul16s::@3/mul16s::m#1, mul16s::@5/mul16s::m#0 )
  mul16s::b#2 = phi( mul16s::@3/mul16s::b#3, mul16s::@5/mul16s::b#4 )
  mul16s::$3 = mul16s::b#2 < 0
  mul16s::$4 = ! mul16s::$3
  if(mul16s::$4) goto mul16s::@2
  to:mul16s::@4
mul16s::@3: scope:[mul16s]  from mul16s::@5
  mul16s::a#5 = phi( mul16s::@5/mul16s::a#2 )
  mul16s::b#3 = phi( mul16s::@5/mul16s::b#4 )
  mul16s::m#3 = phi( mul16s::@5/mul16s::m#0 )
  mul16s::$6 = word1  mul16s::m#3
  mul16s::$13 = (unsigned int)mul16s::b#3
  mul16s::$7 = mul16s::$6 - mul16s::$13
  mul16s::$11 = mul16s::$7
  mul16s::m#1 = mul16s::m#3 word1= mul16s::$11
  to:mul16s::@1
mul16s::@2: scope:[mul16s]  from mul16s::@1 mul16s::@4
  mul16s::m#4 = phi( mul16s::@1/mul16s::m#6, mul16s::@4/mul16s::m#2 )
  mul16s::return#1 = (long)mul16s::m#4
  to:mul16s::@return
mul16s::@4: scope:[mul16s]  from mul16s::@1
  mul16s::a#3 = phi( mul16s::@1/mul16s::a#4 )
  mul16s::m#5 = phi( mul16s::@1/mul16s::m#6 )
  mul16s::$9 = word1  mul16s::m#5
  mul16s::$14 = (unsigned int)mul16s::a#3
  mul16s::$10 = mul16s::$9 - mul16s::$14
  mul16s::$12 = mul16s::$10
  mul16s::m#2 = mul16s::m#5 word1= mul16s::$12
  to:mul16s::@2
mul16s::@return: scope:[mul16s]  from mul16s::@2
  mul16s::return#4 = phi( mul16s::@2/mul16s::return#1 )
  mul16s::return#2 = mul16s::return#4
  return 
  to:@return

void * memset(void *str , char c , unsigned int num)
memset: scope:[memset]  from main::@3 main::@4
  memset::c#5 = phi( main::@3/memset::c#0, main::@4/memset::c#1 )
  memset::str#4 = phi( main::@3/memset::str#0, main::@4/memset::str#1 )
  memset::num#2 = phi( main::@3/memset::num#0, main::@4/memset::num#1 )
  memset::$0 = memset::num#2 > 0
  memset::$1 = ! memset::$0
  if(memset::$1) goto memset::@1
  to:memset::@2
memset::@1: scope:[memset]  from memset memset::@3
  memset::str#2 = phi( memset/memset::str#4, memset::@3/memset::str#5 )
  memset::return#0 = memset::str#2
  to:memset::@return
memset::@2: scope:[memset]  from memset
  memset::c#4 = phi( memset/memset::c#5 )
  memset::num#3 = phi( memset/memset::num#2 )
  memset::str#3 = phi( memset/memset::str#4 )
  memset::$4 = (char *)memset::str#3
  memset::end#0 = memset::$4 + memset::num#3
  memset::dst#0 = ((char *)) memset::str#3
  to:memset::@3
memset::@3: scope:[memset]  from memset::@2 memset::@4
  memset::c#3 = phi( memset::@2/memset::c#4, memset::@4/memset::c#2 )
  memset::str#5 = phi( memset::@2/memset::str#3, memset::@4/memset::str#6 )
  memset::end#1 = phi( memset::@2/memset::end#0, memset::@4/memset::end#2 )
  memset::dst#2 = phi( memset::@2/memset::dst#0, memset::@4/memset::dst#1 )
  memset::$3 = memset::dst#2 != memset::end#1
  if(memset::$3) goto memset::@4
  to:memset::@1
memset::@4: scope:[memset]  from memset::@3
  memset::str#6 = phi( memset::@3/memset::str#5 )
  memset::end#2 = phi( memset::@3/memset::end#1 )
  memset::dst#3 = phi( memset::@3/memset::dst#2 )
  memset::c#2 = phi( memset::@3/memset::c#3 )
  *memset::dst#3 = memset::c#2
  memset::dst#1 = ++ memset::dst#3
  to:memset::@3
memset::@return: scope:[memset]  from memset::@1
  memset::return#4 = phi( memset::@1/memset::return#0 )
  memset::return#1 = memset::return#4
  return 
  to:@return

void main()
main: scope:[main]  from __start::@1
  xsin_idx#28 = phi( __start::@1/xsin_idx#18 )
  rem16u#37 = phi( __start::@1/rem16u#27 )
  asm { sei  }
  *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = WHITE
  *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) = DARK_GREY
  *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR) = *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1)
  *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2) = BLACK
  main::toD0181_screen#0 = SCREEN
  main::toD0181_gfx#0 = LOGO
  to:main::toD0181
main::toD0181: scope:[main]  from main
  xsin_idx#27 = phi( main/xsin_idx#28 )
  rem16u#36 = phi( main/rem16u#37 )
  main::toD0181_gfx#1 = phi( main/main::toD0181_gfx#0 )
  main::toD0181_screen#1 = phi( main/main::toD0181_screen#0 )
  main::toD0181_$7 = (unsigned int)main::toD0181_screen#1
  main::toD0181_$0 = main::toD0181_$7 & $3fff
  main::toD0181_$1 = main::toD0181_$0 * 4
  main::toD0181_$2 = byte1  main::toD0181_$1
  main::toD0181_$3 = byte1  (unsigned int)main::toD0181_gfx#1
  main::toD0181_$4 = main::toD0181_$3 / 4
  main::toD0181_$5 = main::toD0181_$4 & $f
  main::toD0181_$6 = main::toD0181_$2 | main::toD0181_$5
  main::toD0181_return#0 = main::toD0181_$6
  to:main::toD0181_@return
main::toD0181_@return: scope:[main]  from main::toD0181
  xsin_idx#26 = phi( main::toD0181/xsin_idx#27 )
  rem16u#35 = phi( main::toD0181/rem16u#36 )
  main::toD0181_return#2 = phi( main::toD0181/main::toD0181_return#0 )
  main::toD0181_return#1 = main::toD0181_return#2
  to:main::@3
main::@3: scope:[main]  from main::toD0181_@return
  xsin_idx#25 = phi( main::toD0181_@return/xsin_idx#26 )
  rem16u#34 = phi( main::toD0181_@return/rem16u#35 )
  main::toD0181_return#3 = phi( main::toD0181_@return/main::toD0181_return#1 )
  main::$0 = main::toD0181_return#3
  *D018 = main::$0
  *D016 = VICII_MCM
  memset::str#0 = (void *)SCREEN
  memset::c#0 = BLACK
  memset::num#0 = $3e8
  call memset
  memset::return#2 = memset::return#1
  to:main::@4
main::@4: scope:[main]  from main::@3
  xsin_idx#24 = phi( main::@3/xsin_idx#25 )
  rem16u#33 = phi( main::@3/rem16u#34 )
  memset::str#1 = (void *)COLS
  memset::c#1 = WHITE|8
  memset::num#1 = $3e8
  call memset
  memset::return#3 = memset::return#1
  to:main::@5
main::@5: scope:[main]  from main::@4
  xsin_idx#23 = phi( main::@4/xsin_idx#24 )
  rem16u#31 = phi( main::@4/rem16u#33 )
  main::ch#0 = 0
  to:main::@1
main::@1: scope:[main]  from main::@1 main::@5
  xsin_idx#22 = phi( main::@1/xsin_idx#22, main::@5/xsin_idx#23 )
  rem16u#29 = phi( main::@1/rem16u#29, main::@5/rem16u#31 )
  main::ch#2 = phi( main::@1/main::ch#1, main::@5/main::ch#0 )
  SCREEN[main::ch#2] = main::ch#2
  main::ch#1 = main::ch#2 + rangenext(0,$ef)
  main::$5 = main::ch#1 != rangelast(0,$ef)
  if(main::$5) goto main::@1
  to:main::@2
main::@2: scope:[main]  from main::@1
  xsin_idx#19 = phi( main::@1/xsin_idx#22 )
  rem16u#25 = phi( main::@1/rem16u#29 )
  sin16s_gen2::sintab#1 = xsin
  sin16s_gen2::wavelength#0 = XSIN_SIZE
  sin16s_gen2::min#0 = -$140
  sin16s_gen2::max#0 = $140
  call sin16s_gen2
  to:main::@6
main::@6: scope:[main]  from main::@2
  xsin_idx#15 = phi( main::@2/xsin_idx#19 )
  rem16u#18 = phi( main::@2/rem16u#1 )
  rem16u#7 = rem16u#18
  call loop
  to:main::@7
main::@7: scope:[main]  from main::@6
  rem16u#26 = phi( main::@6/rem16u#7 )
  xsin_idx#8 = phi( main::@6/xsin_idx#4 )
  xsin_idx#0 = xsin_idx#8
  to:main::@return
main::@return: scope:[main]  from main::@7
  xsin_idx#9 = phi( main::@7/xsin_idx#0 )
  rem16u#19 = phi( main::@7/rem16u#26 )
  rem16u#8 = rem16u#19
  xsin_idx#1 = xsin_idx#9
  return 
  to:@return

void loop()
loop: scope:[loop]  from main::@6
  xsin_idx#20 = phi( main::@6/xsin_idx#15 )
  to:loop::@1
loop::@1: scope:[loop]  from loop loop::@5
  xsin_idx#17 = phi( loop/xsin_idx#20, loop::@5/xsin_idx#21 )
  if(true) goto loop::@2
  to:loop::@return
loop::@2: scope:[loop]  from loop::@1 loop::@2
  xsin_idx#16 = phi( loop::@1/xsin_idx#17, loop::@2/xsin_idx#16 )
  loop::$0 = *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER) != $ff
  if(loop::$0) goto loop::@2
  to:loop::@3
loop::@3: scope:[loop]  from loop::@2
  xsin_idx#10 = phi( loop::@2/xsin_idx#16 )
  *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = ++ *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR)
  loop::$7 = xsin_idx#10 * SIZEOF_INT
  loop::$2 = xsin + loop::$7
  loop::xpos#0 = *loop::$2
  render_logo::xpos#0 = loop::xpos#0
  call render_logo
  to:loop::@6
loop::@6: scope:[loop]  from loop::@3
  xsin_idx#11 = phi( loop::@3/xsin_idx#10 )
  xsin_idx#2 = ++ xsin_idx#11
  loop::$4 = xsin_idx#2 == XSIN_SIZE
  loop::$5 = ! loop::$4
  if(loop::$5) goto loop::@5
  to:loop::@4
loop::@5: scope:[loop]  from loop::@4 loop::@6
  xsin_idx#21 = phi( loop::@4/xsin_idx#3, loop::@6/xsin_idx#2 )
  *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = -- *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR)
  to:loop::@1
loop::@4: scope:[loop]  from loop::@6
  xsin_idx#3 = 0
  to:loop::@5
loop::@return: scope:[loop]  from loop::@1
  xsin_idx#12 = phi( loop::@1/xsin_idx#17 )
  xsin_idx#4 = xsin_idx#12
  return 
  to:@return

void render_logo(int xpos)
render_logo: scope:[render_logo]  from loop::@3
  render_logo::xpos#1 = phi( loop::@3/render_logo::xpos#0 )
  render_logo::logo_idx#0 = 0
  render_logo::screen_idx#0 = 0
  render_logo::$25 = (char)render_logo::xpos#1
  render_logo::$0 = render_logo::$25 & 7
  render_logo::$1 = VICII_MCM | render_logo::$0
  *D016 = render_logo::$1
  render_logo::$2 = render_logo::xpos#1 / 8
  render_logo::x_char#0 = (signed char)render_logo::$2
  render_logo::$3 = render_logo::xpos#1 < 0
  if(render_logo::$3) goto render_logo::@1
  to:render_logo::@2
render_logo::@1: scope:[render_logo]  from render_logo
  render_logo::x_char#1 = phi( render_logo/render_logo::x_char#0 )
  render_logo::$14 = - render_logo::x_char#1
  render_logo::logo_idx#1 = (char)render_logo::$14
  render_logo::screen_idx#1 = 0
  to:render_logo::@12
render_logo::@2: scope:[render_logo]  from render_logo
  render_logo::x_char#2 = phi( render_logo/render_logo::x_char#0 )
  render_logo::logo_start#0 = (char)render_logo::x_char#2
  render_logo::screen_idx#2 = 0
  to:render_logo::@3
render_logo::@3: scope:[render_logo]  from render_logo::@2 render_logo::@7
  render_logo::logo_start#1 = phi( render_logo::@2/render_logo::logo_start#0, render_logo::@7/render_logo::logo_start#2 )
  render_logo::screen_idx#7 = phi( render_logo::@2/render_logo::screen_idx#2, render_logo::@7/render_logo::screen_idx#3 )
  render_logo::$4 = render_logo::screen_idx#7 != render_logo::logo_start#1
  if(render_logo::$4) goto render_logo::@4
  to:render_logo::@5
render_logo::@4: scope:[render_logo]  from render_logo::@3
  render_logo::logo_start#4 = phi( render_logo::@3/render_logo::logo_start#1 )
  render_logo::screen_idx#18 = phi( render_logo::@3/render_logo::screen_idx#7 )
  render_logo::line#0 = 0
  to:render_logo::@6
render_logo::@5: scope:[render_logo]  from render_logo::@3
  render_logo::screen_idx#19 = phi( render_logo::@3/render_logo::screen_idx#7 )
  render_logo::logo_idx#2 = 0
  to:render_logo::@8
render_logo::@6: scope:[render_logo]  from render_logo::@4 render_logo::@6
  render_logo::logo_start#3 = phi( render_logo::@4/render_logo::logo_start#4, render_logo::@6/render_logo::logo_start#3 )
  render_logo::screen_idx#8 = phi( render_logo::@4/render_logo::screen_idx#18, render_logo::@6/render_logo::screen_idx#8 )
  render_logo::line#2 = phi( render_logo::@4/render_logo::line#0, render_logo::@6/render_logo::line#1 )
  render_logo::$5 = $28 * render_logo::line#2
  render_logo::$6 = SCREEN + render_logo::$5
  render_logo::$6[render_logo::screen_idx#8] = 0
  render_logo::line#1 = render_logo::line#2 + rangenext(0,5)
  render_logo::$7 = render_logo::line#1 != rangelast(0,5)
  unroll if(render_logo::$7) goto render_logo::@6
  to:render_logo::@7
render_logo::@7: scope:[render_logo]  from render_logo::@6
  render_logo::logo_start#2 = phi( render_logo::@6/render_logo::logo_start#3 )
  render_logo::screen_idx#9 = phi( render_logo::@6/render_logo::screen_idx#8 )
  render_logo::screen_idx#3 = ++ render_logo::screen_idx#9
  to:render_logo::@3
render_logo::@8: scope:[render_logo]  from render_logo::@11 render_logo::@5
  render_logo::logo_idx#12 = phi( render_logo::@11/render_logo::logo_idx#3, render_logo::@5/render_logo::logo_idx#2 )
  render_logo::screen_idx#10 = phi( render_logo::@11/render_logo::screen_idx#4, render_logo::@5/render_logo::screen_idx#19 )
  render_logo::$8 = render_logo::screen_idx#10 != $28
  if(render_logo::$8) goto render_logo::@9
  to:render_logo::@return
render_logo::@9: scope:[render_logo]  from render_logo::@8
  render_logo::screen_idx#20 = phi( render_logo::@8/render_logo::screen_idx#10 )
  render_logo::logo_idx#10 = phi( render_logo::@8/render_logo::logo_idx#12 )
  render_logo::line1#0 = 0
  to:render_logo::@10
render_logo::@10: scope:[render_logo]  from render_logo::@10 render_logo::@9
  render_logo::screen_idx#11 = phi( render_logo::@10/render_logo::screen_idx#11, render_logo::@9/render_logo::screen_idx#20 )
  render_logo::logo_idx#5 = phi( render_logo::@10/render_logo::logo_idx#5, render_logo::@9/render_logo::logo_idx#10 )
  render_logo::line1#2 = phi( render_logo::@10/render_logo::line1#1, render_logo::@9/render_logo::line1#0 )
  render_logo::$9 = $28 * render_logo::line1#2
  render_logo::$10 = SCREEN + render_logo::$9
  render_logo::$11 = $28 * render_logo::line1#2
  render_logo::$12 = render_logo::logo_idx#5 + render_logo::$11
  render_logo::$10[render_logo::screen_idx#11] = render_logo::$12
  render_logo::line1#1 = render_logo::line1#2 + rangenext(0,5)
  render_logo::$13 = render_logo::line1#1 != rangelast(0,5)
  unroll if(render_logo::$13) goto render_logo::@10
  to:render_logo::@11
render_logo::@11: scope:[render_logo]  from render_logo::@10
  render_logo::logo_idx#6 = phi( render_logo::@10/render_logo::logo_idx#5 )
  render_logo::screen_idx#12 = phi( render_logo::@10/render_logo::screen_idx#11 )
  render_logo::screen_idx#4 = ++ render_logo::screen_idx#12
  render_logo::logo_idx#3 = ++ render_logo::logo_idx#6
  to:render_logo::@8
render_logo::@12: scope:[render_logo]  from render_logo::@1 render_logo::@15
  render_logo::screen_idx#22 = phi( render_logo::@1/render_logo::screen_idx#1, render_logo::@15/render_logo::screen_idx#5 )
  render_logo::logo_idx#7 = phi( render_logo::@1/render_logo::logo_idx#1, render_logo::@15/render_logo::logo_idx#4 )
  render_logo::$15 = render_logo::logo_idx#7 != $28
  if(render_logo::$15) goto render_logo::@13
  to:render_logo::@16
render_logo::@13: scope:[render_logo]  from render_logo::@12
  render_logo::screen_idx#21 = phi( render_logo::@12/render_logo::screen_idx#22 )
  render_logo::logo_idx#11 = phi( render_logo::@12/render_logo::logo_idx#7 )
  render_logo::line2#0 = 0
  to:render_logo::@14
render_logo::@14: scope:[render_logo]  from render_logo::@13 render_logo::@14
  render_logo::screen_idx#13 = phi( render_logo::@13/render_logo::screen_idx#21, render_logo::@14/render_logo::screen_idx#13 )
  render_logo::logo_idx#8 = phi( render_logo::@13/render_logo::logo_idx#11, render_logo::@14/render_logo::logo_idx#8 )
  render_logo::line2#2 = phi( render_logo::@13/render_logo::line2#0, render_logo::@14/render_logo::line2#1 )
  render_logo::$16 = $28 * render_logo::line2#2
  render_logo::$17 = SCREEN + render_logo::$16
  render_logo::$18 = $28 * render_logo::line2#2
  render_logo::$19 = render_logo::logo_idx#8 + render_logo::$18
  render_logo::$17[render_logo::screen_idx#13] = render_logo::$19
  render_logo::line2#1 = render_logo::line2#2 + rangenext(0,5)
  render_logo::$20 = render_logo::line2#1 != rangelast(0,5)
  unroll if(render_logo::$20) goto render_logo::@14
  to:render_logo::@15
render_logo::@15: scope:[render_logo]  from render_logo::@14
  render_logo::logo_idx#9 = phi( render_logo::@14/render_logo::logo_idx#8 )
  render_logo::screen_idx#14 = phi( render_logo::@14/render_logo::screen_idx#13 )
  render_logo::screen_idx#5 = ++ render_logo::screen_idx#14
  render_logo::logo_idx#4 = ++ render_logo::logo_idx#9
  to:render_logo::@12
render_logo::@16: scope:[render_logo]  from render_logo::@12 render_logo::@19
  render_logo::screen_idx#15 = phi( render_logo::@12/render_logo::screen_idx#22, render_logo::@19/render_logo::screen_idx#6 )
  render_logo::$21 = render_logo::screen_idx#15 != $28
  if(render_logo::$21) goto render_logo::@17
  to:render_logo::@return
render_logo::@17: scope:[render_logo]  from render_logo::@16
  render_logo::screen_idx#23 = phi( render_logo::@16/render_logo::screen_idx#15 )
  render_logo::line3#0 = 0
  to:render_logo::@18
render_logo::@18: scope:[render_logo]  from render_logo::@17 render_logo::@18
  render_logo::screen_idx#16 = phi( render_logo::@17/render_logo::screen_idx#23, render_logo::@18/render_logo::screen_idx#16 )
  render_logo::line3#2 = phi( render_logo::@17/render_logo::line3#0, render_logo::@18/render_logo::line3#1 )
  render_logo::$22 = $28 * render_logo::line3#2
  render_logo::$23 = SCREEN + render_logo::$22
  render_logo::$23[render_logo::screen_idx#16] = 0
  render_logo::line3#1 = render_logo::line3#2 + rangenext(0,5)
  render_logo::$24 = render_logo::line3#1 != rangelast(0,5)
  unroll if(render_logo::$24) goto render_logo::@18
  to:render_logo::@19
render_logo::@19: scope:[render_logo]  from render_logo::@18
  render_logo::screen_idx#17 = phi( render_logo::@18/render_logo::screen_idx#16 )
  render_logo::screen_idx#6 = ++ render_logo::screen_idx#17
  to:render_logo::@16
render_logo::@return: scope:[render_logo]  from render_logo::@16 render_logo::@8
  return 
  to:@return

void __start()
__start: scope:[__start]  from
  to:__start::__init1
__start::__init1: scope:[__start]  from __start
  rem16u#9 = 0
  xsin_idx#5 = 0
  to:__start::@1
__start::@1: scope:[__start]  from __start::__init1
  xsin_idx#18 = phi( __start::__init1/xsin_idx#5 )
  rem16u#27 = phi( __start::__init1/rem16u#9 )
  call main
  to:__start::@2
__start::@2: scope:[__start]  from __start::@1
  xsin_idx#13 = phi( __start::@1/xsin_idx#1 )
  rem16u#20 = phi( __start::@1/rem16u#8 )
  rem16u#10 = rem16u#20
  xsin_idx#6 = xsin_idx#13
  to:__start::@return
__start::@return: scope:[__start]  from __start::@2
  xsin_idx#14 = phi( __start::@2/xsin_idx#6 )
  rem16u#21 = phi( __start::@2/rem16u#10 )
  rem16u#11 = rem16u#21
  xsin_idx#7 = xsin_idx#14
  return 
  to:@return

SYMBOL TABLE SSA
__constant const char BLACK = 0
__constant char * const COLS = (char *)$d800
__constant char * const D016 = (char *)$d016
__constant char * const D018 = (char *)$d018
__constant const char DARK_GREY = $b
__constant char LOGO[6*$28*8] = kickasm {{ .var logoPic = LoadPicture("logo.png", List().add($444444, $808080, $000000, $ffffff))
    .for (var y=0; y<6	; y++)
        .for (var x=0;x<40; x++)
            .for(var cp=0; cp<8; cp++)
                .byte logoPic.getMulticolorByte(x,cp+y*8)
 }}
__constant char OFFSET_STRUCT_MOS6569_VICII_BG_COLOR = $21
__constant char OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1 = $22
__constant char OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2 = $23
__constant char OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR = $20
__constant char OFFSET_STRUCT_MOS6569_VICII_RASTER = $12
__constant const unsigned long PI2_u4f28 = $6487ed51
__constant const unsigned long PI_HALF_u4f28 = $1921fb54
__constant const unsigned long PI_u4f28 = $3243f6a9
__constant char *SCREEN = (char *)$400
__constant char SIZEOF_INT = 2
__constant struct MOS6569_VICII * const VICII = (struct MOS6569_VICII *)$d000
__constant const char VICII_MCM = $10
__constant const char WHITE = 1
__constant const unsigned int XSIN_SIZE = $200
void __start()
unsigned long div32u16u(unsigned long dividend , unsigned int divisor)
unsigned int div32u16u::$0
unsigned int div32u16u::$2
unsigned long div32u16u::dividend
unsigned long div32u16u::dividend#0
unsigned long div32u16u::dividend#1
unsigned long div32u16u::dividend#2
unsigned int div32u16u::divisor
unsigned int div32u16u::divisor#0
unsigned int div32u16u::divisor#1
unsigned int div32u16u::divisor#2
unsigned long div32u16u::quotient
unsigned long div32u16u::quotient#0
unsigned int div32u16u::quotient_hi
unsigned int div32u16u::quotient_hi#0
unsigned int div32u16u::quotient_hi#1
unsigned int div32u16u::quotient_lo
unsigned int div32u16u::quotient_lo#0
unsigned long div32u16u::return
unsigned long div32u16u::return#0
unsigned long div32u16u::return#1
unsigned long div32u16u::return#2
unsigned long div32u16u::return#3
unsigned long div32u16u::return#4
unsigned int divr16u(unsigned int dividend , unsigned int divisor , unsigned int rem)
unsigned int divr16u::$0
char divr16u::$1
unsigned int divr16u::$10
bool divr16u::$11
number divr16u::$2
bool divr16u::$3
bool divr16u::$4
number divr16u::$5
unsigned int divr16u::$6
unsigned int divr16u::$7
bool divr16u::$8
bool divr16u::$9
unsigned int divr16u::dividend
unsigned int divr16u::dividend#0
unsigned int divr16u::dividend#1
unsigned int divr16u::dividend#2
unsigned int divr16u::dividend#3
unsigned int divr16u::dividend#4
unsigned int divr16u::dividend#5
unsigned int divr16u::dividend#6
unsigned int divr16u::dividend#7
unsigned int divr16u::dividend#8
unsigned int divr16u::divisor
unsigned int divr16u::divisor#0
unsigned int divr16u::divisor#1
unsigned int divr16u::divisor#2
unsigned int divr16u::divisor#3
unsigned int divr16u::divisor#4
unsigned int divr16u::divisor#5
unsigned int divr16u::divisor#6
unsigned int divr16u::divisor#7
char divr16u::i
char divr16u::i#0
char divr16u::i#1
char divr16u::i#2
char divr16u::i#3
char divr16u::i#4
char divr16u::i#5
char divr16u::i#6
unsigned int divr16u::quotient
unsigned int divr16u::quotient#0
unsigned int divr16u::quotient#1
unsigned int divr16u::quotient#2
unsigned int divr16u::quotient#3
unsigned int divr16u::quotient#4
unsigned int divr16u::quotient#5
unsigned int divr16u::quotient#6
unsigned int divr16u::quotient#7
unsigned int divr16u::quotient#8
unsigned int divr16u::rem
unsigned int divr16u::rem#0
unsigned int divr16u::rem#1
unsigned int divr16u::rem#10
unsigned int divr16u::rem#11
unsigned int divr16u::rem#2
unsigned int divr16u::rem#3
unsigned int divr16u::rem#4
unsigned int divr16u::rem#5
unsigned int divr16u::rem#6
unsigned int divr16u::rem#7
unsigned int divr16u::rem#8
unsigned int divr16u::rem#9
unsigned int divr16u::return
unsigned int divr16u::return#0
unsigned int divr16u::return#1
unsigned int divr16u::return#2
unsigned int divr16u::return#3
unsigned int divr16u::return#4
unsigned int divr16u::return#5
unsigned int divr16u::return#6
void loop()
bool loop::$0
int *loop::$2
bool loop::$4
bool loop::$5
unsigned int loop::$7
int loop::xpos
int loop::xpos#0
void main()
char main::$0
bool main::$5
char main::ch
char main::ch#0
char main::ch#1
char main::ch#2
number main::toD0181_$0
number main::toD0181_$1
char main::toD0181_$2
char main::toD0181_$3
number main::toD0181_$4
number main::toD0181_$5
number main::toD0181_$6
unsigned int main::toD0181_$7
char *main::toD0181_gfx
char *main::toD0181_gfx#0
char *main::toD0181_gfx#1
char main::toD0181_return
char main::toD0181_return#0
char main::toD0181_return#1
char main::toD0181_return#2
char main::toD0181_return#3
char *main::toD0181_screen
char *main::toD0181_screen#0
char *main::toD0181_screen#1
void * memset(void *str , char c , unsigned int num)
bool memset::$0
bool memset::$1
bool memset::$3
char *memset::$4
char memset::c
char memset::c#0
char memset::c#1
char memset::c#2
char memset::c#3
char memset::c#4
char memset::c#5
char *memset::dst
char *memset::dst#0
char *memset::dst#1
char *memset::dst#2
char *memset::dst#3
char *memset::end
char *memset::end#0
char *memset::end#1
char *memset::end#2
unsigned int memset::num
unsigned int memset::num#0
unsigned int memset::num#1
unsigned int memset::num#2
unsigned int memset::num#3
void *memset::return
void *memset::return#0
void *memset::return#1
void *memset::return#2
void *memset::return#3
void *memset::return#4
void *memset::str
void *memset::str#0
void *memset::str#1
void *memset::str#2
void *memset::str#3
void *memset::str#4
void *memset::str#5
void *memset::str#6
long mul16s(int a , int b)
bool mul16s::$1
unsigned int mul16s::$10
unsigned int mul16s::$11
unsigned int mul16s::$12
unsigned int mul16s::$13
unsigned int mul16s::$14
bool mul16s::$2
bool mul16s::$3
bool mul16s::$4
unsigned int mul16s::$6
unsigned int mul16s::$7
unsigned int mul16s::$9
int mul16s::a
int mul16s::a#0
int mul16s::a#1
int mul16s::a#2
int mul16s::a#3
int mul16s::a#4
int mul16s::a#5
int mul16s::b
int mul16s::b#0
int mul16s::b#1
int mul16s::b#2
int mul16s::b#3
int mul16s::b#4
unsigned long mul16s::m
unsigned long mul16s::m#0
unsigned long mul16s::m#1
unsigned long mul16s::m#2
unsigned long mul16s::m#3
unsigned long mul16s::m#4
unsigned long mul16s::m#5
unsigned long mul16s::m#6
long mul16s::return
long mul16s::return#0
long mul16s::return#1
long mul16s::return#2
long mul16s::return#3
long mul16s::return#4
unsigned long mul16u(unsigned int a , unsigned int b)
bool mul16u::$0
number mul16u::$1
bool mul16u::$2
bool mul16u::$3
unsigned long mul16u::$4
unsigned int mul16u::$5
unsigned long mul16u::$6
unsigned int mul16u::a
unsigned int mul16u::a#0
unsigned int mul16u::a#1
unsigned int mul16u::a#2
unsigned int mul16u::a#3
unsigned int mul16u::a#4
unsigned int mul16u::a#5
unsigned int mul16u::a#6
unsigned int mul16u::a#7
unsigned int mul16u::b
unsigned int mul16u::b#0
unsigned int mul16u::b#1
unsigned int mul16u::b#2
unsigned long mul16u::mb
unsigned long mul16u::mb#0
unsigned long mul16u::mb#1
unsigned long mul16u::mb#2
unsigned long mul16u::mb#3
unsigned long mul16u::mb#4
unsigned long mul16u::mb#5
unsigned long mul16u::res
unsigned long mul16u::res#0
unsigned long mul16u::res#1
unsigned long mul16u::res#2
unsigned long mul16u::res#3
unsigned long mul16u::res#4
unsigned long mul16u::res#5
unsigned long mul16u::res#6
unsigned long mul16u::return
unsigned long mul16u::return#0
unsigned long mul16u::return#1
unsigned long mul16u::return#2
unsigned long mul16u::return#3
unsigned long mul16u::return#4
unsigned long mul16u::return#5
unsigned long mul16u::return#6
unsigned int mulu16_sel(unsigned int v1 , unsigned int v2 , char select)
unsigned long mulu16_sel::$0
unsigned long mulu16_sel::$1
unsigned int mulu16_sel::$2
unsigned int mulu16_sel::return
unsigned int mulu16_sel::return#0
unsigned int mulu16_sel::return#1
unsigned int mulu16_sel::return#10
unsigned int mulu16_sel::return#11
unsigned int mulu16_sel::return#12
unsigned int mulu16_sel::return#2
unsigned int mulu16_sel::return#3
unsigned int mulu16_sel::return#4
unsigned int mulu16_sel::return#5
unsigned int mulu16_sel::return#6
unsigned int mulu16_sel::return#7
unsigned int mulu16_sel::return#8
unsigned int mulu16_sel::return#9
char mulu16_sel::select
char mulu16_sel::select#0
char mulu16_sel::select#1
char mulu16_sel::select#2
char mulu16_sel::select#3
char mulu16_sel::select#4
char mulu16_sel::select#5
char mulu16_sel::select#6
unsigned int mulu16_sel::v1
unsigned int mulu16_sel::v1#0
unsigned int mulu16_sel::v1#1
unsigned int mulu16_sel::v1#2
unsigned int mulu16_sel::v1#3
unsigned int mulu16_sel::v1#4
unsigned int mulu16_sel::v1#5
unsigned int mulu16_sel::v2
unsigned int mulu16_sel::v2#0
unsigned int mulu16_sel::v2#1
unsigned int mulu16_sel::v2#2
unsigned int mulu16_sel::v2#3
unsigned int mulu16_sel::v2#4
unsigned int mulu16_sel::v2#5
unsigned int rem16u
unsigned int rem16u#0
unsigned int rem16u#1
unsigned int rem16u#10
unsigned int rem16u#11
unsigned int rem16u#12
unsigned int rem16u#13
unsigned int rem16u#14
unsigned int rem16u#15
unsigned int rem16u#16
unsigned int rem16u#17
unsigned int rem16u#18
unsigned int rem16u#19
unsigned int rem16u#2
unsigned int rem16u#20
unsigned int rem16u#21
unsigned int rem16u#22
unsigned int rem16u#23
unsigned int rem16u#24
unsigned int rem16u#25
unsigned int rem16u#26
unsigned int rem16u#27
unsigned int rem16u#28
unsigned int rem16u#29
unsigned int rem16u#3
unsigned int rem16u#30
unsigned int rem16u#31
unsigned int rem16u#32
unsigned int rem16u#33
unsigned int rem16u#34
unsigned int rem16u#35
unsigned int rem16u#36
unsigned int rem16u#37
unsigned int rem16u#4
unsigned int rem16u#5
unsigned int rem16u#6
unsigned int rem16u#7
unsigned int rem16u#8
unsigned int rem16u#9
void render_logo(int xpos)
number render_logo::$0
number render_logo::$1
char *render_logo::$10
number render_logo::$11
number render_logo::$12
bool render_logo::$13
signed char render_logo::$14
bool render_logo::$15
number render_logo::$16
char *render_logo::$17
number render_logo::$18
number render_logo::$19
number render_logo::$2
bool render_logo::$20
bool render_logo::$21
number render_logo::$22
char *render_logo::$23
bool render_logo::$24
char render_logo::$25
bool render_logo::$3
bool render_logo::$4
number render_logo::$5
char *render_logo::$6
bool render_logo::$7
bool render_logo::$8
number render_logo::$9
char render_logo::line
char render_logo::line#0
char render_logo::line#1
char render_logo::line#2
char render_logo::line1
char render_logo::line1#0
char render_logo::line1#1
char render_logo::line1#2
char render_logo::line2
char render_logo::line2#0
char render_logo::line2#1
char render_logo::line2#2
char render_logo::line3
char render_logo::line3#0
char render_logo::line3#1
char render_logo::line3#2
char render_logo::logo_idx
char render_logo::logo_idx#0
char render_logo::logo_idx#1
char render_logo::logo_idx#10
char render_logo::logo_idx#11
char render_logo::logo_idx#12
char render_logo::logo_idx#2
char render_logo::logo_idx#3
char render_logo::logo_idx#4
char render_logo::logo_idx#5
char render_logo::logo_idx#6
char render_logo::logo_idx#7
char render_logo::logo_idx#8
char render_logo::logo_idx#9
char render_logo::logo_start
char render_logo::logo_start#0
char render_logo::logo_start#1
char render_logo::logo_start#2
char render_logo::logo_start#3
char render_logo::logo_start#4
char render_logo::screen_idx
char render_logo::screen_idx#0
char render_logo::screen_idx#1
char render_logo::screen_idx#10
char render_logo::screen_idx#11
char render_logo::screen_idx#12
char render_logo::screen_idx#13
char render_logo::screen_idx#14
char render_logo::screen_idx#15
char render_logo::screen_idx#16
char render_logo::screen_idx#17
char render_logo::screen_idx#18
char render_logo::screen_idx#19
char render_logo::screen_idx#2
char render_logo::screen_idx#20
char render_logo::screen_idx#21
char render_logo::screen_idx#22
char render_logo::screen_idx#23
char render_logo::screen_idx#3
char render_logo::screen_idx#4
char render_logo::screen_idx#5
char render_logo::screen_idx#6
char render_logo::screen_idx#7
char render_logo::screen_idx#8
char render_logo::screen_idx#9
signed char render_logo::x_char
signed char render_logo::x_char#0
signed char render_logo::x_char#1
signed char render_logo::x_char#2
int render_logo::xpos
int render_logo::xpos#0
int render_logo::xpos#1
int sin16s(unsigned long x)
bool sin16s::$0
bool sin16s::$1
unsigned int sin16s::$13
bool sin16s::$14
bool sin16s::$15
unsigned long sin16s::$16
unsigned long sin16s::$17
int sin16s::$18
bool sin16s::$2
bool sin16s::$3
unsigned long sin16s::$4
char sin16s::isUpper
char sin16s::isUpper#0
char sin16s::isUpper#1
char sin16s::isUpper#2
char sin16s::isUpper#3
char sin16s::isUpper#4
char sin16s::isUpper#5
char sin16s::isUpper#6
char sin16s::isUpper#7
char sin16s::isUpper#8
char sin16s::isUpper#9
int sin16s::return
int sin16s::return#0
int sin16s::return#1
int sin16s::return#2
int sin16s::return#3
int sin16s::return#4
int sin16s::sinx
int sin16s::sinx#0
int sin16s::sinx#1
int sin16s::sinx#2
unsigned int sin16s::usinx
unsigned int sin16s::usinx#0
unsigned int sin16s::usinx#1
unsigned int sin16s::usinx#2
unsigned int sin16s::usinx#3
unsigned int sin16s::usinx#4
unsigned long sin16s::x
unsigned long sin16s::x#0
unsigned long sin16s::x#1
unsigned long sin16s::x#2
unsigned long sin16s::x#3
unsigned long sin16s::x#4
unsigned long sin16s::x#5
unsigned long sin16s::x#6
unsigned long sin16s::x#7
unsigned int sin16s::x1
unsigned int sin16s::x1#0
unsigned int sin16s::x1#1
unsigned int sin16s::x1#2
unsigned int sin16s::x1#3
unsigned int sin16s::x1#4
unsigned int sin16s::x2
unsigned int sin16s::x2#0
unsigned int sin16s::x3
unsigned int sin16s::x3#0
unsigned int sin16s::x3#1
unsigned int sin16s::x3_6
unsigned int sin16s::x3_6#0
unsigned int sin16s::x4
unsigned int sin16s::x4#0
unsigned int sin16s::x5
unsigned int sin16s::x5#0
unsigned int sin16s::x5_128
unsigned int sin16s::x5_128#0
void sin16s_gen2(int *sintab , unsigned int wavelength , int min , int max)
int sin16s_gen2::$1
int sin16s_gen2::$10
bool sin16s_gen2::$4
int sin16s_gen2::$5
long sin16s_gen2::$6
unsigned int sin16s_gen2::$7
int sin16s_gen2::$8
unsigned long sin16s_gen2::$9
int sin16s_gen2::ampl
int sin16s_gen2::ampl#0
int sin16s_gen2::ampl#1
int sin16s_gen2::ampl#2
int sin16s_gen2::ampl#3
int sin16s_gen2::ampl#4
int sin16s_gen2::ampl#5
unsigned int sin16s_gen2::i
unsigned int sin16s_gen2::i#0
unsigned int sin16s_gen2::i#1
unsigned int sin16s_gen2::i#2
unsigned int sin16s_gen2::i#3
unsigned int sin16s_gen2::i#4
unsigned int sin16s_gen2::i#5
int sin16s_gen2::max
int sin16s_gen2::max#0
int sin16s_gen2::max#1
int sin16s_gen2::min
int sin16s_gen2::min#0
int sin16s_gen2::min#1
int sin16s_gen2::offs
int sin16s_gen2::offs#0
int sin16s_gen2::offs#1
int sin16s_gen2::offs#2
int sin16s_gen2::offs#3
int sin16s_gen2::offs#4
int sin16s_gen2::offs#5
int *sin16s_gen2::sintab
int *sin16s_gen2::sintab#0
int *sin16s_gen2::sintab#1
int *sin16s_gen2::sintab#2
int *sin16s_gen2::sintab#3
int *sin16s_gen2::sintab#4
int *sin16s_gen2::sintab#5
int *sin16s_gen2::sintab#6
int *sin16s_gen2::sintab#7
unsigned long sin16s_gen2::step
unsigned long sin16s_gen2::step#0
unsigned long sin16s_gen2::step#1
unsigned long sin16s_gen2::step#2
unsigned long sin16s_gen2::step#3
unsigned long sin16s_gen2::step#4
unsigned int sin16s_gen2::wavelength
unsigned int sin16s_gen2::wavelength#0
unsigned int sin16s_gen2::wavelength#1
unsigned int sin16s_gen2::wavelength#2
unsigned int sin16s_gen2::wavelength#3
unsigned int sin16s_gen2::wavelength#4
unsigned int sin16s_gen2::wavelength#5
unsigned int sin16s_gen2::wavelength#6
unsigned long sin16s_gen2::x
unsigned long sin16s_gen2::x#0
unsigned long sin16s_gen2::x#1
unsigned long sin16s_gen2::x#2
unsigned long sin16s_gen2::x#3
unsigned long sin16s_gen2::x#4
unsigned long sin16s_gen2::x#5
__constant int xsin[XSIN_SIZE] = { fill( XSIN_SIZE, 0) }
unsigned int xsin_idx
unsigned int xsin_idx#0
unsigned int xsin_idx#1
unsigned int xsin_idx#10
unsigned int xsin_idx#11
unsigned int xsin_idx#12
unsigned int xsin_idx#13
unsigned int xsin_idx#14
unsigned int xsin_idx#15
unsigned int xsin_idx#16
unsigned int xsin_idx#17
unsigned int xsin_idx#18
unsigned int xsin_idx#19
unsigned int xsin_idx#2
unsigned int xsin_idx#20
unsigned int xsin_idx#21
unsigned int xsin_idx#22
unsigned int xsin_idx#23
unsigned int xsin_idx#24
unsigned int xsin_idx#25
unsigned int xsin_idx#26
unsigned int xsin_idx#27
unsigned int xsin_idx#28
unsigned int xsin_idx#3
unsigned int xsin_idx#4
unsigned int xsin_idx#5
unsigned int xsin_idx#6
unsigned int xsin_idx#7
unsigned int xsin_idx#8
unsigned int xsin_idx#9

Adding number conversion cast (snumber) 1 in sin16s_gen2::$1 = sin16s_gen2::ampl#0 >> 1
Adding number conversion cast (unumber) 1 in sin16s::isUpper#1 = 1
Adding number conversion cast (unumber) 3 in sin16s::$4 = sin16s::x#6 << 3
Adding number conversion cast (unumber) 0 in mulu16_sel::select#0 = 0
Adding number conversion cast (unumber) 1 in mulu16_sel::select#1 = 1
Adding number conversion cast (unumber) $10000/6 in mulu16_sel::v2#2 = $10000/6
Adding number conversion cast (unumber) 1 in mulu16_sel::select#2 = 1
Adding number conversion cast (unumber) 0 in mulu16_sel::select#3 = 0
Adding number conversion cast (unumber) 0 in mulu16_sel::select#4 = 0
Adding number conversion cast (unumber) 4 in sin16s::x5_128#0 = sin16s::x5#0 >> 4
Adding number conversion cast (unumber) 0 in sin16s::$14 = sin16s::isUpper#2 != 0
Adding number conversion cast (unumber) 1 in divr16u::$0 = divr16u::rem#5 << 1
Adding number conversion cast (unumber) $80 in divr16u::$2 = divr16u::$1 & $80
Adding number conversion cast (unumber) divr16u::$2 in divr16u::$2 = divr16u::$1 & (unumber)$80
Adding number conversion cast (unumber) 0 in divr16u::$3 = divr16u::$2 != 0
Adding number conversion cast (unumber) 1 in divr16u::$6 = divr16u::dividend#4 << 1
Adding number conversion cast (unumber) 1 in divr16u::$7 = divr16u::quotient#3 << 1
Adding number conversion cast (unumber) 1 in divr16u::$5 = divr16u::rem#7 | 1
Adding number conversion cast (unumber) divr16u::$5 in divr16u::$5 = divr16u::rem#7 | (unumber)1
Adding number conversion cast (unumber) 0 in divr16u::rem#3 = 0
Adding number conversion cast (unumber) 0 in mul16u::$0 = mul16u::a#3 != 0
Adding number conversion cast (unumber) 1 in mul16u::$1 = mul16u::a#4 & 1
Adding number conversion cast (unumber) mul16u::$1 in mul16u::$1 = mul16u::a#4 & (unumber)1
Adding number conversion cast (unumber) 0 in mul16u::$2 = mul16u::$1 != 0
Adding number conversion cast (unumber) 1 in mul16u::$5 = mul16u::a#5 >> 1
Adding number conversion cast (unumber) 1 in mul16u::$6 = mul16u::mb#2 << 1
Adding number conversion cast (snumber) 0 in mul16s::$1 = mul16s::a#2 < 0
Adding number conversion cast (snumber) 0 in mul16s::$3 = mul16s::b#2 < 0
Adding number conversion cast (unumber) 0 in memset::$0 = memset::num#2 > 0
Adding number conversion cast (unumber) $3fff in main::toD0181_$0 = main::toD0181_$7 & $3fff
Adding number conversion cast (unumber) main::toD0181_$0 in main::toD0181_$0 = main::toD0181_$7 & (unumber)$3fff
Adding number conversion cast (unumber) 4 in main::toD0181_$1 = main::toD0181_$0 * 4
Adding number conversion cast (unumber) main::toD0181_$1 in main::toD0181_$1 = main::toD0181_$0 * (unumber)4
Adding number conversion cast (unumber) 4 in main::toD0181_$4 = main::toD0181_$3 / 4
Adding number conversion cast (unumber) main::toD0181_$4 in main::toD0181_$4 = main::toD0181_$3 / (unumber)4
Adding number conversion cast (unumber) $f in main::toD0181_$5 = main::toD0181_$4 & $f
Adding number conversion cast (unumber) main::toD0181_$5 in main::toD0181_$5 = main::toD0181_$4 & (unumber)$f
Adding number conversion cast (unumber) main::toD0181_$6 in main::toD0181_$6 = main::toD0181_$2 | main::toD0181_$5
Adding number conversion cast (unumber) $3e8 in memset::num#0 = $3e8
Adding number conversion cast (unumber) WHITE|8 in memset::c#1 = WHITE|8
Adding number conversion cast (unumber) 8 in memset::c#1 = ((unumber)) WHITE|8
Adding number conversion cast (unumber) $3e8 in memset::num#1 = $3e8
Adding number conversion cast (snumber) -$140 in sin16s_gen2::min#0 = -$140
Adding number conversion cast (snumber) $140 in sin16s_gen2::max#0 = $140
Adding number conversion cast (unumber) $ff in loop::$0 = *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER) != $ff
Adding number conversion cast (unumber) 0 in xsin_idx#3 = 0
Adding number conversion cast (unumber) 7 in render_logo::$0 = render_logo::$25 & 7
Adding number conversion cast (unumber) render_logo::$0 in render_logo::$0 = render_logo::$25 & (unumber)7
Adding number conversion cast (unumber) render_logo::$1 in render_logo::$1 = VICII_MCM | render_logo::$0
Adding number conversion cast (snumber) 8 in render_logo::$2 = render_logo::xpos#1 / 8
Adding number conversion cast (snumber) render_logo::$2 in render_logo::$2 = render_logo::xpos#1 / (snumber)8
Adding number conversion cast (snumber) 0 in render_logo::$3 = render_logo::xpos#1 < 0
Adding number conversion cast (unumber) 0 in render_logo::screen_idx#1 = 0
Adding number conversion cast (unumber) 0 in render_logo::screen_idx#2 = 0
Adding number conversion cast (unumber) 0 in render_logo::logo_idx#2 = 0
Adding number conversion cast (unumber) $28 in render_logo::$5 = $28 * render_logo::line#2
Adding number conversion cast (unumber) render_logo::$5 in render_logo::$5 = (unumber)$28 * render_logo::line#2
Adding number conversion cast (unumber) 0 in render_logo::$6[render_logo::screen_idx#8] = 0
Adding number conversion cast (unumber) $28 in render_logo::$8 = render_logo::screen_idx#10 != $28
Adding number conversion cast (unumber) $28 in render_logo::$9 = $28 * render_logo::line1#2
Adding number conversion cast (unumber) render_logo::$9 in render_logo::$9 = (unumber)$28 * render_logo::line1#2
Adding number conversion cast (unumber) $28 in render_logo::$11 = $28 * render_logo::line1#2
Adding number conversion cast (unumber) render_logo::$11 in render_logo::$11 = (unumber)$28 * render_logo::line1#2
Adding number conversion cast (unumber) render_logo::$12 in render_logo::$12 = render_logo::logo_idx#5 + render_logo::$11
Adding number conversion cast (unumber) $28 in render_logo::$15 = render_logo::logo_idx#7 != $28
Adding number conversion cast (unumber) $28 in render_logo::$16 = $28 * render_logo::line2#2
Adding number conversion cast (unumber) render_logo::$16 in render_logo::$16 = (unumber)$28 * render_logo::line2#2
Adding number conversion cast (unumber) $28 in render_logo::$18 = $28 * render_logo::line2#2
Adding number conversion cast (unumber) render_logo::$18 in render_logo::$18 = (unumber)$28 * render_logo::line2#2
Adding number conversion cast (unumber) render_logo::$19 in render_logo::$19 = render_logo::logo_idx#8 + render_logo::$18
Adding number conversion cast (unumber) $28 in render_logo::$21 = render_logo::screen_idx#15 != $28
Adding number conversion cast (unumber) $28 in render_logo::$22 = $28 * render_logo::line3#2
Adding number conversion cast (unumber) render_logo::$22 in render_logo::$22 = (unumber)$28 * render_logo::line3#2
Adding number conversion cast (unumber) 0 in render_logo::$23[render_logo::screen_idx#16] = 0
Successful SSA optimization PassNAddNumberTypeConversions
Inlining cast sin16s::isUpper#1 = (unumber)1
Inlining cast mulu16_sel::select#0 = (unumber)0
Inlining cast mulu16_sel::select#1 = (unumber)1
Inlining cast mulu16_sel::v2#2 = (unumber)$10000/6
Inlining cast mulu16_sel::select#2 = (unumber)1
Inlining cast mulu16_sel::select#3 = (unumber)0
Inlining cast mulu16_sel::select#4 = (unumber)0
Inlining cast divr16u::rem#3 = (unumber)0
Inlining cast memset::dst#0 = (char *)memset::str#3
Inlining cast memset::num#0 = (unumber)$3e8
Inlining cast memset::c#1 = (unumber)WHITE|(unumber)8
Inlining cast memset::num#1 = (unumber)$3e8
Inlining cast sin16s_gen2::min#0 = (snumber)-$140
Inlining cast sin16s_gen2::max#0 = (snumber)$140
Inlining cast xsin_idx#3 = (unumber)0
Inlining cast render_logo::screen_idx#1 = (unumber)0
Inlining cast render_logo::screen_idx#2 = (unumber)0
Inlining cast render_logo::logo_idx#2 = (unumber)0
Inlining cast render_logo::$6[render_logo::screen_idx#8] = (unumber)0
Inlining cast render_logo::$23[render_logo::screen_idx#16] = (unumber)0
Successful SSA optimization Pass2InlineCast
Simplifying constant pointer cast (char *) 53270
Simplifying constant pointer cast (char *) 53272
Simplifying constant pointer cast (struct MOS6569_VICII *) 53248
Simplifying constant pointer cast (char *) 55296
Simplifying constant pointer cast (char *) 1024
Simplifying constant integer cast 1
Simplifying constant integer cast 1
Simplifying constant integer cast 3
Simplifying constant integer cast 0
Simplifying constant integer cast 1
Simplifying constant integer cast 1
Simplifying constant integer cast 0
Simplifying constant integer cast 0
Simplifying constant integer cast 4
Simplifying constant integer cast 0
Simplifying constant integer cast 1
Simplifying constant integer cast $80
Simplifying constant integer cast 0
Simplifying constant integer cast 1
Simplifying constant integer cast 1
Simplifying constant integer cast 1
Simplifying constant integer cast 0
Simplifying constant integer cast 0
Simplifying constant integer cast 1
Simplifying constant integer cast 0
Simplifying constant integer cast 1
Simplifying constant integer cast 1
Simplifying constant integer cast 0
Simplifying constant integer cast 0
Simplifying constant integer cast 0
Simplifying constant integer cast $3fff
Simplifying constant integer cast 4
Simplifying constant integer cast 4
Simplifying constant integer cast $f
Simplifying constant integer cast $3e8
Simplifying constant integer cast WHITE|(unumber)8
Simplifying constant integer cast 8
Simplifying constant integer cast $3e8
Simplifying constant integer cast -$140
Simplifying constant integer cast $140
Simplifying constant integer cast $ff
Simplifying constant integer cast 0
Simplifying constant integer cast 7
Simplifying constant integer cast 8
Simplifying constant integer cast 0
Simplifying constant integer cast 0
Simplifying constant integer cast 0
Simplifying constant integer cast 0
Simplifying constant integer cast $28
Simplifying constant integer cast 0
Simplifying constant integer cast $28
Simplifying constant integer cast $28
Simplifying constant integer cast $28
Simplifying constant integer cast $28
Simplifying constant integer cast $28
Simplifying constant integer cast $28
Simplifying constant integer cast $28
Simplifying constant integer cast $28
Simplifying constant integer cast 0
Successful SSA optimization PassNCastSimplification
Finalized signed number type (signed char) 1
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) 3
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 4
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) $80
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 1
Finalized unsigned number type (char) 1
Finalized signed number type (signed char) 0
Finalized signed number type (signed char) 0
Finalized unsigned number type (char) 0
Finalized unsigned number type (unsigned int) $3fff
Finalized unsigned number type (char) 4
Finalized unsigned number type (char) 4
Finalized unsigned number type (char) $f
Finalized unsigned number type (unsigned int) $3e8
Finalized unsigned number type (char) 8
Finalized unsigned number type (unsigned int) $3e8
Finalized signed number type (int) -$140
Finalized signed number type (int) $140
Finalized unsigned number type (char) $ff
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 7
Finalized signed number type (signed char) 8
Finalized signed number type (signed char) 0
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) 0
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) 0
Successful SSA optimization PassNFinalizeNumberTypeConversions
Inferred type updated to char in divr16u::$2 = divr16u::$1 & $80
Inferred type updated to unsigned int in divr16u::$5 = divr16u::rem#7 | 1
Inferred type updated to char in mul16u::$1 = mul16u::a#4 & 1
Inferred type updated to unsigned int in main::toD0181_$0 = main::toD0181_$7 & $3fff
Inferred type updated to unsigned int in main::toD0181_$1 = main::toD0181_$0 * 4
Inferred type updated to char in main::toD0181_$4 = main::toD0181_$3 / 4
Inferred type updated to char in main::toD0181_$5 = main::toD0181_$4 & $f
Inferred type updated to char in main::toD0181_$6 = main::toD0181_$2 | main::toD0181_$5
Inferred type updated to char in render_logo::$0 = render_logo::$25 & 7
Inferred type updated to char in render_logo::$1 = VICII_MCM | render_logo::$0
Inferred type updated to int in render_logo::$2 = render_logo::xpos#1 / 8
Inferred type updated to char in render_logo::$5 = $28 * render_logo::line#2
Inferred type updated to char in render_logo::$9 = $28 * render_logo::line1#2
Inferred type updated to char in render_logo::$11 = $28 * render_logo::line1#2
Inferred type updated to char in render_logo::$12 = render_logo::logo_idx#5 + render_logo::$11
Inferred type updated to char in render_logo::$16 = $28 * render_logo::line2#2
Inferred type updated to char in render_logo::$18 = $28 * render_logo::line2#2
Inferred type updated to char in render_logo::$19 = render_logo::logo_idx#8 + render_logo::$18
Inferred type updated to char in render_logo::$22 = $28 * render_logo::line3#2
Inversing boolean not [42] sin16s::$1 = sin16s::x#3 < PI_u4f28 from [41] sin16s::$0 = sin16s::x#3 >= PI_u4f28
Inversing boolean not [46] sin16s::$3 = sin16s::x#4 < PI_HALF_u4f28 from [45] sin16s::$2 = sin16s::x#4 >= PI_HALF_u4f28
Inversing boolean not [96] sin16s::$15 = sin16s::isUpper#2 == 0 from [95] sin16s::$14 = sin16s::isUpper#2 != 0
Inversing boolean not [131] divr16u::$4 = divr16u::$2 == 0 from [130] divr16u::$3 = divr16u::$2 != 0
Inversing boolean not [139] divr16u::$9 = divr16u::rem#6 < divr16u::divisor#2 from [138] divr16u::$8 = divr16u::rem#6 >= divr16u::divisor#2
Inversing boolean not [193] mul16u::$3 = mul16u::$1 == 0 from [192] mul16u::$2 = mul16u::$1 != 0
Inversing boolean not [216] mul16s::$2 = mul16s::a#2 >= 0 from [215] mul16s::$1 = mul16s::a#2 < 0
Inversing boolean not [220] mul16s::$4 = mul16s::b#2 >= 0 from [219] mul16s::$3 = mul16s::b#2 < 0
Inversing boolean not [241] memset::$1 = memset::num#2 <= 0 from [240] memset::$0 = memset::num#2 > 0
Inversing boolean not [331] loop::$5 = xsin_idx#2 != XSIN_SIZE from [330] loop::$4 = xsin_idx#2 == XSIN_SIZE
Successful SSA optimization Pass2UnaryNotSimplification
Alias div32u16u::return#0 = div32u16u::return#3 
Alias sin16s_gen2::wavelength#1 = sin16s_gen2::wavelength#3 
Alias sin16s_gen2::ampl#0 = sin16s_gen2::ampl#4 
Alias sin16s_gen2::offs#0 = sin16s_gen2::offs#5 
Alias sin16s_gen2::sintab#6 = sin16s_gen2::sintab#7 
Alias rem16u#0 = rem16u#12 
Alias sin16s_gen2::x#2 = sin16s_gen2::x#4 sin16s_gen2::x#5 sin16s_gen2::x#3 
Alias sin16s_gen2::ampl#1 = sin16s_gen2::ampl#2 sin16s_gen2::ampl#3 sin16s_gen2::ampl#5 
Alias sin16s_gen2::offs#1 = sin16s_gen2::offs#3 sin16s_gen2::offs#4 sin16s_gen2::offs#2 
Alias sin16s_gen2::sintab#2 = sin16s_gen2::sintab#4 sin16s_gen2::sintab#5 sin16s_gen2::sintab#3 
Alias sin16s_gen2::step#1 = sin16s_gen2::step#3 sin16s_gen2::step#4 sin16s_gen2::step#2 
Alias sin16s_gen2::i#2 = sin16s_gen2::i#5 sin16s_gen2::i#4 sin16s_gen2::i#3 
Alias sin16s_gen2::wavelength#2 = sin16s_gen2::wavelength#6 sin16s_gen2::wavelength#5 sin16s_gen2::wavelength#4 
Alias rem16u#1 = rem16u#32 rem16u#23 rem16u#30 rem16u#28 rem16u#13 
Alias sin16s::return#0 = sin16s::return#3 
Alias mul16s::a#0 = sin16s_gen2::$5 
Alias mul16s::return#0 = mul16s::return#3 
Alias sin16s_gen2::x#1 = sin16s_gen2::$9 
Alias sin16s::x#3 = sin16s::x#5 
Alias sin16s::x#1 = sin16s::$16 
Alias mulu16_sel::return#0 = mulu16_sel::return#7 
Alias sin16s::x1#0 = sin16s::x1#1 sin16s::x1#4 sin16s::x1#2 sin16s::x1#3 
Alias sin16s::isUpper#2 = sin16s::isUpper#6 sin16s::isUpper#7 sin16s::isUpper#5 sin16s::isUpper#4 sin16s::isUpper#3 
Alias mulu16_sel::return#1 = mulu16_sel::return#8 
Alias mulu16_sel::return#2 = mulu16_sel::return#9 
Alias sin16s::x3#0 = sin16s::x3#1 
Alias mulu16_sel::return#10 = mulu16_sel::return#3 
Alias sin16s::usinx#0 = sin16s::usinx#4 sin16s::usinx#2 
Alias mulu16_sel::return#11 = mulu16_sel::return#4 
Alias sin16s::usinx#1 = sin16s::$13 sin16s::usinx#3 
Alias sin16s::x#4 = sin16s::x#7 
Alias sin16s::isUpper#8 = sin16s::isUpper#9 
Alias sin16s::x#2 = sin16s::$17 
Alias sin16s::return#1 = sin16s::sinx#2 sin16s::return#4 sin16s::return#2 
Alias sin16s::sinx#1 = sin16s::$18 
Alias mul16u::return#0 = mul16u::return#4 
Alias mulu16_sel::select#5 = mulu16_sel::select#6 
Alias mulu16_sel::return#12 = mulu16_sel::return#5 mulu16_sel::$2 mulu16_sel::return#6 
Alias divr16u::rem#0 = divr16u::$0 divr16u::rem#7 
Alias divr16u::dividend#0 = divr16u::$6 divr16u::dividend#8 
Alias divr16u::quotient#1 = divr16u::$7 divr16u::quotient#4 
Alias divr16u::dividend#3 = divr16u::dividend#7 
Alias divr16u::quotient#6 = divr16u::quotient#7 
Alias divr16u::divisor#4 = divr16u::divisor#5 
Alias divr16u::i#5 = divr16u::i#6 
Alias divr16u::rem#1 = divr16u::$5 
Alias divr16u::rem#6 = divr16u::rem#8 
Alias divr16u::divisor#2 = divr16u::divisor#3 
Alias divr16u::i#3 = divr16u::i#4 
Alias divr16u::rem#2 = divr16u::$10 
Alias divr16u::rem#11 = divr16u::rem#9 
Alias divr16u::return#0 = divr16u::quotient#5 divr16u::quotient#8 divr16u::return#4 divr16u::return#1 
Alias rem16u#14 = rem16u#2 rem16u#3 
Alias divr16u::dividend#1 = div32u16u::$0 
Alias divr16u::return#2 = divr16u::return#5 
Alias div32u16u::dividend#1 = div32u16u::dividend#2 
Alias div32u16u::divisor#1 = div32u16u::divisor#2 
Alias rem16u#15 = rem16u#4 
Alias divr16u::dividend#2 = div32u16u::$2 
Alias divr16u::return#3 = divr16u::return#6 
Alias div32u16u::quotient_hi#0 = div32u16u::quotient_hi#1 
Alias rem16u#16 = rem16u#5 rem16u#17 rem16u#6 
Alias div32u16u::return#1 = div32u16u::quotient#0 div32u16u::return#4 div32u16u::return#2 
Alias mul16u::a#3 = mul16u::a#4 mul16u::a#7 
Alias mul16u::mb#3 = mul16u::mb#4 mul16u::mb#5 
Alias mul16u::res#2 = mul16u::res#5 mul16u::res#4 mul16u::return#1 mul16u::res#3 mul16u::return#5 mul16u::return#2 
Alias mul16u::a#1 = mul16u::$5 
Alias mul16u::mb#1 = mul16u::$6 
Alias mul16u::res#1 = mul16u::$4 
Alias mul16u::return#3 = mul16u::return#6 
Alias mul16s::a#1 = mul16s::a#2 mul16s::a#5 
Alias mul16s::b#1 = mul16s::b#4 mul16s::b#3 
Alias mul16s::m#0 = mul16s::m#3 
Alias mul16s::$11 = mul16s::$7 
Alias mul16s::m#5 = mul16s::m#6 
Alias mul16s::a#3 = mul16s::a#4 
Alias mul16s::$12 = mul16s::$10 
Alias mul16s::return#1 = mul16s::return#4 mul16s::return#2 
Alias memset::return#0 = memset::str#2 memset::return#4 memset::return#1 
Alias memset::str#3 = memset::str#4 
Alias memset::num#2 = memset::num#3 
Alias memset::c#4 = memset::c#5 
Alias memset::c#2 = memset::c#3 
Alias memset::dst#2 = memset::dst#3 
Alias memset::end#1 = memset::end#2 
Alias memset::str#5 = memset::str#6 
Alias main::toD0181_screen#0 = main::toD0181_screen#1 
Alias main::toD0181_gfx#0 = main::toD0181_gfx#1 
Alias rem16u#31 = rem16u#36 rem16u#37 rem16u#35 rem16u#34 rem16u#33 
Alias xsin_idx#23 = xsin_idx#27 xsin_idx#28 xsin_idx#26 xsin_idx#25 xsin_idx#24 
Alias main::toD0181_return#0 = main::toD0181_$6 main::toD0181_return#2 main::toD0181_return#1 main::toD0181_return#3 main::$0 
Alias rem16u#25 = rem16u#29 
Alias xsin_idx#15 = xsin_idx#19 xsin_idx#22 
Alias rem16u#18 = rem16u#7 rem16u#26 rem16u#19 rem16u#8 
Alias xsin_idx#0 = xsin_idx#8 xsin_idx#9 xsin_idx#1 
Alias xsin_idx#10 = xsin_idx#16 xsin_idx#11 
Alias xsin_idx#12 = xsin_idx#17 xsin_idx#4 
Alias render_logo::x_char#0 = render_logo::x_char#1 render_logo::x_char#2 
Alias render_logo::screen_idx#18 = render_logo::screen_idx#7 render_logo::screen_idx#19 
Alias render_logo::logo_start#1 = render_logo::logo_start#4 
Alias render_logo::screen_idx#8 = render_logo::screen_idx#9 
Alias render_logo::logo_start#2 = render_logo::logo_start#3 
Alias render_logo::logo_idx#10 = render_logo::logo_idx#12 
Alias render_logo::screen_idx#10 = render_logo::screen_idx#20 
Alias render_logo::screen_idx#11 = render_logo::screen_idx#12 
Alias render_logo::logo_idx#5 = render_logo::logo_idx#6 
Alias render_logo::logo_idx#11 = render_logo::logo_idx#7 
Alias render_logo::screen_idx#21 = render_logo::screen_idx#22 
Alias render_logo::screen_idx#13 = render_logo::screen_idx#14 
Alias render_logo::logo_idx#8 = render_logo::logo_idx#9 
Alias render_logo::screen_idx#15 = render_logo::screen_idx#23 
Alias render_logo::screen_idx#16 = render_logo::screen_idx#17 
Alias rem16u#27 = rem16u#9 
Alias xsin_idx#18 = xsin_idx#5 
Alias rem16u#10 = rem16u#20 rem16u#21 rem16u#11 
Alias xsin_idx#13 = xsin_idx#6 xsin_idx#14 xsin_idx#7 
Successful SSA optimization Pass2AliasElimination
Alias sin16s::isUpper#2 = sin16s::isUpper#8 
Alias divr16u::dividend#3 = divr16u::dividend#4 
Alias divr16u::quotient#3 = divr16u::quotient#6 
Alias divr16u::divisor#2 = divr16u::divisor#4 divr16u::divisor#7 
Alias divr16u::i#2 = divr16u::i#3 divr16u::i#5 
Alias divr16u::dividend#0 = divr16u::dividend#6 
Alias mul16u::a#3 = mul16u::a#5 
Alias mul16u::mb#2 = mul16u::mb#3 
Alias mul16s::b#1 = mul16s::b#2 
Alias mul16s::a#1 = mul16s::a#3 
Successful SSA optimization Pass2AliasElimination
Identical Phi Values sin16s_gen2::max#1 sin16s_gen2::max#0
Identical Phi Values sin16s_gen2::min#1 sin16s_gen2::min#0
Identical Phi Values sin16s_gen2::wavelength#1 sin16s_gen2::wavelength#0
Identical Phi Values rem16u#22 rem16u#25
Identical Phi Values sin16s_gen2::sintab#6 sin16s_gen2::sintab#1
Identical Phi Values rem16u#0 rem16u#16
Identical Phi Values sin16s_gen2::wavelength#2 sin16s_gen2::wavelength#1
Identical Phi Values rem16u#1 rem16u#0
Identical Phi Values sin16s_gen2::ampl#1 sin16s_gen2::ampl#0
Identical Phi Values sin16s_gen2::offs#1 sin16s_gen2::offs#0
Identical Phi Values sin16s_gen2::step#1 sin16s_gen2::step#0
Identical Phi Values sin16s::x#3 sin16s::x#0
Identical Phi Values divr16u::divisor#2 divr16u::divisor#6
Identical Phi Values div32u16u::dividend#1 div32u16u::dividend#0
Identical Phi Values div32u16u::divisor#1 div32u16u::divisor#0
Identical Phi Values rem16u#24 rem16u#22
Identical Phi Values rem16u#15 rem16u#14
Identical Phi Values rem16u#16 rem16u#14
Identical Phi Values mul16s::a#1 mul16s::a#0
Identical Phi Values mul16s::b#1 mul16s::b#0
Identical Phi Values memset::end#1 memset::end#0
Identical Phi Values memset::str#5 memset::str#3
Identical Phi Values memset::c#2 memset::c#4
Identical Phi Values rem16u#31 rem16u#27
Identical Phi Values xsin_idx#23 xsin_idx#18
Identical Phi Values rem16u#25 rem16u#31
Identical Phi Values xsin_idx#15 xsin_idx#23
Identical Phi Values rem16u#18 rem16u#1
Identical Phi Values xsin_idx#0 xsin_idx#12
Identical Phi Values xsin_idx#20 xsin_idx#15
Identical Phi Values xsin_idx#10 xsin_idx#12
Identical Phi Values render_logo::xpos#1 render_logo::xpos#0
Identical Phi Values render_logo::screen_idx#8 render_logo::screen_idx#18
Identical Phi Values render_logo::logo_start#2 render_logo::logo_start#1
Identical Phi Values render_logo::logo_idx#5 render_logo::logo_idx#10
Identical Phi Values render_logo::screen_idx#11 render_logo::screen_idx#10
Identical Phi Values render_logo::logo_idx#8 render_logo::logo_idx#11
Identical Phi Values render_logo::screen_idx#13 render_logo::screen_idx#21
Identical Phi Values render_logo::screen_idx#16 render_logo::screen_idx#15
Identical Phi Values rem16u#10 rem16u#18
Identical Phi Values xsin_idx#13 xsin_idx#0
Successful SSA optimization Pass2IdenticalPhiElimination
Identical Phi Values memset::return#0 memset::str#3
Identical Phi Values render_logo::logo_start#1 render_logo::logo_start#0
Successful SSA optimization Pass2IdenticalPhiElimination
Identified duplicate assignment right side [381] render_logo::$11 = $28 * render_logo::line1#2
Identified duplicate assignment right side [398] render_logo::$18 = $28 * render_logo::line2#2
Successful SSA optimization Pass2DuplicateRValueIdentification
Simple Condition sin16s_gen2::$4 [14] if(sin16s_gen2::i#2<sin16s_gen2::wavelength#0) goto sin16s_gen2::@2
Simple Condition sin16s::$1 [34] if(sin16s::x#0<PI_u4f28) goto sin16s::@1
Simple Condition sin16s::$3 [37] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2
Simple Condition sin16s::$15 [78] if(sin16s::isUpper#2==0) goto sin16s::@3
Simple Condition divr16u::$4 [100] if(divr16u::$2==0) goto divr16u::@2
Simple Condition divr16u::$9 [105] if(divr16u::rem#6<divr16u::divisor#6) goto divr16u::@3
Simple Condition divr16u::$11 [110] if(divr16u::i#1!=rangelast(0,$f)) goto divr16u::@1
Simple Condition mul16u::$0 [137] if(mul16u::a#3!=0) goto mul16u::@2
Simple Condition mul16u::$3 [140] if(mul16u::$1==0) goto mul16u::@4
Simple Condition mul16s::$2 [153] if(mul16s::a#0>=0) goto mul16s::@1
Simple Condition mul16s::$4 [156] if(mul16s::b#0>=0) goto mul16s::@2
Simple Condition memset::$1 [170] if(memset::num#2<=0) goto memset::@1
Simple Condition memset::$3 [177] if(memset::dst#2!=memset::end#0) goto memset::@4
Simple Condition main::$5 [214] if(main::ch#1!=rangelast(0,$ef)) goto main::@1
Simple Condition loop::$0 [229] if(*((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER)!=$ff) goto loop::@2
Simple Condition loop::$5 [238] if(xsin_idx#2!=XSIN_SIZE) goto loop::@5
Simple Condition render_logo::$3 [253] if(render_logo::xpos#0<0) goto render_logo::@1
Simple Condition render_logo::$4 [261] if(render_logo::screen_idx#18!=render_logo::logo_start#0) goto render_logo::@4
Simple Condition render_logo::$7 [270] unroll if(render_logo::line#1!=rangelast(0,5)) goto render_logo::@6
Simple Condition render_logo::$8 [274] if(render_logo::screen_idx#10!=$28) goto render_logo::@9
Simple Condition render_logo::$13 [284] unroll if(render_logo::line1#1!=rangelast(0,5)) goto render_logo::@10
Simple Condition render_logo::$15 [289] if(render_logo::logo_idx#11!=$28) goto render_logo::@13
Simple Condition render_logo::$20 [299] unroll if(render_logo::line2#1!=rangelast(0,5)) goto render_logo::@14
Simple Condition render_logo::$21 [304] if(render_logo::screen_idx#15!=$28) goto render_logo::@17
Simple Condition render_logo::$24 [312] unroll if(render_logo::line3#1!=rangelast(0,5)) goto render_logo::@18
Successful SSA optimization Pass2ConditionalJumpSimplification
Constant right-side identified [56] mulu16_sel::v2#2 = (unumber)$10000/6
Constant right-side identified [199] memset::str#0 = (void *)SCREEN
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant div32u16u::dividend#0 = PI2_u4f28
Constant sin16s_gen2::x#0 = 0
Constant sin16s_gen2::i#0 = 0
Constant sin16s::isUpper#0 = 0
Constant sin16s::isUpper#1 = 1
Constant mulu16_sel::select#0 = 0
Constant mulu16_sel::select#1 = 1
Constant mulu16_sel::v2#2 = (unumber)$10000/6
Constant mulu16_sel::select#2 = 1
Constant mulu16_sel::select#3 = 0
Constant mulu16_sel::select#4 = 0
Constant divr16u::quotient#0 = 0
Constant divr16u::i#0 = 0
Constant divr16u::rem#3 = 0
Constant mul16u::res#0 = 0
Constant main::toD0181_screen#0 = SCREEN
Constant main::toD0181_gfx#0 = LOGO
Constant memset::str#0 = (void *)SCREEN
Constant memset::c#0 = BLACK
Constant memset::num#0 = $3e8
Constant memset::str#1 = (void *)COLS
Constant memset::c#1 = WHITE|8
Constant memset::num#1 = $3e8
Constant main::ch#0 = 0
Constant sin16s_gen2::sintab#1 = xsin
Constant sin16s_gen2::wavelength#0 = XSIN_SIZE
Constant sin16s_gen2::min#0 = -$140
Constant sin16s_gen2::max#0 = $140
Constant xsin_idx#3 = 0
Constant render_logo::logo_idx#0 = 0
Constant render_logo::screen_idx#0 = 0
Constant render_logo::screen_idx#1 = 0
Constant render_logo::screen_idx#2 = 0
Constant render_logo::line#0 = 0
Constant render_logo::logo_idx#2 = 0
Constant render_logo::line1#0 = 0
Constant render_logo::line2#0 = 0
Constant render_logo::line3#0 = 0
Constant rem16u#27 = 0
Constant xsin_idx#18 = 0
Successful SSA optimization Pass2ConstantIdentification
Constant div32u16u::divisor#0 = sin16s_gen2::wavelength#0
Constant main::toD0181_$7 = (unsigned int)main::toD0181_screen#0
Successful SSA optimization Pass2ConstantIdentification
Constant divr16u::divisor#0 = div32u16u::divisor#0
Constant divr16u::divisor#1 = div32u16u::divisor#0
Successful SSA optimization Pass2ConstantIdentification
Constant value identified (unsigned int)main::toD0181_gfx#0 in [193] main::toD0181_$3 = byte1  (unsigned int)main::toD0181_gfx#0
Successful SSA optimization Pass2ConstantValues
if() condition always true - replacing block destination [226] if(true) goto loop::@2
Successful SSA optimization Pass2ConstantIfs
Resolved ranged next value [108] divr16u::i#1 = ++ divr16u::i#2 to ++
Resolved ranged comparison value [110] if(divr16u::i#1!=rangelast(0,$f)) goto divr16u::@1 to $10
Resolved ranged next value [212] main::ch#1 = ++ main::ch#2 to ++
Resolved ranged comparison value [214] if(main::ch#1!=rangelast(0,$ef)) goto main::@1 to $f0
Resolved ranged next value [268] render_logo::line#1 = ++ render_logo::line#2 to ++
Resolved ranged comparison value [270] unroll if(render_logo::line#1!=rangelast(0,5)) goto render_logo::@6 to 6
Resolved ranged next value [282] render_logo::line1#1 = ++ render_logo::line1#2 to ++
Resolved ranged comparison value [284] unroll if(render_logo::line1#1!=rangelast(0,5)) goto render_logo::@10 to 6
Resolved ranged next value [297] render_logo::line2#1 = ++ render_logo::line2#2 to ++
Resolved ranged comparison value [299] unroll if(render_logo::line2#1!=rangelast(0,5)) goto render_logo::@14 to 6
Resolved ranged next value [310] render_logo::line3#1 = ++ render_logo::line3#2 to ++
Resolved ranged comparison value [312] unroll if(render_logo::line3#1!=rangelast(0,5)) goto render_logo::@18 to 6
Removing unused block loop::@return
Successful SSA optimization Pass2EliminateUnusedBlocks
Eliminating unused variable memset::return#2 and assignment [157] memset::return#2 = memset::str#3
Eliminating unused variable memset::return#3 and assignment [159] memset::return#3 = memset::str#3
Eliminating unused constant render_logo::logo_idx#0
Eliminating unused constant render_logo::screen_idx#0
Eliminating unused constant rem16u#27
Successful SSA optimization PassNEliminateUnusedVars
Removing unused procedure __start
Removing unused procedure block __start
Removing unused procedure block __start::__init1
Removing unused procedure block __start::@1
Removing unused procedure block __start::@2
Removing unused procedure block __start::@return
Successful SSA optimization PassNEliminateEmptyStart
Adding number conversion cast (unumber) $10 in [86] if(divr16u::i#1!=$10) goto divr16u::@1
Adding number conversion cast (unumber) $f0 in [161] if(main::ch#1!=$f0) goto main::@1
Adding number conversion cast (unumber) 6 in [194] unroll if(render_logo::line#1!=6) goto render_logo::@6
Adding number conversion cast (unumber) 6 in [205] unroll if(render_logo::line1#1!=6) goto render_logo::@10
Adding number conversion cast (unumber) 6 in [217] unroll if(render_logo::line2#1!=6) goto render_logo::@14
Adding number conversion cast (unumber) 6 in [227] unroll if(render_logo::line3#1!=6) goto render_logo::@18
Successful SSA optimization PassNAddNumberTypeConversions
Simplifying constant integer cast $10
Simplifying constant integer cast $f0
Simplifying constant integer cast 6
Simplifying constant integer cast 6
Simplifying constant integer cast 6
Simplifying constant integer cast 6
Successful SSA optimization PassNCastSimplification
Finalized unsigned number type (char) $10
Finalized unsigned number type (char) $f0
Finalized unsigned number type (char) 6
Finalized unsigned number type (char) 6
Finalized unsigned number type (char) 6
Finalized unsigned number type (char) 6
Successful SSA optimization PassNFinalizeNumberTypeConversions
Alias render_logo::$11 = render_logo::$9 
Alias render_logo::$18 = render_logo::$16 
Successful SSA optimization Pass2AliasElimination
Constant right-side identified [0] sin16s_gen2::ampl#0 = sin16s_gen2::max#0 - sin16s_gen2::min#0
Constant right-side identified [91] divr16u::dividend#1 = word1  div32u16u::dividend#0
Constant right-side identified [95] divr16u::dividend#2 = word0  div32u16u::dividend#0
Constant right-side identified [147] main::toD0181_$0 = main::toD0181_$7 & $3fff
Constant right-side identified [150] main::toD0181_$3 = byte1  (unsigned int)main::toD0181_gfx#0
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant sin16s_gen2::ampl#0 = sin16s_gen2::max#0-sin16s_gen2::min#0
Constant divr16u::dividend#1 = word1 div32u16u::dividend#0
Constant divr16u::dividend#2 = word0 div32u16u::dividend#0
Constant main::toD0181_$0 = main::toD0181_$7&$3fff
Constant main::toD0181_$3 = byte1 (unsigned int)main::toD0181_gfx#0
Successful SSA optimization Pass2ConstantIdentification
Constant mul16s::b#0 = sin16s_gen2::ampl#0
Successful SSA optimization Pass2ConstantIdentification
Constant mul16u::b#1 = (unsigned int)mul16s::b#0
Constant mul16s::$13 = (unsigned int)mul16s::b#0
Successful SSA optimization Pass2ConstantIdentification
if() condition always true - replacing block destination [120] if(mul16s::b#0>=0) goto mul16s::@2
Successful SSA optimization Pass2ConstantIfs
Eliminating variable mul16s::$9 from unused block mul16s::@4
Eliminating variable mul16s::$14 from unused block mul16s::@4
Eliminating variable mul16s::$12 from unused block mul16s::@4
Eliminating variable mul16s::m#2 from unused block mul16s::@4
Removing PHI-reference to removed block (mul16s::@4) in block mul16s::@2
Removing unused block mul16s::@4
Successful SSA optimization Pass2EliminateUnusedBlocks
Alias mul16s::m#4 = mul16s::m#5 
Successful SSA optimization Pass2AliasElimination
Constant right-side identified [0] sin16s_gen2::$1 = sin16s_gen2::ampl#0 >> 1
Constant right-side identified [135] main::toD0181_$1 = main::toD0181_$0 * 4
Constant right-side identified [137] main::toD0181_$4 = main::toD0181_$3 / 4
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant sin16s_gen2::$1 = sin16s_gen2::ampl#0>>1
Constant main::toD0181_$1 = main::toD0181_$0*4
Constant main::toD0181_$4 = main::toD0181_$3/4
Successful SSA optimization Pass2ConstantIdentification
Constant right-side identified [0] sin16s_gen2::offs#0 = sin16s_gen2::min#0 + sin16s_gen2::$1
Constant right-side identified [134] main::toD0181_$2 = byte1  main::toD0181_$1
Constant right-side identified [135] main::toD0181_$5 = main::toD0181_$4 & $f
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant sin16s_gen2::offs#0 = sin16s_gen2::min#0+sin16s_gen2::$1
Constant main::toD0181_$2 = byte1 main::toD0181_$1
Constant main::toD0181_$5 = main::toD0181_$4&$f
Successful SSA optimization Pass2ConstantIdentification
Simplifying constant evaluating to zero sin16s_gen2::min#0+sin16s_gen2::$1 in 
Successful SSA optimization PassNSimplifyConstantZero
Simplifying expression containing zero sin16s_gen2::$10 in [15] sin16s_gen2::$8 = sin16s_gen2::offs#0 + sin16s_gen2::$10
Successful SSA optimization PassNSimplifyExpressionWithZero
Eliminating unused constant sin16s_gen2::$1
Eliminating unused constant sin16s_gen2::offs#0
Successful SSA optimization PassNEliminateUnusedVars
Alias sin16s_gen2::$8 = sin16s_gen2::$10 
Successful SSA optimization Pass2AliasElimination
Constant right-side identified [132] main::toD0181_return#0 = main::toD0181_$2 | main::toD0181_$5
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant main::toD0181_return#0 = main::toD0181_$2|main::toD0181_$5
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@6 tails: render_logo::@6 blocks: render_logo::@6 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line#2 render_logo::line#0
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [172] if(render_logo::line#1==6) goto render_logo::@7
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [168] render_logo::$5 = $28 * render_logo::line#0
Constant right-side identified [171] render_logo::line#1 = ++ render_logo::line#0
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$5 = $28*render_logo::line#0
Constant render_logo::line#1 = ++render_logo::line#0
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [172] if(render_logo::line#1==6) goto render_logo::@7
Successful SSA optimization Pass2ConstantIfs
Simplifying constant evaluating to zero $28*render_logo::line#0 in 
Successful SSA optimization PassNSimplifyConstantZero
Simplifying expression containing zero SCREEN in [169] render_logo::$6 = SCREEN + render_logo::$5
Successful SSA optimization PassNSimplifyExpressionWithZero
Eliminating unused constant render_logo::$5
Successful SSA optimization PassNEliminateUnusedVars
Constant render_logo::$6 = SCREEN
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@10 tails: render_logo::@10 blocks: render_logo::@10 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line1#2 render_logo::line1#0
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [136] if(render_logo::line1#1==6) goto render_logo::@11
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [131] render_logo::$11 = $28 * render_logo::line1#0
Constant right-side identified [135] render_logo::line1#1 = ++ render_logo::line1#0
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$11 = $28*render_logo::line1#0
Constant render_logo::line1#1 = ++render_logo::line1#0
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [136] if(render_logo::line1#1==6) goto render_logo::@11
Successful SSA optimization Pass2ConstantIfs
Simplifying constant evaluating to zero $28*render_logo::line1#0 in 
Successful SSA optimization PassNSimplifyConstantZero
Simplifying expression containing zero SCREEN in [132] render_logo::$10 = SCREEN + render_logo::$11
Simplifying expression containing zero render_logo::logo_idx#10 in [133] render_logo::$12 = render_logo::logo_idx#10 + render_logo::$11
Successful SSA optimization PassNSimplifyExpressionWithZero
Eliminating unused constant render_logo::$11
Successful SSA optimization PassNEliminateUnusedVars
Alias render_logo::logo_idx#10 = render_logo::$12 
Successful SSA optimization Pass2AliasElimination
Constant render_logo::$10 = SCREEN
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@10_1 tails: render_logo::@10_1 blocks: render_logo::@10_1 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line1#3 render_logo::line1#1
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [137] if(render_logo::line1#4==6) goto render_logo::@11
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [132] render_logo::$28 = $28 * render_logo::line1#1
Constant right-side identified [136] render_logo::line1#4 = ++ render_logo::line1#1
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$28 = $28*render_logo::line1#1
Constant render_logo::line1#4 = ++render_logo::line1#1
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [137] if(render_logo::line1#4==6) goto render_logo::@11
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [131] render_logo::$29 = SCREEN + render_logo::$28
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$29 = SCREEN+render_logo::$28
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@10_2 tails: render_logo::@10_2 blocks: render_logo::@10_2 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line1#5 render_logo::line1#4
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [139] if(render_logo::line1#6==6) goto render_logo::@11
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [134] render_logo::$31 = $28 * render_logo::line1#4
Constant right-side identified [138] render_logo::line1#6 = ++ render_logo::line1#4
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$31 = $28*render_logo::line1#4
Constant render_logo::line1#6 = ++render_logo::line1#4
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [139] if(render_logo::line1#6==6) goto render_logo::@11
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [133] render_logo::$32 = SCREEN + render_logo::$31
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$32 = SCREEN+render_logo::$31
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@10_3 tails: render_logo::@10_3 blocks: render_logo::@10_3 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line1#7 render_logo::line1#6
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [141] if(render_logo::line1#8==6) goto render_logo::@11
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [136] render_logo::$34 = $28 * render_logo::line1#6
Constant right-side identified [140] render_logo::line1#8 = ++ render_logo::line1#6
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$34 = $28*render_logo::line1#6
Constant render_logo::line1#8 = ++render_logo::line1#6
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [141] if(render_logo::line1#8==6) goto render_logo::@11
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [135] render_logo::$35 = SCREEN + render_logo::$34
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$35 = SCREEN+render_logo::$34
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@10_4 tails: render_logo::@10_4 blocks: render_logo::@10_4 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line1#9 render_logo::line1#8
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [143] if(render_logo::line1#10==6) goto render_logo::@11
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [138] render_logo::$37 = $28 * render_logo::line1#8
Constant right-side identified [142] render_logo::line1#10 = ++ render_logo::line1#8
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$37 = $28*render_logo::line1#8
Constant render_logo::line1#10 = ++render_logo::line1#8
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [143] if(render_logo::line1#10==6) goto render_logo::@11
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [137] render_logo::$38 = SCREEN + render_logo::$37
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$38 = SCREEN+render_logo::$37
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@10_5 tails: render_logo::@10_5 blocks: render_logo::@10_5 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line1#11 render_logo::line1#10
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [145] if(render_logo::line1#12==6) goto render_logo::@11
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [140] render_logo::$40 = $28 * render_logo::line1#10
Constant right-side identified [144] render_logo::line1#12 = ++ render_logo::line1#10
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$40 = $28*render_logo::line1#10
Constant render_logo::line1#12 = ++render_logo::line1#10
Successful SSA optimization Pass2ConstantIdentification
Removing PHI-reference to removed block (render_logo::@10_5) in block render_logo::@10_6
if() condition always true - replacing block destination [145] if(render_logo::line1#12==6) goto render_logo::@11
Successful SSA optimization Pass2ConstantIfs
Eliminating variable render_logo::line1#13 from unused block render_logo::@10_6
Eliminating variable render_logo::$43 from unused block render_logo::@10_6
Eliminating variable render_logo::$44 from unused block render_logo::@10_6
Eliminating variable render_logo::$45 from unused block render_logo::@10_6
Eliminating variable render_logo::line1#14 from unused block render_logo::@10_6
Removing unused block render_logo::@10_6
Successful SSA optimization Pass2EliminateUnusedBlocks
Eliminating unused constant render_logo::line1#12
Successful SSA optimization PassNEliminateUnusedVars
Constant right-side identified [139] render_logo::$41 = SCREEN + render_logo::$40
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$41 = SCREEN+render_logo::$40
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@6_1 tails: render_logo::@6_1 blocks: render_logo::@6_1 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line#3 render_logo::line#1
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [149] if(render_logo::line#4==6) goto render_logo::@7
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [145] render_logo::$26 = $28 * render_logo::line#1
Constant right-side identified [148] render_logo::line#4 = ++ render_logo::line#1
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$26 = $28*render_logo::line#1
Constant render_logo::line#4 = ++render_logo::line#1
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [149] if(render_logo::line#4==6) goto render_logo::@7
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [144] render_logo::$27 = SCREEN + render_logo::$26
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$27 = SCREEN+render_logo::$26
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@6_2 tails: render_logo::@6_2 blocks: render_logo::@6_2 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line#5 render_logo::line#4
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [150] if(render_logo::line#6==6) goto render_logo::@7
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [146] render_logo::$46 = $28 * render_logo::line#4
Constant right-side identified [149] render_logo::line#6 = ++ render_logo::line#4
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$46 = $28*render_logo::line#4
Constant render_logo::line#6 = ++render_logo::line#4
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [150] if(render_logo::line#6==6) goto render_logo::@7
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [145] render_logo::$47 = SCREEN + render_logo::$46
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$47 = SCREEN+render_logo::$46
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@6_3 tails: render_logo::@6_3 blocks: render_logo::@6_3 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line#7 render_logo::line#6
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [151] if(render_logo::line#8==6) goto render_logo::@7
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [147] render_logo::$48 = $28 * render_logo::line#6
Constant right-side identified [150] render_logo::line#8 = ++ render_logo::line#6
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$48 = $28*render_logo::line#6
Constant render_logo::line#8 = ++render_logo::line#6
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [151] if(render_logo::line#8==6) goto render_logo::@7
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [146] render_logo::$49 = SCREEN + render_logo::$48
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$49 = SCREEN+render_logo::$48
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@6_4 tails: render_logo::@6_4 blocks: render_logo::@6_4 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line#9 render_logo::line#8
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [152] if(render_logo::line#10==6) goto render_logo::@7
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [148] render_logo::$50 = $28 * render_logo::line#8
Constant right-side identified [151] render_logo::line#10 = ++ render_logo::line#8
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$50 = $28*render_logo::line#8
Constant render_logo::line#10 = ++render_logo::line#8
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [152] if(render_logo::line#10==6) goto render_logo::@7
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [147] render_logo::$51 = SCREEN + render_logo::$50
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$51 = SCREEN+render_logo::$50
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@6_5 tails: render_logo::@6_5 blocks: render_logo::@6_5 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line#11 render_logo::line#10
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [153] if(render_logo::line#12==6) goto render_logo::@7
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [149] render_logo::$52 = $28 * render_logo::line#10
Constant right-side identified [152] render_logo::line#12 = ++ render_logo::line#10
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$52 = $28*render_logo::line#10
Constant render_logo::line#12 = ++render_logo::line#10
Successful SSA optimization Pass2ConstantIdentification
Removing PHI-reference to removed block (render_logo::@6_5) in block render_logo::@6_6
if() condition always true - replacing block destination [153] if(render_logo::line#12==6) goto render_logo::@7
Successful SSA optimization Pass2ConstantIfs
Eliminating variable render_logo::line#13 from unused block render_logo::@6_6
Eliminating variable render_logo::$54 from unused block render_logo::@6_6
Eliminating variable render_logo::$55 from unused block render_logo::@6_6
Eliminating variable render_logo::line#14 from unused block render_logo::@6_6
Removing unused block render_logo::@6_6
Successful SSA optimization Pass2EliminateUnusedBlocks
Eliminating unused constant render_logo::line#12
Successful SSA optimization PassNEliminateUnusedVars
Constant right-side identified [148] render_logo::$53 = SCREEN + render_logo::$52
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$53 = SCREEN+render_logo::$52
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@18 tails: render_logo::@18 blocks: render_logo::@18 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line3#2 render_logo::line3#0
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [161] if(render_logo::line3#1==6) goto render_logo::@19
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [157] render_logo::$22 = $28 * render_logo::line3#0
Constant right-side identified [160] render_logo::line3#1 = ++ render_logo::line3#0
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$22 = $28*render_logo::line3#0
Constant render_logo::line3#1 = ++render_logo::line3#0
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [161] if(render_logo::line3#1==6) goto render_logo::@19
Successful SSA optimization Pass2ConstantIfs
Simplifying constant evaluating to zero $28*render_logo::line3#0 in 
Successful SSA optimization PassNSimplifyConstantZero
Simplifying expression containing zero SCREEN in [158] render_logo::$23 = SCREEN + render_logo::$22
Successful SSA optimization PassNSimplifyExpressionWithZero
Eliminating unused constant render_logo::$22
Successful SSA optimization PassNEliminateUnusedVars
Constant render_logo::$23 = SCREEN
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@18_1 tails: render_logo::@18_1 blocks: render_logo::@18_1 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line3#3 render_logo::line3#1
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [162] if(render_logo::line3#4==6) goto render_logo::@19
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [158] render_logo::$56 = $28 * render_logo::line3#1
Constant right-side identified [161] render_logo::line3#4 = ++ render_logo::line3#1
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$56 = $28*render_logo::line3#1
Constant render_logo::line3#4 = ++render_logo::line3#1
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [162] if(render_logo::line3#4==6) goto render_logo::@19
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [157] render_logo::$57 = SCREEN + render_logo::$56
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$57 = SCREEN+render_logo::$56
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@18_2 tails: render_logo::@18_2 blocks: render_logo::@18_2 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line3#5 render_logo::line3#4
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [163] if(render_logo::line3#6==6) goto render_logo::@19
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [159] render_logo::$58 = $28 * render_logo::line3#4
Constant right-side identified [162] render_logo::line3#6 = ++ render_logo::line3#4
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$58 = $28*render_logo::line3#4
Constant render_logo::line3#6 = ++render_logo::line3#4
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [163] if(render_logo::line3#6==6) goto render_logo::@19
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [158] render_logo::$59 = SCREEN + render_logo::$58
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$59 = SCREEN+render_logo::$58
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@18_3 tails: render_logo::@18_3 blocks: render_logo::@18_3 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line3#7 render_logo::line3#6
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [164] if(render_logo::line3#8==6) goto render_logo::@19
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [160] render_logo::$60 = $28 * render_logo::line3#6
Constant right-side identified [163] render_logo::line3#8 = ++ render_logo::line3#6
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$60 = $28*render_logo::line3#6
Constant render_logo::line3#8 = ++render_logo::line3#6
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [164] if(render_logo::line3#8==6) goto render_logo::@19
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [159] render_logo::$61 = SCREEN + render_logo::$60
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$61 = SCREEN+render_logo::$60
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@18_4 tails: render_logo::@18_4 blocks: render_logo::@18_4 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line3#9 render_logo::line3#8
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [165] if(render_logo::line3#10==6) goto render_logo::@19
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [161] render_logo::$62 = $28 * render_logo::line3#8
Constant right-side identified [164] render_logo::line3#10 = ++ render_logo::line3#8
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$62 = $28*render_logo::line3#8
Constant render_logo::line3#10 = ++render_logo::line3#8
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [165] if(render_logo::line3#10==6) goto render_logo::@19
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [160] render_logo::$63 = SCREEN + render_logo::$62
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$63 = SCREEN+render_logo::$62
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@18_5 tails: render_logo::@18_5 blocks: render_logo::@18_5 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line3#11 render_logo::line3#10
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [166] if(render_logo::line3#12==6) goto render_logo::@19
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [162] render_logo::$64 = $28 * render_logo::line3#10
Constant right-side identified [165] render_logo::line3#12 = ++ render_logo::line3#10
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$64 = $28*render_logo::line3#10
Constant render_logo::line3#12 = ++render_logo::line3#10
Successful SSA optimization Pass2ConstantIdentification
Removing PHI-reference to removed block (render_logo::@18_5) in block render_logo::@18_6
if() condition always true - replacing block destination [166] if(render_logo::line3#12==6) goto render_logo::@19
Successful SSA optimization Pass2ConstantIfs
Eliminating variable render_logo::line3#13 from unused block render_logo::@18_6
Eliminating variable render_logo::$66 from unused block render_logo::@18_6
Eliminating variable render_logo::$67 from unused block render_logo::@18_6
Eliminating variable render_logo::line3#14 from unused block render_logo::@18_6
Removing unused block render_logo::@18_6
Successful SSA optimization Pass2EliminateUnusedBlocks
Eliminating unused constant render_logo::line3#12
Successful SSA optimization PassNEliminateUnusedVars
Constant right-side identified [161] render_logo::$65 = SCREEN + render_logo::$64
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$65 = SCREEN+render_logo::$64
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@14 tails: render_logo::@14 blocks: render_logo::@14 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line2#2 render_logo::line2#0
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [169] if(render_logo::line2#1==6) goto render_logo::@15
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [164] render_logo::$18 = $28 * render_logo::line2#0
Constant right-side identified [168] render_logo::line2#1 = ++ render_logo::line2#0
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$18 = $28*render_logo::line2#0
Constant render_logo::line2#1 = ++render_logo::line2#0
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [169] if(render_logo::line2#1==6) goto render_logo::@15
Successful SSA optimization Pass2ConstantIfs
Simplifying constant evaluating to zero $28*render_logo::line2#0 in 
Successful SSA optimization PassNSimplifyConstantZero
Simplifying expression containing zero SCREEN in [165] render_logo::$17 = SCREEN + render_logo::$18
Simplifying expression containing zero render_logo::logo_idx#11 in [166] render_logo::$19 = render_logo::logo_idx#11 + render_logo::$18
Successful SSA optimization PassNSimplifyExpressionWithZero
Eliminating unused constant render_logo::$18
Successful SSA optimization PassNEliminateUnusedVars
Alias render_logo::logo_idx#11 = render_logo::$19 
Successful SSA optimization Pass2AliasElimination
Constant render_logo::$17 = SCREEN
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@14_1 tails: render_logo::@14_1 blocks: render_logo::@14_1 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line2#3 render_logo::line2#1
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [170] if(render_logo::line2#4==6) goto render_logo::@15
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [165] render_logo::$68 = $28 * render_logo::line2#1
Constant right-side identified [169] render_logo::line2#4 = ++ render_logo::line2#1
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$68 = $28*render_logo::line2#1
Constant render_logo::line2#4 = ++render_logo::line2#1
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [170] if(render_logo::line2#4==6) goto render_logo::@15
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [164] render_logo::$69 = SCREEN + render_logo::$68
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$69 = SCREEN+render_logo::$68
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@14_2 tails: render_logo::@14_2 blocks: render_logo::@14_2 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line2#5 render_logo::line2#4
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [172] if(render_logo::line2#6==6) goto render_logo::@15
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [167] render_logo::$71 = $28 * render_logo::line2#4
Constant right-side identified [171] render_logo::line2#6 = ++ render_logo::line2#4
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$71 = $28*render_logo::line2#4
Constant render_logo::line2#6 = ++render_logo::line2#4
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [172] if(render_logo::line2#6==6) goto render_logo::@15
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [166] render_logo::$72 = SCREEN + render_logo::$71
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$72 = SCREEN+render_logo::$71
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@14_3 tails: render_logo::@14_3 blocks: render_logo::@14_3 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line2#7 render_logo::line2#6
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [174] if(render_logo::line2#8==6) goto render_logo::@15
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [169] render_logo::$74 = $28 * render_logo::line2#6
Constant right-side identified [173] render_logo::line2#8 = ++ render_logo::line2#6
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$74 = $28*render_logo::line2#6
Constant render_logo::line2#8 = ++render_logo::line2#6
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [174] if(render_logo::line2#8==6) goto render_logo::@15
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [168] render_logo::$75 = SCREEN + render_logo::$74
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$75 = SCREEN+render_logo::$74
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@14_4 tails: render_logo::@14_4 blocks: render_logo::@14_4 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line2#9 render_logo::line2#8
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [176] if(render_logo::line2#10==6) goto render_logo::@15
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [171] render_logo::$77 = $28 * render_logo::line2#8
Constant right-side identified [175] render_logo::line2#10 = ++ render_logo::line2#8
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$77 = $28*render_logo::line2#8
Constant render_logo::line2#10 = ++render_logo::line2#8
Successful SSA optimization Pass2ConstantIdentification
if() condition always false - eliminating [176] if(render_logo::line2#10==6) goto render_logo::@15
Successful SSA optimization Pass2ConstantIfs
Constant right-side identified [170] render_logo::$78 = SCREEN + render_logo::$77
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$78 = SCREEN+render_logo::$77
Successful SSA optimization Pass2ConstantIdentification
Unrolling loop Loop head: render_logo::@14_5 tails: render_logo::@14_5 blocks: render_logo::@14_5 
Successful SSA optimization Pass2LoopUnroll
Identical Phi Values render_logo::line2#11 render_logo::line2#10
Successful SSA optimization Pass2IdenticalPhiElimination
Negating conditional jump and destination [178] if(render_logo::line2#12==6) goto render_logo::@15
Successful SSA optimization Pass2ConditionalJumpSequenceImprovement
Constant right-side identified [173] render_logo::$80 = $28 * render_logo::line2#10
Constant right-side identified [177] render_logo::line2#12 = ++ render_logo::line2#10
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$80 = $28*render_logo::line2#10
Constant render_logo::line2#12 = ++render_logo::line2#10
Successful SSA optimization Pass2ConstantIdentification
Removing PHI-reference to removed block (render_logo::@14_5) in block render_logo::@14_6
if() condition always true - replacing block destination [178] if(render_logo::line2#12==6) goto render_logo::@15
Successful SSA optimization Pass2ConstantIfs
Eliminating variable render_logo::line2#13 from unused block render_logo::@14_6
Eliminating variable render_logo::$83 from unused block render_logo::@14_6
Eliminating variable render_logo::$84 from unused block render_logo::@14_6
Eliminating variable render_logo::$85 from unused block render_logo::@14_6
Eliminating variable render_logo::line2#14 from unused block render_logo::@14_6
Removing unused block render_logo::@14_6
Successful SSA optimization Pass2EliminateUnusedBlocks
Eliminating unused constant render_logo::line2#12
Successful SSA optimization PassNEliminateUnusedVars
Constant right-side identified [172] render_logo::$81 = SCREEN + render_logo::$80
Successful SSA optimization Pass2ConstantRValueConsolidation
Constant render_logo::$81 = SCREEN+render_logo::$80
Successful SSA optimization Pass2ConstantIdentification
Inlining Noop Cast [18] memset::$4 = (char *)memset::str#3 keeping memset::str#3
Inlining Noop Cast [20] memset::dst#0 = (char *)memset::str#3 keeping memset::str#3
Inlining Noop Cast [101] sin16s::sinx#0 = (int)sin16s::usinx#1 keeping sin16s::usinx#1
Inlining Noop Cast [124] render_logo::logo_start#0 = (char)render_logo::x_char#0 keeping render_logo::x_char#0
Successful SSA optimization Pass2NopCastInlining
Inlining Noop Cast [40] sin16s_gen2::$8 = (int)sin16s_gen2::$7 keeping sin16s_gen2::$8
Inlining Noop Cast [151] render_logo::logo_idx#1 = (char)render_logo::$14 keeping render_logo::logo_idx#1
Successful SSA optimization Pass2NopCastInlining
Rewriting multiplication to use shift [48] loop::$7 = xsin_idx#12 * SIZEOF_INT
Rewriting division to use shift [121] render_logo::$2 = render_logo::xpos#0 / 8
Successful SSA optimization Pass2MultiplyToShiftRewriting
Inlining constant with var siblings sin16s_gen2::x#0
Inlining constant with var siblings sin16s_gen2::i#0
Inlining constant with var siblings sin16s_gen2::sintab#1
Inlining constant with var siblings sin16s::isUpper#0
Inlining constant with var siblings sin16s::isUpper#1
Inlining constant with var siblings mulu16_sel::select#0
Inlining constant with var siblings mulu16_sel::select#1
Inlining constant with var siblings mulu16_sel::v2#2
Inlining constant with var siblings mulu16_sel::select#2
Inlining constant with var siblings mulu16_sel::select#3
Inlining constant with var siblings mulu16_sel::select#4
Inlining constant with var siblings divr16u::quotient#0
Inlining constant with var siblings divr16u::i#0
Inlining constant with var siblings divr16u::rem#3
Inlining constant with var siblings divr16u::divisor#0
Inlining constant with var siblings divr16u::divisor#1
Inlining constant with var siblings divr16u::dividend#1
Inlining constant with var siblings divr16u::dividend#2
Inlining constant with var siblings mul16u::res#0
Inlining constant with var siblings mul16u::b#1
Inlining constant with var siblings memset::str#0
Inlining constant with var siblings memset::c#0
Inlining constant with var siblings memset::num#0
Inlining constant with var siblings memset::str#1
Inlining constant with var siblings memset::c#1
Inlining constant with var siblings memset::num#1
Inlining constant with var siblings main::ch#0
Inlining constant with var siblings render_logo::screen_idx#1
Inlining constant with var siblings render_logo::screen_idx#2
Inlining constant with different constant siblings render_logo::line#0
Inlining constant with var siblings render_logo::logo_idx#2
Inlining constant with different constant siblings render_logo::line1#0
Inlining constant with different constant siblings render_logo::line2#0
Inlining constant with different constant siblings render_logo::line3#0
Inlining constant with different constant siblings render_logo::line#1
Inlining constant with different constant siblings render_logo::line1#1
Inlining constant with different constant siblings render_logo::line1#4
Inlining constant with different constant siblings render_logo::line1#6
Inlining constant with different constant siblings render_logo::line1#8
Inlining constant with different constant siblings render_logo::line1#10
Inlining constant with different constant siblings render_logo::line#4
Inlining constant with different constant siblings render_logo::line#6
Inlining constant with different constant siblings render_logo::line#8
Inlining constant with different constant siblings render_logo::line#10
Inlining constant with different constant siblings render_logo::line3#1
Inlining constant with different constant siblings render_logo::line3#4
Inlining constant with different constant siblings render_logo::line3#6
Inlining constant with different constant siblings render_logo::line3#8
Inlining constant with different constant siblings render_logo::line3#10
Inlining constant with different constant siblings render_logo::line2#1
Inlining constant with different constant siblings render_logo::line2#4
Inlining constant with different constant siblings render_logo::line2#6
Inlining constant with different constant siblings render_logo::line2#8
Inlining constant with different constant siblings render_logo::line2#10
Inlining constant with var siblings xsin_idx#3
Inlining constant with var siblings xsin_idx#18
Constant inlined divr16u::rem#3 = 0
Constant inlined render_logo::$32 = SCREEN+$28*++++0
Constant inlined render_logo::$31 = $28*++++0
Constant inlined sin16s::isUpper#0 = 0
Constant inlined mulu16_sel::select#4 = 0
Constant inlined mulu16_sel::select#2 = 1
Constant inlined mulu16_sel::select#3 = 0
Constant inlined mulu16_sel::select#0 = 0
Constant inlined sin16s::isUpper#1 = 1
Constant inlined mulu16_sel::select#1 = 1
Constant inlined render_logo::$34 = $28*++++++0
Constant inlined render_logo::line1#10 = ++++++++++0
Constant inlined render_logo::$35 = SCREEN+$28*++++++0
Constant inlined render_logo::$38 = SCREEN+$28*++++++++0
Constant inlined render_logo::line3#8 = ++++++++0
Constant inlined render_logo::$37 = $28*++++++++0
Constant inlined main::ch#0 = 0
Constant inlined render_logo::line2#6 = ++++++0
Constant inlined main::toD0181_$7 = (unsigned int)SCREEN
Constant inlined render_logo::line2#8 = ++++++++0
Constant inlined render_logo::$41 = SCREEN+$28*++++++++++0
Constant inlined render_logo::line2#1 = ++0
Constant inlined render_logo::$40 = $28*++++++++++0
Constant inlined render_logo::line2#4 = ++++0
Constant inlined main::toD0181_$2 = byte1 (unsigned int)SCREEN&$3fff*4
Constant inlined sin16s_gen2::wavelength#0 = XSIN_SIZE
Constant inlined main::toD0181_$1 = (unsigned int)SCREEN&$3fff*4
Constant inlined main::toD0181_$0 = (unsigned int)SCREEN&$3fff
Constant inlined render_logo::line2#0 = 0
Constant inlined main::toD0181_$5 = byte1 (unsigned int)LOGO/4&$f
Constant inlined main::toD0181_$4 = byte1 (unsigned int)LOGO/4
Constant inlined main::toD0181_$3 = byte1 (unsigned int)LOGO
Constant inlined xsin_idx#18 = 0
Constant inlined sin16s_gen2::sintab#1 = xsin
Constant inlined render_logo::$47 = SCREEN+$28*++++0
Constant inlined memset::c#0 = BLACK
Constant inlined render_logo::$46 = $28*++++0
Constant inlined render_logo::$49 = SCREEN+$28*++++++0
Constant inlined memset::c#1 = WHITE|8
Constant inlined render_logo::$48 = $28*++++++0
Constant inlined main::toD0181_screen#0 = SCREEN
Constant inlined render_logo::$50 = $28*++++++++0
Constant inlined render_logo::$52 = $28*++++++++++0
Constant inlined divr16u::i#0 = 0
Constant inlined render_logo::$51 = SCREEN+$28*++++++++0
Constant inlined render_logo::$53 = SCREEN+$28*++++++++++0
Constant inlined sin16s_gen2::x#0 = 0
Constant inlined render_logo::$56 = $28*++0
Constant inlined render_logo::$58 = $28*++++0
Constant inlined render_logo::$57 = SCREEN+$28*++0
Constant inlined render_logo::screen_idx#1 = 0
Constant inlined render_logo::$59 = SCREEN+$28*++++0
Constant inlined render_logo::screen_idx#2 = 0
Constant inlined render_logo::line1#6 = ++++++0
Constant inlined render_logo::$61 = SCREEN+$28*++++++0
Constant inlined render_logo::line1#8 = ++++++++0
Constant inlined render_logo::$60 = $28*++++++0
Constant inlined render_logo::$63 = SCREEN+$28*++++++++0
Constant inlined render_logo::$62 = $28*++++++++0
Constant inlined render_logo::$65 = SCREEN+$28*++++++++++0
Constant inlined render_logo::line1#4 = ++++0
Constant inlined render_logo::$64 = $28*++++++++++0
Constant inlined render_logo::line1#0 = 0
Constant inlined render_logo::line1#1 = ++0
Constant inlined divr16u::dividend#1 = word1 PI2_u4f28
Constant inlined divr16u::dividend#2 = word0 PI2_u4f28
Constant inlined render_logo::line#0 = 0
Constant inlined mulu16_sel::v2#2 = (unsigned int)$10000/6
Constant inlined render_logo::line#1 = ++0
Constant inlined render_logo::line#4 = ++++0
Constant inlined render_logo::line2#10 = ++++++++++0
Constant inlined render_logo::$69 = SCREEN+$28*++0
Constant inlined render_logo::line#6 = ++++++0
Constant inlined render_logo::$68 = $28*++0
Constant inlined render_logo::line#8 = ++++++++0
Constant inlined render_logo::$72 = SCREEN+$28*++++0
Constant inlined render_logo::$71 = $28*++++0
Constant inlined sin16s_gen2::i#0 = 0
Constant inlined render_logo::$74 = $28*++++++0
Constant inlined render_logo::line#10 = ++++++++++0
Constant inlined render_logo::$75 = SCREEN+$28*++++++0
Constant inlined mul16u::b#1 = (unsigned int)sin16s_gen2::ampl#0
Constant inlined memset::num#1 = $3e8
Constant inlined memset::num#0 = $3e8
Constant inlined render_logo::$6 = SCREEN
Constant inlined render_logo::$78 = SCREEN+$28*++++++++0
Constant inlined render_logo::$77 = $28*++++++++0
Constant inlined mul16s::$13 = (unsigned int)sin16s_gen2::ampl#0
Constant inlined render_logo::$81 = SCREEN+$28*++++++++++0
Constant inlined mul16s::b#0 = sin16s_gen2::ampl#0
Constant inlined render_logo::$80 = $28*++++++++++0
Constant inlined render_logo::logo_idx#2 = 0
Constant inlined main::toD0181_gfx#0 = LOGO
Constant inlined render_logo::$10 = SCREEN
Constant inlined xsin_idx#3 = 0
Constant inlined div32u16u::dividend#0 = PI2_u4f28
Constant inlined divr16u::quotient#0 = 0
Constant inlined mul16u::res#0 = 0
Constant inlined render_logo::line3#10 = ++++++++++0
Constant inlined divr16u::divisor#1 = XSIN_SIZE
Constant inlined divr16u::divisor#0 = XSIN_SIZE
Constant inlined render_logo::$17 = SCREEN
Constant inlined render_logo::line3#4 = ++++0
Constant inlined memset::str#1 = (void *)COLS
Constant inlined memset::str#0 = (void *)SCREEN
Constant inlined render_logo::line3#6 = ++++++0
Constant inlined render_logo::line3#0 = 0
Constant inlined render_logo::line3#1 = ++0
Constant inlined render_logo::$23 = SCREEN
Constant inlined div32u16u::divisor#0 = XSIN_SIZE
Constant inlined render_logo::$27 = SCREEN+$28*++0
Constant inlined render_logo::$26 = $28*++0
Constant inlined render_logo::$29 = SCREEN+$28*++0
Constant inlined render_logo::$28 = $28*++0
Successful SSA optimization Pass2ConstantInlining
Simplifying constant integer increment ++0
Simplifying constant integer increment ++0
Simplifying constant integer increment ++1
Simplifying constant integer increment ++1
Simplifying constant integer increment ++2
Simplifying constant integer increment ++2
Simplifying constant integer increment ++3
Simplifying constant integer increment ++3
Simplifying constant integer increment ++4
Simplifying constant integer increment ++0
Simplifying constant integer increment ++0
Simplifying constant integer increment ++1
Simplifying constant integer increment ++2
Simplifying constant integer increment ++3
Simplifying constant integer increment ++0
Simplifying constant integer increment ++0
Simplifying constant integer increment ++1
Simplifying constant integer increment ++2
Simplifying constant integer increment ++3
Simplifying constant integer increment ++0
Simplifying constant integer increment ++0
Simplifying constant integer increment ++1
Simplifying constant integer increment ++1
Simplifying constant integer increment ++2
Simplifying constant integer increment ++2
Simplifying constant integer increment ++3
Simplifying constant integer increment ++3
Simplifying constant integer increment ++4
Successful SSA optimization Pass2ConstantSimplification
Simplifying constant integer increment ++1
Simplifying constant integer increment ++2
Simplifying constant integer increment ++3
Simplifying constant integer increment ++4
Simplifying constant integer increment ++1
Simplifying constant integer increment ++2
Simplifying constant integer increment ++3
Simplifying constant integer increment ++4
Successful SSA optimization Pass2ConstantSimplification
Identical Phi Values memset::num#2 $3e8
Identical Phi Values divr16u::divisor#6 XSIN_SIZE
Successful SSA optimization Pass2IdenticalPhiElimination
if() condition always false - eliminating [17] if($3e8<=0) goto memset::@1
Successful SSA optimization Pass2ConstantIfs
Finalized unsigned number type (char) 6
Finalized unsigned number type (char) $28
Finalized unsigned number type (char) 8
Finalized unsigned number type (unsigned int) $2000
Finalized unsigned number type (unsigned long) $10000
Finalized unsigned number type (char) 6
Successful SSA optimization PassNFinalizeNumberTypeConversions
Added new block during phi lifting main::@8(between main::@1 and main::@1)
Added new block during phi lifting loop::@7(between loop::@6 and loop::@5)
Added new block during phi lifting sin16s::@12(between sin16s and sin16s::@1)
Fixing phi predecessor for sin16s::isUpper#2 to new block ( sin16s -> sin16s::@12 ) during phi lifting.
Added new block during phi lifting sin16s::@13(between sin16s::@1 and sin16s::@2)
Added new block during phi lifting sin16s::@14(between sin16s::@11 and sin16s::@3)
Added new block during phi lifting mul16s::@6(between mul16s::@5 and mul16s::@1)
Added new block during phi lifting render_logo::@20(between render_logo::@12 and render_logo::@16)
Added new block during phi lifting divr16u::@7(between divr16u::@3 and divr16u::@1)
Added new block during phi lifting divr16u::@8(between divr16u::@1 and divr16u::@2)
Added new block during phi lifting divr16u::@9(between divr16u::@2 and divr16u::@3)
Added new block during phi lifting mul16u::@6(between mul16u::@2 and mul16u::@4)
Adding NOP phi() at start of main::toD0181
Adding NOP phi() at start of main::toD0181_@return
Adding NOP phi() at start of main::@4
Adding NOP phi() at start of main::@5
Adding NOP phi() at start of main::@2
Adding NOP phi() at start of main::@6
Adding NOP phi() at start of main::@7
Adding NOP phi() at start of memset::@1
Adding NOP phi() at start of sin16s_gen2
Adding NOP phi() at start of loop
Adding NOP phi() at start of loop::@4
Adding NOP phi() at start of div32u16u
Adding NOP phi() at start of render_logo::@2
Adding NOP phi() at start of render_logo::@9
Adding NOP phi() at start of render_logo::@4
Adding NOP phi() at start of render_logo::@17
Adding NOP phi() at start of render_logo::@13
Adding NOP phi() at start of mul16u::@3
CALL GRAPH
Calls in [main] to memset:9 memset:11 sin16s_gen2:18 loop:20 
Calls in [sin16s_gen2] to div32u16u:35 sin16s:42 mul16s:45 
Calls in [loop] to render_logo:64 
Calls in [div32u16u] to divr16u:73 divr16u:78 
Calls in [sin16s] to mulu16_sel:97 mulu16_sel:104 mulu16_sel:109 mulu16_sel:117 mulu16_sel:124 
Calls in [mul16s] to mul16u:139 
Calls in [mulu16_sel] to mul16u:257 

Created 38 initial phi equivalence classes
Coalesced [23] main::ch#3 = main::ch#1
Coalesced [33] memset::dst#5 = memset::dst#1
Coalesced [53] sin16s_gen2::i#6 = sin16s_gen2::i#1
Coalesced [54] sin16s_gen2::x#6 = sin16s_gen2::x#1
Coalesced [55] sin16s_gen2::sintab#8 = sin16s_gen2::sintab#0
Coalesced [70] xsin_idx#29 = xsin_idx#21
Coalesced [71] xsin_idx#30 = xsin_idx#2
Coalesced [77] divr16u::rem#12 = divr16u::rem#4
Coalesced [85] sin16s::x#9 = sin16s::x#1
Coalesced [89] sin16s::x#11 = sin16s::x#2
Coalesced [95] mulu16_sel::v1#7 = mulu16_sel::v1#0
Coalesced [96] mulu16_sel::v2#7 = mulu16_sel::v2#0
Coalesced [102] mulu16_sel::v1#8 = mulu16_sel::v1#1
Coalesced [103] mulu16_sel::v2#8 = mulu16_sel::v2#1
Coalesced [108] mulu16_sel::v1#9 = mulu16_sel::v1#2
Coalesced [115] mulu16_sel::v1#10 = mulu16_sel::v1#3
Coalesced [116] mulu16_sel::v2#9 = mulu16_sel::v2#3
Coalesced [122] mulu16_sel::v1#6 = mulu16_sel::v1#4
Coalesced [123] mulu16_sel::v2#6 = mulu16_sel::v2#4
Coalesced [131] sin16s::return#6 = sin16s::sinx#1
Coalesced [135] sin16s::x#10 = sin16s::x#4
Coalesced [136] sin16s::x#8 = sin16s::x#0
Coalesced [138] mul16u::a#8 = mul16u::a#2
Coalesced [146] mul16s::m#7 = mul16s::m#1
Coalesced [150] mul16s::m#8 = mul16s::m#0
Coalesced [161] render_logo::screen_idx#26 = render_logo::screen_idx#18
Coalesced [179] render_logo::screen_idx#25 = render_logo::screen_idx#4
Coalesced [180] render_logo::logo_idx#13 = render_logo::logo_idx#3
Coalesced [189] render_logo::screen_idx#24 = render_logo::screen_idx#3
Coalesced [194] render_logo::screen_idx#28 = render_logo::screen_idx#21
Coalesced [205] render_logo::screen_idx#29 = render_logo::screen_idx#6
Coalesced [220] render_logo::logo_idx#15 = render_logo::logo_idx#4
Coalesced [221] render_logo::screen_idx#27 = render_logo::screen_idx#5
Coalesced [223] divr16u::rem#13 = divr16u::rem#10
Coalesced [224] divr16u::dividend#9 = divr16u::dividend#5
Coalesced [231] divr16u::rem#16 = divr16u::rem#1
Coalesced [238] divr16u::rem#18 = divr16u::rem#2
Coalesced [239] divr16u::return#8 = divr16u::quotient#2
Coalesced [245] divr16u::rem#14 = divr16u::rem#11
Coalesced [246] divr16u::dividend#10 = divr16u::dividend#0
Coalesced [247] divr16u::quotient#9 = divr16u::return#0
Coalesced [248] divr16u::i#7 = divr16u::i#1
Coalesced [249] divr16u::rem#17 = divr16u::rem#6
Coalesced [250] divr16u::return#7 = divr16u::quotient#1
Coalesced [251] divr16u::rem#15 = divr16u::rem#0
Coalesced [255] mul16u::b#3 = mul16u::b#0
Coalesced [256] mul16u::a#9 = mul16u::a#0
Coalesced [265] mul16u::a#10 = mul16u::a#6
Coalesced [266] mul16u::mb#6 = mul16u::mb#0
Coalesced [274] mul16u::res#9 = mul16u::res#1
Coalesced [278] mul16u::a#11 = mul16u::a#1
Coalesced [279] mul16u::res#7 = mul16u::res#6
Coalesced [280] mul16u::mb#7 = mul16u::mb#1
Coalesced (already) [281] mul16u::res#8 = mul16u::res#2
Coalesced down to 27 phi equivalence classes
Culled Empty Block label main::toD0181_@return
Culled Empty Block label main::@5
Culled Empty Block label main::@7
Culled Empty Block label main::@8
Culled Empty Block label memset::@1
Culled Empty Block label loop::@4
Culled Empty Block label sin16s::@13
Culled Empty Block label sin16s::@12
Culled Empty Block label mul16s::@6
Culled Empty Block label render_logo::@2
Culled Empty Block label render_logo::@5
Culled Empty Block label render_logo::@9
Culled Empty Block label render_logo::@4
Culled Empty Block label render_logo::@20
Culled Empty Block label render_logo::@17
Culled Empty Block label render_logo::@13
Culled Empty Block label divr16u::@7
Culled Empty Block label divr16u::@9
Culled Empty Block label divr16u::@8
Culled Empty Block label mul16u::@3
Culled Empty Block label mul16u::@6
Renumbering block sin16s::@14 to sin16s::@12
Renumbering block mul16u::@4 to mul16u::@3
Renumbering block mul16u::@5 to mul16u::@4
Renumbering block mul16s::@5 to mul16s::@4
Renumbering block memset::@2 to memset::@1
Renumbering block memset::@3 to memset::@2
Renumbering block memset::@4 to memset::@3
Renumbering block main::@6 to main::@5
Renumbering block loop::@5 to loop::@4
Renumbering block loop::@6 to loop::@5
Renumbering block loop::@7 to loop::@6
Renumbering block render_logo::@3 to render_logo::@2
Renumbering block render_logo::@6 to render_logo::@3
Renumbering block render_logo::@7 to render_logo::@4
Renumbering block render_logo::@8 to render_logo::@5
Renumbering block render_logo::@10 to render_logo::@6
Renumbering block render_logo::@11 to render_logo::@7
Renumbering block render_logo::@12 to render_logo::@8
Renumbering block render_logo::@14 to render_logo::@9
Renumbering block render_logo::@15 to render_logo::@10
Renumbering block render_logo::@16 to render_logo::@11
Renumbering block render_logo::@18 to render_logo::@12
Renumbering block render_logo::@19 to render_logo::@13
Adding NOP phi() at start of main::toD0181
Adding NOP phi() at start of main::@4
Adding NOP phi() at start of main::@2
Adding NOP phi() at start of main::@5
Adding NOP phi() at start of sin16s_gen2
Adding NOP phi() at start of loop
Adding NOP phi() at start of loop::@6
Adding NOP phi() at start of div32u16u

FINAL CONTROL FLOW GRAPH

void main()
main: scope:[main]  from
  asm { sei  }
  [1] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = WHITE
  [2] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) = DARK_GREY
  [3] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR) = *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1)
  [4] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2) = BLACK
  to:main::toD0181
main::toD0181: scope:[main]  from main
  [5] phi()
  to:main::@3
main::@3: scope:[main]  from main::toD0181
  [6] *D018 = main::toD0181_return#0
  [7] *D016 = VICII_MCM
  [8] call memset
  to:main::@4
main::@4: scope:[main]  from main::@3
  [9] phi()
  [10] call memset
  to:main::@1
main::@1: scope:[main]  from main::@1 main::@4
  [11] main::ch#2 = phi( main::@1/main::ch#1, main::@4/0 )
  [12] SCREEN[main::ch#2] = main::ch#2
  [13] main::ch#1 = ++ main::ch#2
  [14] if(main::ch#1!=$f0) goto main::@1
  to:main::@2
main::@2: scope:[main]  from main::@1
  [15] phi()
  [16] call sin16s_gen2
  to:main::@5
main::@5: scope:[main]  from main::@2
  [17] phi()
  [18] call loop
  to:main::@return
main::@return: scope:[main]  from main::@5
  [19] return 
  to:@return

void * memset(void *str , char c , unsigned int num)
memset: scope:[memset]  from main::@3 main::@4
  [20] memset::c#4 = phi( main::@3/BLACK, main::@4/WHITE|8 )
  [20] memset::str#3 = phi( main::@3/(void *)SCREEN, main::@4/(void *)COLS )
  to:memset::@1
memset::@1: scope:[memset]  from memset
  [21] memset::end#0 = (char *)memset::str#3 + $3e8
  [22] memset::dst#4 = (char *)memset::str#3
  to:memset::@2
memset::@2: scope:[memset]  from memset::@1 memset::@3
  [23] memset::dst#2 = phi( memset::@1/memset::dst#4, memset::@3/memset::dst#1 )
  [24] if(memset::dst#2!=memset::end#0) goto memset::@3
  to:memset::@return
memset::@return: scope:[memset]  from memset::@2
  [25] return 
  to:@return
memset::@3: scope:[memset]  from memset::@2
  [26] *memset::dst#2 = memset::c#4
  [27] memset::dst#1 = ++ memset::dst#2
  to:memset::@2

void sin16s_gen2(int *sintab , unsigned int wavelength , int min , int max)
sin16s_gen2: scope:[sin16s_gen2]  from main::@2
  [28] phi()
  [29] call div32u16u
  [30] div32u16u::return#0 = div32u16u::return#1
  to:sin16s_gen2::@3
sin16s_gen2::@3: scope:[sin16s_gen2]  from sin16s_gen2
  [31] sin16s_gen2::step#0 = div32u16u::return#0
  to:sin16s_gen2::@1
sin16s_gen2::@1: scope:[sin16s_gen2]  from sin16s_gen2::@3 sin16s_gen2::@5
  [32] sin16s_gen2::sintab#2 = phi( sin16s_gen2::@3/xsin, sin16s_gen2::@5/sin16s_gen2::sintab#0 )
  [32] sin16s_gen2::x#2 = phi( sin16s_gen2::@3/0, sin16s_gen2::@5/sin16s_gen2::x#1 )
  [32] sin16s_gen2::i#2 = phi( sin16s_gen2::@3/0, sin16s_gen2::@5/sin16s_gen2::i#1 )
  [33] if(sin16s_gen2::i#2<XSIN_SIZE) goto sin16s_gen2::@2
  to:sin16s_gen2::@return
sin16s_gen2::@return: scope:[sin16s_gen2]  from sin16s_gen2::@1
  [34] return 
  to:@return
sin16s_gen2::@2: scope:[sin16s_gen2]  from sin16s_gen2::@1
  [35] sin16s::x#0 = sin16s_gen2::x#2
  [36] call sin16s
  [37] sin16s::return#0 = sin16s::return#1
  to:sin16s_gen2::@4
sin16s_gen2::@4: scope:[sin16s_gen2]  from sin16s_gen2::@2
  [38] mul16s::a#0 = sin16s::return#0
  [39] call mul16s
  [40] mul16s::return#0 = mul16s::return#1
  to:sin16s_gen2::@5
sin16s_gen2::@5: scope:[sin16s_gen2]  from sin16s_gen2::@4
  [41] sin16s_gen2::$6 = mul16s::return#0
  [42] sin16s_gen2::$8 = word1  sin16s_gen2::$6
  [43] *sin16s_gen2::sintab#2 = (int)sin16s_gen2::$8
  [44] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_INT
  [45] sin16s_gen2::x#1 = sin16s_gen2::x#2 + sin16s_gen2::step#0
  [46] sin16s_gen2::i#1 = ++ sin16s_gen2::i#2
  to:sin16s_gen2::@1

void loop()
loop: scope:[loop]  from main::@5
  [47] phi()
  to:loop::@1
loop::@1: scope:[loop]  from loop loop::@4
  [48] xsin_idx#12 = phi( loop/0, loop::@4/xsin_idx#21 )
  to:loop::@2
loop::@2: scope:[loop]  from loop::@1 loop::@2
  [49] if(*((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER)!=$ff) goto loop::@2
  to:loop::@3
loop::@3: scope:[loop]  from loop::@2
  [50] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = ++ *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR)
  [51] loop::$7 = xsin_idx#12 << 1
  [52] loop::$2 = xsin + loop::$7
  [53] loop::xpos#0 = *loop::$2
  [54] render_logo::xpos#0 = loop::xpos#0
  [55] call render_logo
  to:loop::@5
loop::@5: scope:[loop]  from loop::@3
  [56] xsin_idx#2 = ++ xsin_idx#12
  [57] if(xsin_idx#2!=XSIN_SIZE) goto loop::@6
  to:loop::@4
loop::@6: scope:[loop]  from loop::@5
  [58] phi()
  to:loop::@4
loop::@4: scope:[loop]  from loop::@5 loop::@6
  [59] xsin_idx#21 = phi( loop::@5/0, loop::@6/xsin_idx#2 )
  [60] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = -- *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR)
  to:loop::@1

unsigned long div32u16u(unsigned long dividend , unsigned int divisor)
div32u16u: scope:[div32u16u]  from sin16s_gen2
  [61] phi()
  [62] call divr16u
  [63] divr16u::return#2 = divr16u::return#0
  to:div32u16u::@1
div32u16u::@1: scope:[div32u16u]  from div32u16u
  [64] div32u16u::quotient_hi#0 = divr16u::return#2
  [65] divr16u::rem#4 = rem16u#14
  [66] call divr16u
  [67] divr16u::return#3 = divr16u::return#0
  to:div32u16u::@2
div32u16u::@2: scope:[div32u16u]  from div32u16u::@1
  [68] div32u16u::quotient_lo#0 = divr16u::return#3
  [69] div32u16u::return#1 = div32u16u::quotient_hi#0 dw= div32u16u::quotient_lo#0
  to:div32u16u::@return
div32u16u::@return: scope:[div32u16u]  from div32u16u::@2
  [70] return 
  to:@return

int sin16s(unsigned long x)
sin16s: scope:[sin16s]  from sin16s_gen2::@2
  [71] if(sin16s::x#0<PI_u4f28) goto sin16s::@1
  to:sin16s::@4
sin16s::@4: scope:[sin16s]  from sin16s
  [72] sin16s::x#1 = sin16s::x#0 - PI_u4f28
  to:sin16s::@1
sin16s::@1: scope:[sin16s]  from sin16s sin16s::@4
  [73] sin16s::isUpper#2 = phi( sin16s/0, sin16s::@4/1 )
  [73] sin16s::x#4 = phi( sin16s/sin16s::x#0, sin16s::@4/sin16s::x#1 )
  [74] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2
  to:sin16s::@5
sin16s::@5: scope:[sin16s]  from sin16s::@1
  [75] sin16s::x#2 = PI_u4f28 - sin16s::x#4
  to:sin16s::@2
sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
  [76] sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
  [77] sin16s::$4 = sin16s::x#6 << 3
  [78] sin16s::x1#0 = word1  sin16s::$4
  [79] mulu16_sel::v1#0 = sin16s::x1#0
  [80] mulu16_sel::v2#0 = sin16s::x1#0
  [81] call mulu16_sel
  [82] mulu16_sel::return#0 = mulu16_sel::return#12
  to:sin16s::@7
sin16s::@7: scope:[sin16s]  from sin16s::@2
  [83] sin16s::x2#0 = mulu16_sel::return#0
  [84] mulu16_sel::v1#1 = sin16s::x2#0
  [85] mulu16_sel::v2#1 = sin16s::x1#0
  [86] call mulu16_sel
  [87] mulu16_sel::return#1 = mulu16_sel::return#12
  to:sin16s::@8
sin16s::@8: scope:[sin16s]  from sin16s::@7
  [88] sin16s::x3#0 = mulu16_sel::return#1
  [89] mulu16_sel::v1#2 = sin16s::x3#0
  [90] call mulu16_sel
  [91] mulu16_sel::return#2 = mulu16_sel::return#12
  to:sin16s::@9
sin16s::@9: scope:[sin16s]  from sin16s::@8
  [92] sin16s::x3_6#0 = mulu16_sel::return#2
  [93] sin16s::usinx#0 = sin16s::x1#0 - sin16s::x3_6#0
  [94] mulu16_sel::v1#3 = sin16s::x3#0
  [95] mulu16_sel::v2#3 = sin16s::x1#0
  [96] call mulu16_sel
  [97] mulu16_sel::return#10 = mulu16_sel::return#12
  to:sin16s::@10
sin16s::@10: scope:[sin16s]  from sin16s::@9
  [98] sin16s::x4#0 = mulu16_sel::return#10
  [99] mulu16_sel::v1#4 = sin16s::x4#0
  [100] mulu16_sel::v2#4 = sin16s::x1#0
  [101] call mulu16_sel
  [102] mulu16_sel::return#11 = mulu16_sel::return#12
  to:sin16s::@11
sin16s::@11: scope:[sin16s]  from sin16s::@10
  [103] sin16s::x5#0 = mulu16_sel::return#11
  [104] sin16s::x5_128#0 = sin16s::x5#0 >> 4
  [105] sin16s::usinx#1 = sin16s::usinx#0 + sin16s::x5_128#0
  [106] if(sin16s::isUpper#2==0) goto sin16s::@12
  to:sin16s::@6
sin16s::@6: scope:[sin16s]  from sin16s::@11
  [107] sin16s::sinx#1 = - (int)sin16s::usinx#1
  to:sin16s::@3
sin16s::@3: scope:[sin16s]  from sin16s::@12 sin16s::@6
  [108] sin16s::return#1 = phi( sin16s::@12/sin16s::return#5, sin16s::@6/sin16s::sinx#1 )
  to:sin16s::@return
sin16s::@return: scope:[sin16s]  from sin16s::@3
  [109] return 
  to:@return
sin16s::@12: scope:[sin16s]  from sin16s::@11
  [110] sin16s::return#5 = (int)sin16s::usinx#1
  to:sin16s::@3

long mul16s(int a , int b)
mul16s: scope:[mul16s]  from sin16s_gen2::@4
  [111] mul16u::a#2 = (unsigned int)mul16s::a#0
  [112] call mul16u
  [113] mul16u::return#3 = mul16u::res#2
  to:mul16s::@4
mul16s::@4: scope:[mul16s]  from mul16s
  [114] mul16s::m#0 = mul16u::return#3
  [115] if(mul16s::a#0>=0) goto mul16s::@1
  to:mul16s::@3
mul16s::@3: scope:[mul16s]  from mul16s::@4
  [116] mul16s::$6 = word1  mul16s::m#0
  [117] mul16s::$11 = mul16s::$6 - (unsigned int)sin16s_gen2::ampl#0
  [118] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11
  to:mul16s::@1
mul16s::@1: scope:[mul16s]  from mul16s::@3 mul16s::@4
  [119] mul16s::m#4 = phi( mul16s::@3/mul16s::m#1, mul16s::@4/mul16s::m#0 )
  to:mul16s::@2
mul16s::@2: scope:[mul16s]  from mul16s::@1
  [120] mul16s::return#1 = (long)mul16s::m#4
  to:mul16s::@return
mul16s::@return: scope:[mul16s]  from mul16s::@2
  [121] return 
  to:@return

void render_logo(int xpos)
render_logo: scope:[render_logo]  from loop::@3
  [122] render_logo::$25 = (char)render_logo::xpos#0
  [123] render_logo::$0 = render_logo::$25 & 7
  [124] render_logo::$1 = VICII_MCM | render_logo::$0
  [125] *D016 = render_logo::$1
  [126] render_logo::$2 = render_logo::xpos#0 >> 3
  [127] render_logo::x_char#0 = (signed char)render_logo::$2
  [128] if(render_logo::xpos#0<0) goto render_logo::@1
  to:render_logo::@2
render_logo::@2: scope:[render_logo]  from render_logo render_logo::@4
  [129] render_logo::screen_idx#18 = phi( render_logo/0, render_logo::@4/render_logo::screen_idx#3 )
  [130] if(render_logo::screen_idx#18!=(char)render_logo::x_char#0) goto render_logo::@3
  to:render_logo::@5
render_logo::@5: scope:[render_logo]  from render_logo::@2 render_logo::@7
  [131] render_logo::logo_idx#10 = phi( render_logo::@7/render_logo::logo_idx#3, render_logo::@2/0 )
  [131] render_logo::screen_idx#10 = phi( render_logo::@7/render_logo::screen_idx#4, render_logo::@2/render_logo::screen_idx#18 )
  [132] if(render_logo::screen_idx#10!=$28) goto render_logo::@6
  to:render_logo::@return
render_logo::@return: scope:[render_logo]  from render_logo::@11 render_logo::@5
  [133] return 
  to:@return
render_logo::@6: scope:[render_logo]  from render_logo::@5
  [134] SCREEN[render_logo::screen_idx#10] = render_logo::logo_idx#10
  to:render_logo::@10_1
render_logo::@10_1: scope:[render_logo]  from render_logo::@6
  [135] render_logo::$30 = render_logo::logo_idx#10 + $28*1
  [136] (SCREEN+$28*1)[render_logo::screen_idx#10] = render_logo::$30
  to:render_logo::@10_2
render_logo::@10_2: scope:[render_logo]  from render_logo::@10_1
  [137] render_logo::$33 = render_logo::logo_idx#10 + $28*2
  [138] (SCREEN+$28*2)[render_logo::screen_idx#10] = render_logo::$33
  to:render_logo::@10_3
render_logo::@10_3: scope:[render_logo]  from render_logo::@10_2
  [139] render_logo::$36 = render_logo::logo_idx#10 + $28*3
  [140] (SCREEN+$28*3)[render_logo::screen_idx#10] = render_logo::$36
  to:render_logo::@10_4
render_logo::@10_4: scope:[render_logo]  from render_logo::@10_3
  [141] render_logo::$39 = render_logo::logo_idx#10 + $28*4
  [142] (SCREEN+$28*4)[render_logo::screen_idx#10] = render_logo::$39
  to:render_logo::@10_5
render_logo::@10_5: scope:[render_logo]  from render_logo::@10_4
  [143] render_logo::$42 = render_logo::logo_idx#10 + $28*5
  [144] (SCREEN+$28*5)[render_logo::screen_idx#10] = render_logo::$42
  to:render_logo::@7
render_logo::@7: scope:[render_logo]  from render_logo::@10_5
  [145] render_logo::screen_idx#4 = ++ render_logo::screen_idx#10
  [146] render_logo::logo_idx#3 = ++ render_logo::logo_idx#10
  to:render_logo::@5
render_logo::@3: scope:[render_logo]  from render_logo::@2
  [147] SCREEN[render_logo::screen_idx#18] = 0
  to:render_logo::@6_1
render_logo::@6_1: scope:[render_logo]  from render_logo::@3
  [148] (SCREEN+$28*1)[render_logo::screen_idx#18] = 0
  to:render_logo::@6_2
render_logo::@6_2: scope:[render_logo]  from render_logo::@6_1
  [149] (SCREEN+$28*2)[render_logo::screen_idx#18] = 0
  to:render_logo::@6_3
render_logo::@6_3: scope:[render_logo]  from render_logo::@6_2
  [150] (SCREEN+$28*3)[render_logo::screen_idx#18] = 0
  to:render_logo::@6_4
render_logo::@6_4: scope:[render_logo]  from render_logo::@6_3
  [151] (SCREEN+$28*4)[render_logo::screen_idx#18] = 0
  to:render_logo::@6_5
render_logo::@6_5: scope:[render_logo]  from render_logo::@6_4
  [152] (SCREEN+$28*5)[render_logo::screen_idx#18] = 0
  to:render_logo::@4
render_logo::@4: scope:[render_logo]  from render_logo::@6_5
  [153] render_logo::screen_idx#3 = ++ render_logo::screen_idx#18
  to:render_logo::@2
render_logo::@1: scope:[render_logo]  from render_logo
  [154] render_logo::logo_idx#1 = - render_logo::x_char#0
  [155] render_logo::logo_idx#14 = (char)render_logo::logo_idx#1
  to:render_logo::@8
render_logo::@8: scope:[render_logo]  from render_logo::@1 render_logo::@10
  [156] render_logo::screen_idx#21 = phi( render_logo::@1/0, render_logo::@10/render_logo::screen_idx#5 )
  [156] render_logo::logo_idx#11 = phi( render_logo::@1/render_logo::logo_idx#14, render_logo::@10/render_logo::logo_idx#4 )
  [157] if(render_logo::logo_idx#11!=$28) goto render_logo::@9
  to:render_logo::@11
render_logo::@11: scope:[render_logo]  from render_logo::@13 render_logo::@8
  [158] render_logo::screen_idx#15 = phi( render_logo::@8/render_logo::screen_idx#21, render_logo::@13/render_logo::screen_idx#6 )
  [159] if(render_logo::screen_idx#15!=$28) goto render_logo::@12
  to:render_logo::@return
render_logo::@12: scope:[render_logo]  from render_logo::@11
  [160] SCREEN[render_logo::screen_idx#15] = 0
  to:render_logo::@18_1
render_logo::@18_1: scope:[render_logo]  from render_logo::@12
  [161] (SCREEN+$28*1)[render_logo::screen_idx#15] = 0
  to:render_logo::@18_2
render_logo::@18_2: scope:[render_logo]  from render_logo::@18_1
  [162] (SCREEN+$28*2)[render_logo::screen_idx#15] = 0
  to:render_logo::@18_3
render_logo::@18_3: scope:[render_logo]  from render_logo::@18_2
  [163] (SCREEN+$28*3)[render_logo::screen_idx#15] = 0
  to:render_logo::@18_4
render_logo::@18_4: scope:[render_logo]  from render_logo::@18_3
  [164] (SCREEN+$28*4)[render_logo::screen_idx#15] = 0
  to:render_logo::@18_5
render_logo::@18_5: scope:[render_logo]  from render_logo::@18_4
  [165] (SCREEN+$28*5)[render_logo::screen_idx#15] = 0
  to:render_logo::@13
render_logo::@13: scope:[render_logo]  from render_logo::@18_5
  [166] render_logo::screen_idx#6 = ++ render_logo::screen_idx#15
  to:render_logo::@11
render_logo::@9: scope:[render_logo]  from render_logo::@8
  [167] SCREEN[render_logo::screen_idx#21] = render_logo::logo_idx#11
  to:render_logo::@14_1
render_logo::@14_1: scope:[render_logo]  from render_logo::@9
  [168] render_logo::$70 = render_logo::logo_idx#11 + $28*1
  [169] (SCREEN+$28*1)[render_logo::screen_idx#21] = render_logo::$70
  to:render_logo::@14_2
render_logo::@14_2: scope:[render_logo]  from render_logo::@14_1
  [170] render_logo::$73 = render_logo::logo_idx#11 + $28*2
  [171] (SCREEN+$28*2)[render_logo::screen_idx#21] = render_logo::$73
  to:render_logo::@14_3
render_logo::@14_3: scope:[render_logo]  from render_logo::@14_2
  [172] render_logo::$76 = render_logo::logo_idx#11 + $28*3
  [173] (SCREEN+$28*3)[render_logo::screen_idx#21] = render_logo::$76
  to:render_logo::@14_4
render_logo::@14_4: scope:[render_logo]  from render_logo::@14_3
  [174] render_logo::$79 = render_logo::logo_idx#11 + $28*4
  [175] (SCREEN+$28*4)[render_logo::screen_idx#21] = render_logo::$79
  to:render_logo::@14_5
render_logo::@14_5: scope:[render_logo]  from render_logo::@14_4
  [176] render_logo::$82 = render_logo::logo_idx#11 + $28*5
  [177] (SCREEN+$28*5)[render_logo::screen_idx#21] = render_logo::$82
  to:render_logo::@10
render_logo::@10: scope:[render_logo]  from render_logo::@14_5
  [178] render_logo::screen_idx#5 = ++ render_logo::screen_idx#21
  [179] render_logo::logo_idx#4 = ++ render_logo::logo_idx#11
  to:render_logo::@8

unsigned int divr16u(unsigned int dividend , unsigned int divisor , unsigned int rem)
divr16u: scope:[divr16u]  from div32u16u div32u16u::@1
  [180] divr16u::dividend#5 = phi( div32u16u/word1 PI2_u4f28, div32u16u::@1/word0 PI2_u4f28 )
  [180] divr16u::rem#10 = phi( div32u16u/0, div32u16u::@1/divr16u::rem#4 )
  to:divr16u::@1
divr16u::@1: scope:[divr16u]  from divr16u divr16u::@3
  [181] divr16u::i#2 = phi( divr16u/0, divr16u::@3/divr16u::i#1 )
  [181] divr16u::quotient#3 = phi( divr16u/0, divr16u::@3/divr16u::return#0 )
  [181] divr16u::dividend#3 = phi( divr16u/divr16u::dividend#5, divr16u::@3/divr16u::dividend#0 )
  [181] divr16u::rem#5 = phi( divr16u/divr16u::rem#10, divr16u::@3/divr16u::rem#11 )
  [182] divr16u::rem#0 = divr16u::rem#5 << 1
  [183] divr16u::$1 = byte1  divr16u::dividend#3
  [184] divr16u::$2 = divr16u::$1 & $80
  [185] if(divr16u::$2==0) goto divr16u::@2
  to:divr16u::@4
divr16u::@4: scope:[divr16u]  from divr16u::@1
  [186] divr16u::rem#1 = divr16u::rem#0 | 1
  to:divr16u::@2
divr16u::@2: scope:[divr16u]  from divr16u::@1 divr16u::@4
  [187] divr16u::rem#6 = phi( divr16u::@1/divr16u::rem#0, divr16u::@4/divr16u::rem#1 )
  [188] divr16u::dividend#0 = divr16u::dividend#3 << 1
  [189] divr16u::quotient#1 = divr16u::quotient#3 << 1
  [190] if(divr16u::rem#6<XSIN_SIZE) goto divr16u::@3
  to:divr16u::@5
divr16u::@5: scope:[divr16u]  from divr16u::@2
  [191] divr16u::quotient#2 = ++ divr16u::quotient#1
  [192] divr16u::rem#2 = divr16u::rem#6 - XSIN_SIZE
  to:divr16u::@3
divr16u::@3: scope:[divr16u]  from divr16u::@2 divr16u::@5
  [193] divr16u::return#0 = phi( divr16u::@2/divr16u::quotient#1, divr16u::@5/divr16u::quotient#2 )
  [193] divr16u::rem#11 = phi( divr16u::@2/divr16u::rem#6, divr16u::@5/divr16u::rem#2 )
  [194] divr16u::i#1 = ++ divr16u::i#2
  [195] if(divr16u::i#1!=$10) goto divr16u::@1
  to:divr16u::@6
divr16u::@6: scope:[divr16u]  from divr16u::@3
  [196] rem16u#14 = divr16u::rem#11
  to:divr16u::@return
divr16u::@return: scope:[divr16u]  from divr16u::@6
  [197] return 
  to:@return

unsigned int mulu16_sel(unsigned int v1 , unsigned int v2 , char select)
mulu16_sel: scope:[mulu16_sel]  from sin16s::@10 sin16s::@2 sin16s::@7 sin16s::@8 sin16s::@9
  [198] mulu16_sel::select#5 = phi( sin16s::@10/0, sin16s::@2/0, sin16s::@7/1, sin16s::@8/1, sin16s::@9/0 )
  [198] mulu16_sel::v2#5 = phi( sin16s::@10/mulu16_sel::v2#4, sin16s::@2/mulu16_sel::v2#0, sin16s::@7/mulu16_sel::v2#1, sin16s::@8/(unsigned int)$10000/6, sin16s::@9/mulu16_sel::v2#3 )
  [198] mulu16_sel::v1#5 = phi( sin16s::@10/mulu16_sel::v1#4, sin16s::@2/mulu16_sel::v1#0, sin16s::@7/mulu16_sel::v1#1, sin16s::@8/mulu16_sel::v1#2, sin16s::@9/mulu16_sel::v1#3 )
  [199] mul16u::a#0 = mulu16_sel::v1#5
  [200] mul16u::b#0 = mulu16_sel::v2#5
  [201] call mul16u
  [202] mul16u::return#0 = mul16u::res#2
  to:mulu16_sel::@1
mulu16_sel::@1: scope:[mulu16_sel]  from mulu16_sel
  [203] mulu16_sel::$0 = mul16u::return#0
  [204] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
  [205] mulu16_sel::return#12 = word1  mulu16_sel::$1
  to:mulu16_sel::@return
mulu16_sel::@return: scope:[mulu16_sel]  from mulu16_sel::@1
  [206] return 
  to:@return

unsigned long mul16u(unsigned int a , unsigned int b)
mul16u: scope:[mul16u]  from mul16s mulu16_sel
  [207] mul16u::a#6 = phi( mul16s/mul16u::a#2, mulu16_sel/mul16u::a#0 )
  [207] mul16u::b#2 = phi( mul16s/(unsigned int)sin16s_gen2::ampl#0, mulu16_sel/mul16u::b#0 )
  [208] mul16u::mb#0 = (unsigned long)mul16u::b#2
  to:mul16u::@1
mul16u::@1: scope:[mul16u]  from mul16u mul16u::@3
  [209] mul16u::mb#2 = phi( mul16u/mul16u::mb#0, mul16u::@3/mul16u::mb#1 )
  [209] mul16u::res#2 = phi( mul16u/0, mul16u::@3/mul16u::res#6 )
  [209] mul16u::a#3 = phi( mul16u/mul16u::a#6, mul16u::@3/mul16u::a#1 )
  [210] if(mul16u::a#3!=0) goto mul16u::@2
  to:mul16u::@return
mul16u::@return: scope:[mul16u]  from mul16u::@1
  [211] return 
  to:@return
mul16u::@2: scope:[mul16u]  from mul16u::@1
  [212] mul16u::$1 = mul16u::a#3 & 1
  [213] if(mul16u::$1==0) goto mul16u::@3
  to:mul16u::@4
mul16u::@4: scope:[mul16u]  from mul16u::@2
  [214] mul16u::res#1 = mul16u::res#2 + mul16u::mb#2
  to:mul16u::@3
mul16u::@3: scope:[mul16u]  from mul16u::@2 mul16u::@4
  [215] mul16u::res#6 = phi( mul16u::@2/mul16u::res#2, mul16u::@4/mul16u::res#1 )
  [216] mul16u::a#1 = mul16u::a#3 >> 1
  [217] mul16u::mb#1 = mul16u::mb#2 << 1
  to:mul16u::@1


VARIABLE REGISTER WEIGHTS
unsigned long div32u16u(unsigned long dividend , unsigned int divisor)
unsigned long div32u16u::dividend
unsigned int div32u16u::divisor
unsigned long div32u16u::quotient
unsigned int div32u16u::quotient_hi
unsigned int div32u16u::quotient_hi#0 // 40.4
unsigned int div32u16u::quotient_lo
unsigned int div32u16u::quotient_lo#0 // 202.0
unsigned long div32u16u::return
unsigned long div32u16u::return#0 // 22.0
unsigned long div32u16u::return#1 // 37.33333333333333
unsigned int divr16u(unsigned int dividend , unsigned int divisor , unsigned int rem)
char divr16u::$1 // 20002.0
char divr16u::$2 // 20002.0
unsigned int divr16u::dividend
unsigned int divr16u::dividend#0 // 2500.25
unsigned int divr16u::dividend#3 // 4429.142857142857
unsigned int divr16u::dividend#5 // 1001.0
unsigned int divr16u::divisor
char divr16u::i
char divr16u::i#1 // 15001.5
char divr16u::i#2 // 1538.6153846153845
unsigned int divr16u::quotient
unsigned int divr16u::quotient#1 // 15001.5
unsigned int divr16u::quotient#2 // 10001.0
unsigned int divr16u::quotient#3 // 2500.25
unsigned int divr16u::rem
unsigned int divr16u::rem#0 // 7500.75
unsigned int divr16u::rem#1 // 20002.0
unsigned int divr16u::rem#10 // 1102.0
unsigned int divr16u::rem#11 // 10334.666666666666
unsigned int divr16u::rem#2 // 20002.0
unsigned int divr16u::rem#4 // 202.0
unsigned int divr16u::rem#5 // 21003.0
unsigned int divr16u::rem#6 // 10001.0
unsigned int divr16u::return
unsigned int divr16u::return#0 // 4315.0
unsigned int divr16u::return#2 // 202.0
unsigned int divr16u::return#3 // 202.0
void loop()
int *loop::$2 // 202.0
unsigned int loop::$7 // 202.0
int loop::xpos
int loop::xpos#0 // 202.0
void main()
char main::ch
char main::ch#1 // 16.5
char main::ch#2 // 22.0
char *main::toD0181_gfx
char main::toD0181_return
char *main::toD0181_screen
void * memset(void *str , char c , unsigned int num)
char memset::c
char memset::c#4 // 14.428571428571429
char *memset::dst
char *memset::dst#1 // 202.0
char *memset::dst#2 // 138.33333333333331
char *memset::dst#4 // 22.0
char *memset::end
char *memset::end#0 // 18.666666666666664
unsigned int memset::num
void *memset::return
void *memset::str
void *memset::str#3
long mul16s(int a , int b)
unsigned int mul16s::$11 // 2002.0
unsigned int mul16s::$6 // 2002.0
int mul16s::a
int mul16s::a#0 // 220.39999999999998
int mul16s::b
unsigned long mul16s::m
unsigned long mul16s::m#0 // 1001.0
unsigned long mul16s::m#1 // 2002.0
unsigned long mul16s::m#4 // 2002.0
long mul16s::return
long mul16s::return#0 // 202.0
long mul16s::return#1 // 367.33333333333337
unsigned long mul16u(unsigned int a , unsigned int b)
char mul16u::$1 // 2.0000002E7
unsigned int mul16u::a
unsigned int mul16u::a#0 // 10001.0
unsigned int mul16u::a#1 // 1.0000001E7
unsigned int mul16u::a#2 // 2002.0
unsigned int mul16u::a#3 // 6683334.166666666
unsigned int mul16u::a#6 // 55501.5
unsigned int mul16u::b
unsigned int mul16u::b#0 // 20002.0
unsigned int mul16u::b#2 // 10001.0
unsigned long mul16u::mb
unsigned long mul16u::mb#0 // 200002.0
unsigned long mul16u::mb#1 // 2.0000002E7
unsigned long mul16u::mb#2 // 4300000.571428571
unsigned long mul16u::res
unsigned long mul16u::res#1 // 2.0000002E7
unsigned long mul16u::res#2 // 4287286.428571429
unsigned long mul16u::res#6 // 1.0000001E7
unsigned long mul16u::return
unsigned long mul16u::return#0 // 20002.0
unsigned long mul16u::return#3 // 2002.0
unsigned int mulu16_sel(unsigned int v1 , unsigned int v2 , char select)
unsigned long mulu16_sel::$0 // 20002.0
unsigned long mulu16_sel::$1 // 20002.0
unsigned int mulu16_sel::return
unsigned int mulu16_sel::return#0 // 2002.0
unsigned int mulu16_sel::return#1 // 2002.0
unsigned int mulu16_sel::return#10 // 2002.0
unsigned int mulu16_sel::return#11 // 2002.0
unsigned int mulu16_sel::return#12 // 2143.714285714286
unsigned int mulu16_sel::return#2 // 2002.0
char mulu16_sel::select
char mulu16_sel::select#5 // 1666.8333333333333
unsigned int mulu16_sel::v1
unsigned int mulu16_sel::v1#0 // 1001.0
unsigned int mulu16_sel::v1#1 // 1001.0
unsigned int mulu16_sel::v1#2 // 2002.0
unsigned int mulu16_sel::v1#3 // 1001.0
unsigned int mulu16_sel::v1#4 // 1001.0
unsigned int mulu16_sel::v1#5 // 15006.0
unsigned int mulu16_sel::v2
unsigned int mulu16_sel::v2#0 // 2002.0
unsigned int mulu16_sel::v2#1 // 2002.0
unsigned int mulu16_sel::v2#3 // 2002.0
unsigned int mulu16_sel::v2#4 // 2002.0
unsigned int mulu16_sel::v2#5 // 7002.5
unsigned int rem16u
unsigned int rem16u#14 // 220.39999999999998
void render_logo(int xpos)
char render_logo::$0 // 2002.0
char render_logo::$1 // 2002.0
int render_logo::$2 // 1001.0
char render_logo::$25 // 2002.0
char render_logo::$30 // 200002.0
char render_logo::$33 // 200002.0
char render_logo::$36 // 200002.0
char render_logo::$39 // 200002.0
char render_logo::$42 // 200002.0
char render_logo::$70 // 200002.0
char render_logo::$73 // 200002.0
char render_logo::$76 // 200002.0
char render_logo::$79 // 200002.0
char render_logo::$82 // 200002.0
char render_logo::line
char render_logo::line1
char render_logo::line2
char render_logo::line3
char render_logo::logo_idx
signed char render_logo::logo_idx#1 // 1001.0
char render_logo::logo_idx#10 // 57143.42857142857
char render_logo::logo_idx#11 // 64357.857142857145
char render_logo::logo_idx#14 // 2002.0
char render_logo::logo_idx#3 // 200002.0
char render_logo::logo_idx#4 // 200002.0
char render_logo::logo_start
char render_logo::screen_idx
char render_logo::screen_idx#10 // 76923.84615384616
char render_logo::screen_idx#15 // 125001.25
char render_logo::screen_idx#18 // 125001.25
char render_logo::screen_idx#21 // 69231.46153846155
char render_logo::screen_idx#3 // 200002.0
char render_logo::screen_idx#4 // 100001.0
char render_logo::screen_idx#5 // 100001.0
char render_logo::screen_idx#6 // 200002.0
signed char render_logo::x_char
signed char render_logo::x_char#0 // 182.0
int render_logo::xpos
int render_logo::xpos#0 // 300.42857142857144
int sin16s(unsigned long x)
unsigned long sin16s::$4 // 2002.0
char sin16s::isUpper
char sin16s::isUpper#2 // 30.333333333333332
int sin16s::return
int sin16s::return#0 // 202.0
int sin16s::return#1 // 701.0
int sin16s::return#5 // 2002.0
int sin16s::sinx
int sin16s::sinx#1 // 2002.0
unsigned int sin16s::usinx
unsigned int sin16s::usinx#0 // 166.83333333333334
unsigned int sin16s::usinx#1 // 500.5
unsigned long sin16s::x
unsigned long sin16s::x#0 // 1552.0
unsigned long sin16s::x#1 // 2002.0
unsigned long sin16s::x#2 // 2002.0
unsigned long sin16s::x#4 // 2502.5
unsigned long sin16s::x#6 // 3003.0
unsigned int sin16s::x1
unsigned int sin16s::x1#0 // 318.5
unsigned int sin16s::x2
unsigned int sin16s::x2#0 // 2002.0
unsigned int sin16s::x3
unsigned int sin16s::x3#0 // 500.5
unsigned int sin16s::x3_6
unsigned int sin16s::x3_6#0 // 2002.0
unsigned int sin16s::x4
unsigned int sin16s::x4#0 // 2002.0
unsigned int sin16s::x5
unsigned int sin16s::x5#0 // 2002.0
unsigned int sin16s::x5_128
unsigned int sin16s::x5_128#0 // 2002.0
void sin16s_gen2(int *sintab , unsigned int wavelength , int min , int max)
long sin16s_gen2::$6 // 202.0
unsigned int sin16s_gen2::$8 // 101.0
int sin16s_gen2::ampl
unsigned int sin16s_gen2::i
unsigned int sin16s_gen2::i#1 // 202.0
unsigned int sin16s_gen2::i#2 // 23.307692307692307
int sin16s_gen2::max
int sin16s_gen2::min
int sin16s_gen2::offs
int *sin16s_gen2::sintab
int *sin16s_gen2::sintab#0 // 67.33333333333333
int *sin16s_gen2::sintab#2 // 27.545454545454547
unsigned long sin16s_gen2::step
unsigned long sin16s_gen2::step#0 // 7.466666666666667
unsigned int sin16s_gen2::wavelength
unsigned long sin16s_gen2::x
unsigned long sin16s_gen2::x#1 // 101.0
unsigned long sin16s_gen2::x#2 // 25.25
unsigned int xsin_idx
unsigned int xsin_idx#12 // 37.875
unsigned int xsin_idx#2 // 101.0
unsigned int xsin_idx#21 // 101.0

Initial phi equivalence classes
[ main::ch#2 main::ch#1 ]
[ memset::str#3 ]
[ memset::c#4 ]
[ memset::dst#2 memset::dst#4 memset::dst#1 ]
[ sin16s_gen2::i#2 sin16s_gen2::i#1 ]
[ sin16s_gen2::x#2 sin16s_gen2::x#1 ]
[ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ]
[ xsin_idx#12 xsin_idx#21 xsin_idx#2 ]
[ sin16s::isUpper#2 ]
[ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ]
[ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ]
[ mul16s::m#4 mul16s::m#1 mul16s::m#0 ]
[ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ]
[ render_logo::logo_idx#10 render_logo::logo_idx#3 ]
[ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ]
[ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ]
[ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ]
[ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ]
[ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ]
[ divr16u::i#2 divr16u::i#1 ]
[ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ]
[ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ]
[ mulu16_sel::select#5 ]
[ mul16u::b#2 mul16u::b#0 ]
[ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ]
[ mul16u::res#2 mul16u::res#6 mul16u::res#1 ]
[ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
Added variable memset::end#0 to live range equivalence class [ memset::end#0 ]
Added variable div32u16u::return#0 to live range equivalence class [ div32u16u::return#0 ]
Added variable sin16s_gen2::step#0 to live range equivalence class [ sin16s_gen2::step#0 ]
Added variable sin16s::return#0 to live range equivalence class [ sin16s::return#0 ]
Added variable mul16s::a#0 to live range equivalence class [ mul16s::a#0 ]
Added variable mul16s::return#0 to live range equivalence class [ mul16s::return#0 ]
Added variable sin16s_gen2::$6 to live range equivalence class [ sin16s_gen2::$6 ]
Added variable sin16s_gen2::$8 to live range equivalence class [ sin16s_gen2::$8 ]
Added variable loop::$7 to live range equivalence class [ loop::$7 ]
Added variable loop::$2 to live range equivalence class [ loop::$2 ]
Added variable loop::xpos#0 to live range equivalence class [ loop::xpos#0 ]
Added variable render_logo::xpos#0 to live range equivalence class [ render_logo::xpos#0 ]
Added variable divr16u::return#2 to live range equivalence class [ divr16u::return#2 ]
Added variable div32u16u::quotient_hi#0 to live range equivalence class [ div32u16u::quotient_hi#0 ]
Added variable divr16u::return#3 to live range equivalence class [ divr16u::return#3 ]
Added variable div32u16u::quotient_lo#0 to live range equivalence class [ div32u16u::quotient_lo#0 ]
Added variable div32u16u::return#1 to live range equivalence class [ div32u16u::return#1 ]
Added variable sin16s::$4 to live range equivalence class [ sin16s::$4 ]
Added variable sin16s::x1#0 to live range equivalence class [ sin16s::x1#0 ]
Added variable mulu16_sel::return#0 to live range equivalence class [ mulu16_sel::return#0 ]
Added variable sin16s::x2#0 to live range equivalence class [ sin16s::x2#0 ]
Added variable mulu16_sel::return#1 to live range equivalence class [ mulu16_sel::return#1 ]
Added variable sin16s::x3#0 to live range equivalence class [ sin16s::x3#0 ]
Added variable mulu16_sel::return#2 to live range equivalence class [ mulu16_sel::return#2 ]
Added variable sin16s::x3_6#0 to live range equivalence class [ sin16s::x3_6#0 ]
Added variable sin16s::usinx#0 to live range equivalence class [ sin16s::usinx#0 ]
Added variable mulu16_sel::return#10 to live range equivalence class [ mulu16_sel::return#10 ]
Added variable sin16s::x4#0 to live range equivalence class [ sin16s::x4#0 ]
Added variable mulu16_sel::return#11 to live range equivalence class [ mulu16_sel::return#11 ]
Added variable sin16s::x5#0 to live range equivalence class [ sin16s::x5#0 ]
Added variable sin16s::x5_128#0 to live range equivalence class [ sin16s::x5_128#0 ]
Added variable sin16s::usinx#1 to live range equivalence class [ sin16s::usinx#1 ]
Added variable mul16u::return#3 to live range equivalence class [ mul16u::return#3 ]
Added variable mul16s::$6 to live range equivalence class [ mul16s::$6 ]
Added variable mul16s::$11 to live range equivalence class [ mul16s::$11 ]
Added variable mul16s::return#1 to live range equivalence class [ mul16s::return#1 ]
Added variable render_logo::$25 to live range equivalence class [ render_logo::$25 ]
Added variable render_logo::$0 to live range equivalence class [ render_logo::$0 ]
Added variable render_logo::$1 to live range equivalence class [ render_logo::$1 ]
Added variable render_logo::$2 to live range equivalence class [ render_logo::$2 ]
Added variable render_logo::x_char#0 to live range equivalence class [ render_logo::x_char#0 ]
Added variable render_logo::$30 to live range equivalence class [ render_logo::$30 ]
Added variable render_logo::$33 to live range equivalence class [ render_logo::$33 ]
Added variable render_logo::$36 to live range equivalence class [ render_logo::$36 ]
Added variable render_logo::$39 to live range equivalence class [ render_logo::$39 ]
Added variable render_logo::$42 to live range equivalence class [ render_logo::$42 ]
Added variable render_logo::logo_idx#1 to live range equivalence class [ render_logo::logo_idx#1 ]
Added variable render_logo::$70 to live range equivalence class [ render_logo::$70 ]
Added variable render_logo::$73 to live range equivalence class [ render_logo::$73 ]
Added variable render_logo::$76 to live range equivalence class [ render_logo::$76 ]
Added variable render_logo::$79 to live range equivalence class [ render_logo::$79 ]
Added variable render_logo::$82 to live range equivalence class [ render_logo::$82 ]
Added variable divr16u::$1 to live range equivalence class [ divr16u::$1 ]
Added variable divr16u::$2 to live range equivalence class [ divr16u::$2 ]
Added variable rem16u#14 to live range equivalence class [ rem16u#14 ]
Added variable mul16u::return#0 to live range equivalence class [ mul16u::return#0 ]
Added variable mulu16_sel::$0 to live range equivalence class [ mulu16_sel::$0 ]
Added variable mulu16_sel::$1 to live range equivalence class [ mulu16_sel::$1 ]
Added variable mulu16_sel::return#12 to live range equivalence class [ mulu16_sel::return#12 ]
Added variable mul16u::$1 to live range equivalence class [ mul16u::$1 ]
Complete equivalence classes
[ main::ch#2 main::ch#1 ]
[ memset::str#3 ]
[ memset::c#4 ]
[ memset::dst#2 memset::dst#4 memset::dst#1 ]
[ sin16s_gen2::i#2 sin16s_gen2::i#1 ]
[ sin16s_gen2::x#2 sin16s_gen2::x#1 ]
[ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ]
[ xsin_idx#12 xsin_idx#21 xsin_idx#2 ]
[ sin16s::isUpper#2 ]
[ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ]
[ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ]
[ mul16s::m#4 mul16s::m#1 mul16s::m#0 ]
[ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ]
[ render_logo::logo_idx#10 render_logo::logo_idx#3 ]
[ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ]
[ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ]
[ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ]
[ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ]
[ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ]
[ divr16u::i#2 divr16u::i#1 ]
[ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ]
[ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ]
[ mulu16_sel::select#5 ]
[ mul16u::b#2 mul16u::b#0 ]
[ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ]
[ mul16u::res#2 mul16u::res#6 mul16u::res#1 ]
[ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
[ memset::end#0 ]
[ div32u16u::return#0 ]
[ sin16s_gen2::step#0 ]
[ sin16s::return#0 ]
[ mul16s::a#0 ]
[ mul16s::return#0 ]
[ sin16s_gen2::$6 ]
[ sin16s_gen2::$8 ]
[ loop::$7 ]
[ loop::$2 ]
[ loop::xpos#0 ]
[ render_logo::xpos#0 ]
[ divr16u::return#2 ]
[ div32u16u::quotient_hi#0 ]
[ divr16u::return#3 ]
[ div32u16u::quotient_lo#0 ]
[ div32u16u::return#1 ]
[ sin16s::$4 ]
[ sin16s::x1#0 ]
[ mulu16_sel::return#0 ]
[ sin16s::x2#0 ]
[ mulu16_sel::return#1 ]
[ sin16s::x3#0 ]
[ mulu16_sel::return#2 ]
[ sin16s::x3_6#0 ]
[ sin16s::usinx#0 ]
[ mulu16_sel::return#10 ]
[ sin16s::x4#0 ]
[ mulu16_sel::return#11 ]
[ sin16s::x5#0 ]
[ sin16s::x5_128#0 ]
[ sin16s::usinx#1 ]
[ mul16u::return#3 ]
[ mul16s::$6 ]
[ mul16s::$11 ]
[ mul16s::return#1 ]
[ render_logo::$25 ]
[ render_logo::$0 ]
[ render_logo::$1 ]
[ render_logo::$2 ]
[ render_logo::x_char#0 ]
[ render_logo::$30 ]
[ render_logo::$33 ]
[ render_logo::$36 ]
[ render_logo::$39 ]
[ render_logo::$42 ]
[ render_logo::logo_idx#1 ]
[ render_logo::$70 ]
[ render_logo::$73 ]
[ render_logo::$76 ]
[ render_logo::$79 ]
[ render_logo::$82 ]
[ divr16u::$1 ]
[ divr16u::$2 ]
[ rem16u#14 ]
[ mul16u::return#0 ]
[ mulu16_sel::$0 ]
[ mulu16_sel::$1 ]
[ mulu16_sel::return#12 ]
[ mul16u::$1 ]
Allocated zp[1]:2 [ main::ch#2 main::ch#1 ]
Allocated zp[2]:3 [ memset::str#3 ]
Allocated zp[1]:5 [ memset::c#4 ]
Allocated zp[2]:6 [ memset::dst#2 memset::dst#4 memset::dst#1 ]
Allocated zp[2]:8 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ]
Allocated zp[4]:10 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ]
Allocated zp[2]:14 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ]
Allocated zp[2]:16 [ xsin_idx#12 xsin_idx#21 xsin_idx#2 ]
Allocated zp[1]:18 [ sin16s::isUpper#2 ]
Allocated zp[4]:19 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ]
Allocated zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ]
Allocated zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 ]
Allocated zp[1]:29 [ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ]
Allocated zp[1]:30 [ render_logo::logo_idx#10 render_logo::logo_idx#3 ]
Allocated zp[1]:31 [ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ]
Allocated zp[1]:32 [ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ]
Allocated zp[2]:33 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ]
Allocated zp[2]:35 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ]
Allocated zp[2]:37 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ]
Allocated zp[1]:39 [ divr16u::i#2 divr16u::i#1 ]
Allocated zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ]
Allocated zp[2]:42 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ]
Allocated zp[1]:44 [ mulu16_sel::select#5 ]
Allocated zp[2]:45 [ mul16u::b#2 mul16u::b#0 ]
Allocated zp[2]:47 [ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ]
Allocated zp[4]:49 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ]
Allocated zp[4]:53 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
Allocated zp[2]:57 [ memset::end#0 ]
Allocated zp[4]:59 [ div32u16u::return#0 ]
Allocated zp[4]:63 [ sin16s_gen2::step#0 ]
Allocated zp[2]:67 [ sin16s::return#0 ]
Allocated zp[2]:69 [ mul16s::a#0 ]
Allocated zp[4]:71 [ mul16s::return#0 ]
Allocated zp[4]:75 [ sin16s_gen2::$6 ]
Allocated zp[2]:79 [ sin16s_gen2::$8 ]
Allocated zp[2]:81 [ loop::$7 ]
Allocated zp[2]:83 [ loop::$2 ]
Allocated zp[2]:85 [ loop::xpos#0 ]
Allocated zp[2]:87 [ render_logo::xpos#0 ]
Allocated zp[2]:89 [ divr16u::return#2 ]
Allocated zp[2]:91 [ div32u16u::quotient_hi#0 ]
Allocated zp[2]:93 [ divr16u::return#3 ]
Allocated zp[2]:95 [ div32u16u::quotient_lo#0 ]
Allocated zp[4]:97 [ div32u16u::return#1 ]
Allocated zp[4]:101 [ sin16s::$4 ]
Allocated zp[2]:105 [ sin16s::x1#0 ]
Allocated zp[2]:107 [ mulu16_sel::return#0 ]
Allocated zp[2]:109 [ sin16s::x2#0 ]
Allocated zp[2]:111 [ mulu16_sel::return#1 ]
Allocated zp[2]:113 [ sin16s::x3#0 ]
Allocated zp[2]:115 [ mulu16_sel::return#2 ]
Allocated zp[2]:117 [ sin16s::x3_6#0 ]
Allocated zp[2]:119 [ sin16s::usinx#0 ]
Allocated zp[2]:121 [ mulu16_sel::return#10 ]
Allocated zp[2]:123 [ sin16s::x4#0 ]
Allocated zp[2]:125 [ mulu16_sel::return#11 ]
Allocated zp[2]:127 [ sin16s::x5#0 ]
Allocated zp[2]:129 [ sin16s::x5_128#0 ]
Allocated zp[2]:131 [ sin16s::usinx#1 ]
Allocated zp[4]:133 [ mul16u::return#3 ]
Allocated zp[2]:137 [ mul16s::$6 ]
Allocated zp[2]:139 [ mul16s::$11 ]
Allocated zp[4]:141 [ mul16s::return#1 ]
Allocated zp[1]:145 [ render_logo::$25 ]
Allocated zp[1]:146 [ render_logo::$0 ]
Allocated zp[1]:147 [ render_logo::$1 ]
Allocated zp[2]:148 [ render_logo::$2 ]
Allocated zp[1]:150 [ render_logo::x_char#0 ]
Allocated zp[1]:151 [ render_logo::$30 ]
Allocated zp[1]:152 [ render_logo::$33 ]
Allocated zp[1]:153 [ render_logo::$36 ]
Allocated zp[1]:154 [ render_logo::$39 ]
Allocated zp[1]:155 [ render_logo::$42 ]
Allocated zp[1]:156 [ render_logo::logo_idx#1 ]
Allocated zp[1]:157 [ render_logo::$70 ]
Allocated zp[1]:158 [ render_logo::$73 ]
Allocated zp[1]:159 [ render_logo::$76 ]
Allocated zp[1]:160 [ render_logo::$79 ]
Allocated zp[1]:161 [ render_logo::$82 ]
Allocated zp[1]:162 [ divr16u::$1 ]
Allocated zp[1]:163 [ divr16u::$2 ]
Allocated zp[2]:164 [ rem16u#14 ]
Allocated zp[4]:166 [ mul16u::return#0 ]
Allocated zp[4]:170 [ mulu16_sel::$0 ]
Allocated zp[4]:174 [ mulu16_sel::$1 ]
Allocated zp[2]:178 [ mulu16_sel::return#12 ]
Allocated zp[1]:180 [ mul16u::$1 ]
REGISTER UPLIFT POTENTIAL REGISTERS
Statement [1] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = WHITE [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [2] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) = DARK_GREY [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [3] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR) = *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [4] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2) = BLACK [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [6] *D018 = main::toD0181_return#0 [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [7] *D016 = VICII_MCM [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [21] memset::end#0 = (char *)memset::str#3 + $3e8 [ memset::str#3 memset::c#4 memset::end#0 ] ( memset:8 [ memset::str#3 memset::c#4 memset::end#0 ] { }  memset:10 [ memset::str#3 memset::c#4 memset::end#0 ] { }  ) always clobbers reg byte a 
Removing always clobbered register reg byte a as potential for zp[1]:5 [ memset::c#4 ]
Statement [22] memset::dst#4 = (char *)memset::str#3 [ memset::c#4 memset::end#0 memset::dst#4 ] ( memset:8 [ memset::c#4 memset::end#0 memset::dst#4 ] { }  memset:10 [ memset::c#4 memset::end#0 memset::dst#4 ] { }  ) always clobbers reg byte a 
Statement [24] if(memset::dst#2!=memset::end#0) goto memset::@3 [ memset::c#4 memset::end#0 memset::dst#2 ] ( memset:8 [ memset::c#4 memset::end#0 memset::dst#2 ] { }  memset:10 [ memset::c#4 memset::end#0 memset::dst#2 ] { }  ) always clobbers reg byte a 
Statement [26] *memset::dst#2 = memset::c#4 [ memset::c#4 memset::end#0 memset::dst#2 ] ( memset:8 [ memset::c#4 memset::end#0 memset::dst#2 ] { }  memset:10 [ memset::c#4 memset::end#0 memset::dst#2 ] { }  ) always clobbers reg byte a reg byte y 
Removing always clobbered register reg byte y as potential for zp[1]:5 [ memset::c#4 ]
Statement [30] div32u16u::return#0 = div32u16u::return#1 [ div32u16u::return#0 ] ( sin16s_gen2:16 [ div32u16u::return#0 ] { { div32u16u::return#0 = div32u16u::return#1 } }  ) always clobbers reg byte a 
Statement [31] sin16s_gen2::step#0 = div32u16u::return#0 [ sin16s_gen2::step#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 ] { }  ) always clobbers reg byte a 
Statement [33] if(sin16s_gen2::i#2<XSIN_SIZE) goto sin16s_gen2::@2 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] { }  ) always clobbers reg byte a 
Statement [35] sin16s::x#0 = sin16s_gen2::x#2 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [37] sin16s::return#0 = sin16s::return#1 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::return#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [38] mul16s::a#0 = sin16s::return#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [40] mul16s::return#0 = mul16s::return#1 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [41] sin16s_gen2::$6 = mul16s::return#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$6 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$6 ] { }  ) always clobbers reg byte a 
Statement [42] sin16s_gen2::$8 = word1  sin16s_gen2::$6 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] { }  ) always clobbers reg byte a 
Statement [43] *sin16s_gen2::sintab#2 = (int)sin16s_gen2::$8 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] { }  ) always clobbers reg byte a reg byte y 
Statement [44] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_INT [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#0 ] { }  ) always clobbers reg byte a 
Statement [45] sin16s_gen2::x#1 = sin16s_gen2::x#2 + sin16s_gen2::step#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#1 sin16s_gen2::sintab#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#1 sin16s_gen2::sintab#0 ] { }  ) always clobbers reg byte a 
Statement [49] if(*((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER)!=$ff) goto loop::@2 [ xsin_idx#12 ] ( loop:18 [ xsin_idx#12 ] { }  ) always clobbers reg byte a 
Statement [51] loop::$7 = xsin_idx#12 << 1 [ xsin_idx#12 loop::$7 ] ( loop:18 [ xsin_idx#12 loop::$7 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [52] loop::$2 = xsin + loop::$7 [ xsin_idx#12 loop::$2 ] ( loop:18 [ xsin_idx#12 loop::$2 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [53] loop::xpos#0 = *loop::$2 [ xsin_idx#12 loop::xpos#0 ] ( loop:18 [ xsin_idx#12 loop::xpos#0 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a reg byte y 
Statement [54] render_logo::xpos#0 = loop::xpos#0 [ xsin_idx#12 render_logo::xpos#0 ] ( loop:18 [ xsin_idx#12 render_logo::xpos#0 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [57] if(xsin_idx#2!=XSIN_SIZE) goto loop::@6 [ xsin_idx#2 ] ( loop:18 [ xsin_idx#2 ] { }  ) always clobbers reg byte a 
Statement [63] divr16u::return#2 = divr16u::return#0 [ divr16u::return#2 rem16u#14 ] ( sin16s_gen2:16::div32u16u:29 [ divr16u::return#2 rem16u#14 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  ) always clobbers reg byte a 
Statement [64] div32u16u::quotient_hi#0 = divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#14 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::quotient_hi#0 rem16u#14 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [65] divr16u::rem#4 = rem16u#14 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [67] divr16u::return#3 = divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::quotient_hi#0 divr16u::return#3 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [68] div32u16u::quotient_lo#0 = divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] { { div32u16u::return#0 = div32u16u::return#1 } }  ) always clobbers reg byte a 
Statement [69] div32u16u::return#1 = div32u16u::quotient_hi#0 dw= div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::return#1 ] { { div32u16u::return#0 = div32u16u::return#1 } }  ) always clobbers reg byte a 
Statement [71] if(sin16s::x#0<PI_u4f28) goto sin16s::@1 [ sin16s::x#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [72] sin16s::x#1 = sin16s::x#0 - PI_u4f28 [ sin16s::x#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [74] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#4 sin16s::isUpper#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Removing always clobbered register reg byte a as potential for zp[1]:18 [ sin16s::isUpper#2 ]
Statement [75] sin16s::x#2 = PI_u4f28 - sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [77] sin16s::$4 = sin16s::x#6 << 3 [ sin16s::isUpper#2 sin16s::$4 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::$4 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [78] sin16s::x1#0 = word1  sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [79] mulu16_sel::v1#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [80] mulu16_sel::v2#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [82] mulu16_sel::return#0 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [83] sin16s::x2#0 = mulu16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [84] mulu16_sel::v1#1 = sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [85] mulu16_sel::v2#1 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#1 mulu16_sel::v2#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#1 mulu16_sel::v2#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [87] mulu16_sel::return#1 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [88] sin16s::x3#0 = mulu16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  ) always clobbers reg byte a 
Statement [89] mulu16_sel::v1#2 = sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v1#2 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v1#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  ) always clobbers reg byte a 
Statement [91] mulu16_sel::return#2 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#2 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  ) always clobbers reg byte a 
Statement [92] sin16s::x3_6#0 = mulu16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [93] sin16s::usinx#0 = sin16s::x1#0 - sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [94] mulu16_sel::v1#3 = sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#3 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#3 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [95] mulu16_sel::v2#3 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#3 mulu16_sel::v2#3 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#3 mulu16_sel::v2#3 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [97] mulu16_sel::return#10 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#10 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#10 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [98] sin16s::x4#0 = mulu16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [99] mulu16_sel::v1#4 = sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#4 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#4 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [100] mulu16_sel::v2#4 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v1#4 mulu16_sel::v2#4 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v1#4 mulu16_sel::v2#4 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [102] mulu16_sel::return#11 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#11 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#11 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [103] sin16s::x5#0 = mulu16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [104] sin16s::x5_128#0 = sin16s::x5#0 >> 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [105] sin16s::usinx#1 = sin16s::usinx#0 + sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [107] sin16s::sinx#1 = - (int)sin16s::usinx#1 [ sin16s::sinx#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::sinx#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [110] sin16s::return#5 = (int)sin16s::usinx#1 [ sin16s::return#5 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::return#5 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [111] mul16u::a#2 = (unsigned int)mul16s::a#0 [ mul16s::a#0 mul16u::a#2 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::a#2 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [113] mul16u::return#3 = mul16u::res#2 [ mul16s::a#0 mul16u::return#3 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::return#3 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [114] mul16s::m#0 = mul16u::return#3 [ mul16s::a#0 mul16s::m#0 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16s::m#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [115] if(mul16s::a#0>=0) goto mul16s::@1 [ mul16s::m#0 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [116] mul16s::$6 = word1  mul16s::m#0 [ mul16s::m#0 mul16s::$6 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#0 mul16s::$6 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [117] mul16s::$11 = mul16s::$6 - (unsigned int)sin16s_gen2::ampl#0 [ mul16s::m#0 mul16s::$11 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#0 mul16s::$11 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [118] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11 [ mul16s::m#1 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#1 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [120] mul16s::return#1 = (long)mul16s::m#4 [ mul16s::return#1 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#1 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [122] render_logo::$25 = (char)render_logo::xpos#0 [ render_logo::xpos#0 render_logo::$25 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::xpos#0 render_logo::$25 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [124] render_logo::$1 = VICII_MCM | render_logo::$0 [ render_logo::xpos#0 render_logo::$1 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::xpos#0 render_logo::$1 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [126] render_logo::$2 = render_logo::xpos#0 >> 3 [ render_logo::xpos#0 render_logo::$2 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::xpos#0 render_logo::$2 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [127] render_logo::x_char#0 = (signed char)render_logo::$2 [ render_logo::xpos#0 render_logo::x_char#0 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::xpos#0 render_logo::x_char#0 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [128] if(render_logo::xpos#0<0) goto render_logo::@1 [ render_logo::x_char#0 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Removing always clobbered register reg byte a as potential for zp[1]:150 [ render_logo::x_char#0 ]
Statement [147] SCREEN[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Removing always clobbered register reg byte a as potential for zp[1]:29 [ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ]
Statement [148] (SCREEN+$28*1)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [149] (SCREEN+$28*2)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [150] (SCREEN+$28*3)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [151] (SCREEN+$28*4)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [152] (SCREEN+$28*5)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [154] render_logo::logo_idx#1 = - render_logo::x_char#0 [ render_logo::logo_idx#1 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::logo_idx#1 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [160] SCREEN[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Removing always clobbered register reg byte a as potential for zp[1]:32 [ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ]
Statement [161] (SCREEN+$28*1)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [162] (SCREEN+$28*2)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [163] (SCREEN+$28*3)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [164] (SCREEN+$28*4)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [165] (SCREEN+$28*5)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [186] divr16u::rem#1 = divr16u::rem#0 | 1 [ divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( sin16s_gen2:16::div32u16u:29::divr16u:62 [ divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  sin16s_gen2:16::div32u16u:29::divr16u:66 [ div32u16u::quotient_hi#0 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Removing always clobbered register reg byte a as potential for zp[1]:39 [ divr16u::i#2 divr16u::i#1 ]
Statement [190] if(divr16u::rem#6<XSIN_SIZE) goto divr16u::@3 [ divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( sin16s_gen2:16::div32u16u:29::divr16u:62 [ divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  sin16s_gen2:16::div32u16u:29::divr16u:66 [ div32u16u::quotient_hi#0 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [192] divr16u::rem#2 = divr16u::rem#6 - XSIN_SIZE [ divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( sin16s_gen2:16::div32u16u:29::divr16u:62 [ divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  sin16s_gen2:16::div32u16u:29::divr16u:66 [ div32u16u::quotient_hi#0 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [196] rem16u#14 = divr16u::rem#11 [ divr16u::return#0 rem16u#14 ] ( sin16s_gen2:16::div32u16u:29::divr16u:62 [ divr16u::return#0 rem16u#14 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  sin16s_gen2:16::div32u16u:29::divr16u:66 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#14 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [199] mul16u::a#0 = mulu16_sel::v1#5 [ mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Removing always clobbered register reg byte a as potential for zp[1]:44 [ mulu16_sel::select#5 ]
Statement [200] mul16u::b#0 = mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [202] mul16u::return#0 = mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#0 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [203] mulu16_sel::$0 = mul16u::return#0 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [204] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 [ mulu16_sel::$1 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [205] mulu16_sel::return#12 = word1  mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [208] mul16u::mb#0 = (unsigned long)mul16u::b#2 [ mul16u::a#6 mul16u::mb#0 ] ( sin16s_gen2:16::mul16s:39::mul16u:112 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::a#6 mul16u::mb#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:81::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [210] if(mul16u::a#3!=0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] ( sin16s_gen2:16::mul16s:39::mul16u:112 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:81::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [212] mul16u::$1 = mul16u::a#3 & 1 [ mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] ( sin16s_gen2:16::mul16s:39::mul16u:112 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:81::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [214] mul16u::res#1 = mul16u::res#2 + mul16u::mb#2 [ mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] ( sin16s_gen2:16::mul16s:39::mul16u:112 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:81::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [1] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = WHITE [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [2] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) = DARK_GREY [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [3] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR) = *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [4] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2) = BLACK [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [6] *D018 = main::toD0181_return#0 [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [7] *D016 = VICII_MCM [ ] (  [ ] { }  ) always clobbers reg byte a 
Statement [21] memset::end#0 = (char *)memset::str#3 + $3e8 [ memset::str#3 memset::c#4 memset::end#0 ] ( memset:8 [ memset::str#3 memset::c#4 memset::end#0 ] { }  memset:10 [ memset::str#3 memset::c#4 memset::end#0 ] { }  ) always clobbers reg byte a 
Statement [22] memset::dst#4 = (char *)memset::str#3 [ memset::c#4 memset::end#0 memset::dst#4 ] ( memset:8 [ memset::c#4 memset::end#0 memset::dst#4 ] { }  memset:10 [ memset::c#4 memset::end#0 memset::dst#4 ] { }  ) always clobbers reg byte a 
Statement [24] if(memset::dst#2!=memset::end#0) goto memset::@3 [ memset::c#4 memset::end#0 memset::dst#2 ] ( memset:8 [ memset::c#4 memset::end#0 memset::dst#2 ] { }  memset:10 [ memset::c#4 memset::end#0 memset::dst#2 ] { }  ) always clobbers reg byte a 
Statement [26] *memset::dst#2 = memset::c#4 [ memset::c#4 memset::end#0 memset::dst#2 ] ( memset:8 [ memset::c#4 memset::end#0 memset::dst#2 ] { }  memset:10 [ memset::c#4 memset::end#0 memset::dst#2 ] { }  ) always clobbers reg byte a reg byte y 
Statement [30] div32u16u::return#0 = div32u16u::return#1 [ div32u16u::return#0 ] ( sin16s_gen2:16 [ div32u16u::return#0 ] { { div32u16u::return#0 = div32u16u::return#1 } }  ) always clobbers reg byte a 
Statement [31] sin16s_gen2::step#0 = div32u16u::return#0 [ sin16s_gen2::step#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 ] { }  ) always clobbers reg byte a 
Statement [33] if(sin16s_gen2::i#2<XSIN_SIZE) goto sin16s_gen2::@2 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] { }  ) always clobbers reg byte a 
Statement [35] sin16s::x#0 = sin16s_gen2::x#2 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [37] sin16s::return#0 = sin16s::return#1 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::return#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [38] mul16s::a#0 = sin16s::return#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [40] mul16s::return#0 = mul16s::return#1 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [41] sin16s_gen2::$6 = mul16s::return#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$6 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$6 ] { }  ) always clobbers reg byte a 
Statement [42] sin16s_gen2::$8 = word1  sin16s_gen2::$6 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] { }  ) always clobbers reg byte a 
Statement [43] *sin16s_gen2::sintab#2 = (int)sin16s_gen2::$8 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] { }  ) always clobbers reg byte a reg byte y 
Statement [44] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_INT [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#0 ] { }  ) always clobbers reg byte a 
Statement [45] sin16s_gen2::x#1 = sin16s_gen2::x#2 + sin16s_gen2::step#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#1 sin16s_gen2::sintab#0 ] ( sin16s_gen2:16 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#1 sin16s_gen2::sintab#0 ] { }  ) always clobbers reg byte a 
Statement [49] if(*((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER)!=$ff) goto loop::@2 [ xsin_idx#12 ] ( loop:18 [ xsin_idx#12 ] { }  ) always clobbers reg byte a 
Statement [51] loop::$7 = xsin_idx#12 << 1 [ xsin_idx#12 loop::$7 ] ( loop:18 [ xsin_idx#12 loop::$7 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [52] loop::$2 = xsin + loop::$7 [ xsin_idx#12 loop::$2 ] ( loop:18 [ xsin_idx#12 loop::$2 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [53] loop::xpos#0 = *loop::$2 [ xsin_idx#12 loop::xpos#0 ] ( loop:18 [ xsin_idx#12 loop::xpos#0 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a reg byte y 
Statement [54] render_logo::xpos#0 = loop::xpos#0 [ xsin_idx#12 render_logo::xpos#0 ] ( loop:18 [ xsin_idx#12 render_logo::xpos#0 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [57] if(xsin_idx#2!=XSIN_SIZE) goto loop::@6 [ xsin_idx#2 ] ( loop:18 [ xsin_idx#2 ] { }  ) always clobbers reg byte a 
Statement [63] divr16u::return#2 = divr16u::return#0 [ divr16u::return#2 rem16u#14 ] ( sin16s_gen2:16::div32u16u:29 [ divr16u::return#2 rem16u#14 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  ) always clobbers reg byte a 
Statement [64] div32u16u::quotient_hi#0 = divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#14 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::quotient_hi#0 rem16u#14 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [65] divr16u::rem#4 = rem16u#14 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [67] divr16u::return#3 = divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::quotient_hi#0 divr16u::return#3 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [68] div32u16u::quotient_lo#0 = divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] { { div32u16u::return#0 = div32u16u::return#1 } }  ) always clobbers reg byte a 
Statement [69] div32u16u::return#1 = div32u16u::quotient_hi#0 dw= div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( sin16s_gen2:16::div32u16u:29 [ div32u16u::return#1 ] { { div32u16u::return#0 = div32u16u::return#1 } }  ) always clobbers reg byte a 
Statement [71] if(sin16s::x#0<PI_u4f28) goto sin16s::@1 [ sin16s::x#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [72] sin16s::x#1 = sin16s::x#0 - PI_u4f28 [ sin16s::x#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [74] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#4 sin16s::isUpper#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [75] sin16s::x#2 = PI_u4f28 - sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [77] sin16s::$4 = sin16s::x#6 << 3 [ sin16s::isUpper#2 sin16s::$4 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::$4 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [78] sin16s::x1#0 = word1  sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [79] mulu16_sel::v1#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [80] mulu16_sel::v2#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [82] mulu16_sel::return#0 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [83] sin16s::x2#0 = mulu16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [84] mulu16_sel::v1#1 = sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [85] mulu16_sel::v2#1 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#1 mulu16_sel::v2#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#1 mulu16_sel::v2#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [87] mulu16_sel::return#1 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [88] sin16s::x3#0 = mulu16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  ) always clobbers reg byte a 
Statement [89] mulu16_sel::v1#2 = sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v1#2 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v1#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  ) always clobbers reg byte a 
Statement [91] mulu16_sel::return#2 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#2 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  ) always clobbers reg byte a 
Statement [92] sin16s::x3_6#0 = mulu16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [93] sin16s::usinx#0 = sin16s::x1#0 - sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [94] mulu16_sel::v1#3 = sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#3 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#3 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [95] mulu16_sel::v2#3 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#3 mulu16_sel::v2#3 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#3 mulu16_sel::v2#3 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [97] mulu16_sel::return#10 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#10 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#10 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [98] sin16s::x4#0 = mulu16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [99] mulu16_sel::v1#4 = sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#4 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v1#4 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [100] mulu16_sel::v2#4 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v1#4 mulu16_sel::v2#4 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v1#4 mulu16_sel::v2#4 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [102] mulu16_sel::return#11 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#11 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#11 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [103] sin16s::x5#0 = mulu16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [104] sin16s::x5_128#0 = sin16s::x5#0 >> 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [105] sin16s::usinx#1 = sin16s::usinx#0 + sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [107] sin16s::sinx#1 = - (int)sin16s::usinx#1 [ sin16s::sinx#1 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::sinx#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [110] sin16s::return#5 = (int)sin16s::usinx#1 [ sin16s::return#5 ] ( sin16s_gen2:16::sin16s:36 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::return#5 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
Statement [111] mul16u::a#2 = (unsigned int)mul16s::a#0 [ mul16s::a#0 mul16u::a#2 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::a#2 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [113] mul16u::return#3 = mul16u::res#2 [ mul16s::a#0 mul16u::return#3 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::return#3 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [114] mul16s::m#0 = mul16u::return#3 [ mul16s::a#0 mul16s::m#0 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16s::m#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [115] if(mul16s::a#0>=0) goto mul16s::@1 [ mul16s::m#0 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [116] mul16s::$6 = word1  mul16s::m#0 [ mul16s::m#0 mul16s::$6 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#0 mul16s::$6 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [117] mul16s::$11 = mul16s::$6 - (unsigned int)sin16s_gen2::ampl#0 [ mul16s::m#0 mul16s::$11 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#0 mul16s::$11 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [118] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11 [ mul16s::m#1 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#1 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [120] mul16s::return#1 = (long)mul16s::m#4 [ mul16s::return#1 ] ( sin16s_gen2:16::mul16s:39 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#1 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } }  ) always clobbers reg byte a 
Statement [122] render_logo::$25 = (char)render_logo::xpos#0 [ render_logo::xpos#0 render_logo::$25 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::xpos#0 render_logo::$25 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [124] render_logo::$1 = VICII_MCM | render_logo::$0 [ render_logo::xpos#0 render_logo::$1 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::xpos#0 render_logo::$1 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [126] render_logo::$2 = render_logo::xpos#0 >> 3 [ render_logo::xpos#0 render_logo::$2 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::xpos#0 render_logo::$2 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [127] render_logo::x_char#0 = (signed char)render_logo::$2 [ render_logo::xpos#0 render_logo::x_char#0 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::xpos#0 render_logo::x_char#0 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [128] if(render_logo::xpos#0<0) goto render_logo::@1 [ render_logo::x_char#0 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [147] SCREEN[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [148] (SCREEN+$28*1)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [149] (SCREEN+$28*2)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [150] (SCREEN+$28*3)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [151] (SCREEN+$28*4)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [152] (SCREEN+$28*5)[render_logo::screen_idx#18] = 0 [ render_logo::x_char#0 render_logo::screen_idx#18 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::x_char#0 render_logo::screen_idx#18 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [154] render_logo::logo_idx#1 = - render_logo::x_char#0 [ render_logo::logo_idx#1 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::logo_idx#1 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [160] SCREEN[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [161] (SCREEN+$28*1)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [162] (SCREEN+$28*2)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [163] (SCREEN+$28*3)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [164] (SCREEN+$28*4)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [165] (SCREEN+$28*5)[render_logo::screen_idx#15] = 0 [ render_logo::screen_idx#15 ] ( loop:18::render_logo:55 [ xsin_idx#12 render_logo::screen_idx#15 ] { { render_logo::xpos#0 = loop::xpos#0 } }  ) always clobbers reg byte a 
Statement [186] divr16u::rem#1 = divr16u::rem#0 | 1 [ divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( sin16s_gen2:16::div32u16u:29::divr16u:62 [ divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  sin16s_gen2:16::div32u16u:29::divr16u:66 [ div32u16u::quotient_hi#0 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [190] if(divr16u::rem#6<XSIN_SIZE) goto divr16u::@3 [ divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( sin16s_gen2:16::div32u16u:29::divr16u:62 [ divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  sin16s_gen2:16::div32u16u:29::divr16u:66 [ div32u16u::quotient_hi#0 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [192] divr16u::rem#2 = divr16u::rem#6 - XSIN_SIZE [ divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( sin16s_gen2:16::div32u16u:29::divr16u:62 [ divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  sin16s_gen2:16::div32u16u:29::divr16u:66 [ div32u16u::quotient_hi#0 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [196] rem16u#14 = divr16u::rem#11 [ divr16u::return#0 rem16u#14 ] ( sin16s_gen2:16::div32u16u:29::divr16u:62 [ divr16u::return#0 rem16u#14 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::return#0 = divr16u::return#2 } }  sin16s_gen2:16::div32u16u:29::divr16u:66 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#14 ] { { div32u16u::return#0 = div32u16u::return#1 } { divr16u::rem#10 = divr16u::rem#4 rem16u#14 } { divr16u::return#0 = divr16u::return#3 } }  ) always clobbers reg byte a 
Statement [199] mul16u::a#0 = mulu16_sel::v1#5 [ mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [200] mul16u::b#0 = mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#0 mul16u::b#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [202] mul16u::return#0 = mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#0 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [203] mulu16_sel::$0 = mul16u::return#0 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [204] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 [ mulu16_sel::$1 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [205] mulu16_sel::return#12 = word1  mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen2:16::sin16s:36::mulu16_sel:81 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
Statement [208] mul16u::mb#0 = (unsigned long)mul16u::b#2 [ mul16u::a#6 mul16u::mb#0 ] ( sin16s_gen2:16::mul16s:39::mul16u:112 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::a#6 mul16u::mb#0 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:81::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#6 mul16u::mb#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [210] if(mul16u::a#3!=0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] ( sin16s_gen2:16::mul16s:39::mul16u:112 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:81::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [212] mul16u::$1 = mul16u::a#3 & 1 [ mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] ( sin16s_gen2:16::mul16s:39::mul16u:112 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:81::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#3 mul16u::mb#2 mul16u::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Statement [214] mul16u::res#1 = mul16u::res#2 + mul16u::mb#2 [ mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] ( sin16s_gen2:16::mul16s:39::mul16u:112 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { mul16s::a#0 = sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:81::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:86::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:90::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:96::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen2:16::sin16s:36::mulu16_sel:101::mul16u:201 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#3 mul16u::mb#2 mul16u::res#1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
Potential registers zp[1]:2 [ main::ch#2 main::ch#1 ] : zp[1]:2 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[2]:3 [ memset::str#3 ] : zp[2]:3 , 
Potential registers zp[1]:5 [ memset::c#4 ] : zp[1]:5 , reg byte x , 
Potential registers zp[2]:6 [ memset::dst#2 memset::dst#4 memset::dst#1 ] : zp[2]:6 , 
Potential registers zp[2]:8 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] : zp[2]:8 , 
Potential registers zp[4]:10 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ] : zp[4]:10 , 
Potential registers zp[2]:14 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ] : zp[2]:14 , 
Potential registers zp[2]:16 [ xsin_idx#12 xsin_idx#21 xsin_idx#2 ] : zp[2]:16 , 
Potential registers zp[1]:18 [ sin16s::isUpper#2 ] : zp[1]:18 , reg byte x , reg byte y , 
Potential registers zp[4]:19 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] : zp[4]:19 , 
Potential registers zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] : zp[2]:23 , 
Potential registers zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 ] : zp[4]:25 , 
Potential registers zp[1]:29 [ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ] : zp[1]:29 , reg byte x , reg byte y , 
Potential registers zp[1]:30 [ render_logo::logo_idx#10 render_logo::logo_idx#3 ] : zp[1]:30 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:31 [ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ] : zp[1]:31 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:32 [ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ] : zp[1]:32 , reg byte x , reg byte y , 
Potential registers zp[2]:33 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] : zp[2]:33 , 
Potential registers zp[2]:35 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] : zp[2]:35 , 
Potential registers zp[2]:37 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] : zp[2]:37 , 
Potential registers zp[1]:39 [ divr16u::i#2 divr16u::i#1 ] : zp[1]:39 , reg byte x , reg byte y , 
Potential registers zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ] : zp[2]:40 , 
Potential registers zp[2]:42 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ] : zp[2]:42 , 
Potential registers zp[1]:44 [ mulu16_sel::select#5 ] : zp[1]:44 , reg byte x , reg byte y , 
Potential registers zp[2]:45 [ mul16u::b#2 mul16u::b#0 ] : zp[2]:45 , 
Potential registers zp[2]:47 [ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ] : zp[2]:47 , 
Potential registers zp[4]:49 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] : zp[4]:49 , 
Potential registers zp[4]:53 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] : zp[4]:53 , 
Potential registers zp[2]:57 [ memset::end#0 ] : zp[2]:57 , 
Potential registers zp[4]:59 [ div32u16u::return#0 ] : zp[4]:59 , 
Potential registers zp[4]:63 [ sin16s_gen2::step#0 ] : zp[4]:63 , 
Potential registers zp[2]:67 [ sin16s::return#0 ] : zp[2]:67 , 
Potential registers zp[2]:69 [ mul16s::a#0 ] : zp[2]:69 , 
Potential registers zp[4]:71 [ mul16s::return#0 ] : zp[4]:71 , 
Potential registers zp[4]:75 [ sin16s_gen2::$6 ] : zp[4]:75 , 
Potential registers zp[2]:79 [ sin16s_gen2::$8 ] : zp[2]:79 , 
Potential registers zp[2]:81 [ loop::$7 ] : zp[2]:81 , 
Potential registers zp[2]:83 [ loop::$2 ] : zp[2]:83 , 
Potential registers zp[2]:85 [ loop::xpos#0 ] : zp[2]:85 , 
Potential registers zp[2]:87 [ render_logo::xpos#0 ] : zp[2]:87 , 
Potential registers zp[2]:89 [ divr16u::return#2 ] : zp[2]:89 , 
Potential registers zp[2]:91 [ div32u16u::quotient_hi#0 ] : zp[2]:91 , 
Potential registers zp[2]:93 [ divr16u::return#3 ] : zp[2]:93 , 
Potential registers zp[2]:95 [ div32u16u::quotient_lo#0 ] : zp[2]:95 , 
Potential registers zp[4]:97 [ div32u16u::return#1 ] : zp[4]:97 , 
Potential registers zp[4]:101 [ sin16s::$4 ] : zp[4]:101 , 
Potential registers zp[2]:105 [ sin16s::x1#0 ] : zp[2]:105 , 
Potential registers zp[2]:107 [ mulu16_sel::return#0 ] : zp[2]:107 , 
Potential registers zp[2]:109 [ sin16s::x2#0 ] : zp[2]:109 , 
Potential registers zp[2]:111 [ mulu16_sel::return#1 ] : zp[2]:111 , 
Potential registers zp[2]:113 [ sin16s::x3#0 ] : zp[2]:113 , 
Potential registers zp[2]:115 [ mulu16_sel::return#2 ] : zp[2]:115 , 
Potential registers zp[2]:117 [ sin16s::x3_6#0 ] : zp[2]:117 , 
Potential registers zp[2]:119 [ sin16s::usinx#0 ] : zp[2]:119 , 
Potential registers zp[2]:121 [ mulu16_sel::return#10 ] : zp[2]:121 , 
Potential registers zp[2]:123 [ sin16s::x4#0 ] : zp[2]:123 , 
Potential registers zp[2]:125 [ mulu16_sel::return#11 ] : zp[2]:125 , 
Potential registers zp[2]:127 [ sin16s::x5#0 ] : zp[2]:127 , 
Potential registers zp[2]:129 [ sin16s::x5_128#0 ] : zp[2]:129 , 
Potential registers zp[2]:131 [ sin16s::usinx#1 ] : zp[2]:131 , 
Potential registers zp[4]:133 [ mul16u::return#3 ] : zp[4]:133 , 
Potential registers zp[2]:137 [ mul16s::$6 ] : zp[2]:137 , 
Potential registers zp[2]:139 [ mul16s::$11 ] : zp[2]:139 , 
Potential registers zp[4]:141 [ mul16s::return#1 ] : zp[4]:141 , 
Potential registers zp[1]:145 [ render_logo::$25 ] : zp[1]:145 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:146 [ render_logo::$0 ] : zp[1]:146 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:147 [ render_logo::$1 ] : zp[1]:147 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[2]:148 [ render_logo::$2 ] : zp[2]:148 , 
Potential registers zp[1]:150 [ render_logo::x_char#0 ] : zp[1]:150 , reg byte x , reg byte y , 
Potential registers zp[1]:151 [ render_logo::$30 ] : zp[1]:151 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:152 [ render_logo::$33 ] : zp[1]:152 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:153 [ render_logo::$36 ] : zp[1]:153 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:154 [ render_logo::$39 ] : zp[1]:154 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:155 [ render_logo::$42 ] : zp[1]:155 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:156 [ render_logo::logo_idx#1 ] : zp[1]:156 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:157 [ render_logo::$70 ] : zp[1]:157 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:158 [ render_logo::$73 ] : zp[1]:158 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:159 [ render_logo::$76 ] : zp[1]:159 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:160 [ render_logo::$79 ] : zp[1]:160 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:161 [ render_logo::$82 ] : zp[1]:161 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:162 [ divr16u::$1 ] : zp[1]:162 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[1]:163 [ divr16u::$2 ] : zp[1]:163 , reg byte a , reg byte x , reg byte y , 
Potential registers zp[2]:164 [ rem16u#14 ] : zp[2]:164 , 
Potential registers zp[4]:166 [ mul16u::return#0 ] : zp[4]:166 , 
Potential registers zp[4]:170 [ mulu16_sel::$0 ] : zp[4]:170 , 
Potential registers zp[4]:174 [ mulu16_sel::$1 ] : zp[4]:174 , 
Potential registers zp[2]:178 [ mulu16_sel::return#12 ] : zp[2]:178 , 
Potential registers zp[1]:180 [ mul16u::$1 ] : zp[1]:180 , reg byte a , reg byte x , reg byte y , 

REGISTER UPLIFT SCOPES
Uplift Scope [mul16u] 34,287,289.43: zp[4]:49 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] 24,500,004.57: zp[4]:53 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] 20,000,002: zp[1]:180 [ mul16u::$1 ] 16,750,839.67: zp[2]:47 [ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ] 30,003: zp[2]:45 [ mul16u::b#2 mul16u::b#0 ] 20,002: zp[4]:166 [ mul16u::return#0 ] 2,002: zp[4]:133 [ mul16u::return#3 ] 
Uplift Scope [render_logo] 501,928.1: zp[1]:29 [ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ] 494,235.71: zp[1]:32 [ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ] 266,361.86: zp[1]:31 [ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ] 257,145.43: zp[1]:30 [ render_logo::logo_idx#10 render_logo::logo_idx#3 ] 200,002: zp[1]:151 [ render_logo::$30 ] 200,002: zp[1]:152 [ render_logo::$33 ] 200,002: zp[1]:153 [ render_logo::$36 ] 200,002: zp[1]:154 [ render_logo::$39 ] 200,002: zp[1]:155 [ render_logo::$42 ] 200,002: zp[1]:157 [ render_logo::$70 ] 200,002: zp[1]:158 [ render_logo::$73 ] 200,002: zp[1]:159 [ render_logo::$76 ] 200,002: zp[1]:160 [ render_logo::$79 ] 200,002: zp[1]:161 [ render_logo::$82 ] 2,002: zp[1]:145 [ render_logo::$25 ] 2,002: zp[1]:146 [ render_logo::$0 ] 2,002: zp[1]:147 [ render_logo::$1 ] 1,001: zp[2]:148 [ render_logo::$2 ] 1,001: zp[1]:156 [ render_logo::logo_idx#1 ] 300.43: zp[2]:87 [ render_logo::xpos#0 ] 182: zp[1]:150 [ render_logo::x_char#0 ] 
Uplift Scope [divr16u] 90,147.42: zp[2]:33 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] 31,817.75: zp[2]:37 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] 20,002: zp[1]:162 [ divr16u::$1 ] 20,002: zp[1]:163 [ divr16u::$2 ] 16,540.12: zp[1]:39 [ divr16u::i#2 divr16u::i#1 ] 7,930.39: zp[2]:35 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] 202: zp[2]:89 [ divr16u::return#2 ] 202: zp[2]:93 [ divr16u::return#3 ] 
Uplift Scope [mulu16_sel] 21,012: zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ] 20,002: zp[4]:170 [ mulu16_sel::$0 ] 20,002: zp[4]:174 [ mulu16_sel::$1 ] 15,010.5: zp[2]:42 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ] 2,143.71: zp[2]:178 [ mulu16_sel::return#12 ] 2,002: zp[2]:107 [ mulu16_sel::return#0 ] 2,002: zp[2]:111 [ mulu16_sel::return#1 ] 2,002: zp[2]:115 [ mulu16_sel::return#2 ] 2,002: zp[2]:121 [ mulu16_sel::return#10 ] 2,002: zp[2]:125 [ mulu16_sel::return#11 ] 1,666.83: zp[1]:44 [ mulu16_sel::select#5 ] 
Uplift Scope [sin16s] 11,061.5: zp[4]:19 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] 4,705: zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] 2,002: zp[4]:101 [ sin16s::$4 ] 2,002: zp[2]:109 [ sin16s::x2#0 ] 2,002: zp[2]:117 [ sin16s::x3_6#0 ] 2,002: zp[2]:123 [ sin16s::x4#0 ] 2,002: zp[2]:127 [ sin16s::x5#0 ] 2,002: zp[2]:129 [ sin16s::x5_128#0 ] 500.5: zp[2]:113 [ sin16s::x3#0 ] 500.5: zp[2]:131 [ sin16s::usinx#1 ] 318.5: zp[2]:105 [ sin16s::x1#0 ] 202: zp[2]:67 [ sin16s::return#0 ] 166.83: zp[2]:119 [ sin16s::usinx#0 ] 30.33: zp[1]:18 [ sin16s::isUpper#2 ] 
Uplift Scope [mul16s] 5,005: zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 ] 2,002: zp[2]:137 [ mul16s::$6 ] 2,002: zp[2]:139 [ mul16s::$11 ] 367.33: zp[4]:141 [ mul16s::return#1 ] 220.4: zp[2]:69 [ mul16s::a#0 ] 202: zp[4]:71 [ mul16s::return#0 ] 
Uplift Scope [sin16s_gen2] 225.31: zp[2]:8 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] 202: zp[4]:75 [ sin16s_gen2::$6 ] 126.25: zp[4]:10 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ] 101: zp[2]:79 [ sin16s_gen2::$8 ] 94.88: zp[2]:14 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ] 7.47: zp[4]:63 [ sin16s_gen2::step#0 ] 
Uplift Scope [loop] 202: zp[2]:81 [ loop::$7 ] 202: zp[2]:83 [ loop::$2 ] 202: zp[2]:85 [ loop::xpos#0 ] 
Uplift Scope [] 239.88: zp[2]:16 [ xsin_idx#12 xsin_idx#21 xsin_idx#2 ] 220.4: zp[2]:164 [ rem16u#14 ] 
Uplift Scope [memset] 362.33: zp[2]:6 [ memset::dst#2 memset::dst#4 memset::dst#1 ] 18.67: zp[2]:57 [ memset::end#0 ] 14.43: zp[1]:5 [ memset::c#4 ] 0: zp[2]:3 [ memset::str#3 ] 
Uplift Scope [div32u16u] 202: zp[2]:95 [ div32u16u::quotient_lo#0 ] 40.4: zp[2]:91 [ div32u16u::quotient_hi#0 ] 37.33: zp[4]:97 [ div32u16u::return#1 ] 22: zp[4]:59 [ div32u16u::return#0 ] 
Uplift Scope [main] 38.5: zp[1]:2 [ main::ch#2 main::ch#1 ] 
Uplift Scope [MOS6526_CIA] 
Uplift Scope [MOS6569_VICII] 
Uplift Scope [MOS6581_SID] 

Uplifting [mul16u] best 72632 combination zp[4]:49 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] zp[4]:53 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] reg byte a [ mul16u::$1 ] zp[2]:47 [ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ] zp[2]:45 [ mul16u::b#2 mul16u::b#0 ] zp[4]:166 [ mul16u::return#0 ] zp[4]:133 [ mul16u::return#3 ] 
Uplifting [divr16u] best 72442 combination zp[2]:33 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp[2]:37 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp[2]:35 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] zp[2]:89 [ divr16u::return#2 ] zp[2]:93 [ divr16u::return#3 ] 
Uplifting [mulu16_sel] best 72424 combination zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ] zp[4]:170 [ mulu16_sel::$0 ] zp[4]:174 [ mulu16_sel::$1 ] zp[2]:42 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ] zp[2]:178 [ mulu16_sel::return#12 ] zp[2]:107 [ mulu16_sel::return#0 ] zp[2]:111 [ mulu16_sel::return#1 ] zp[2]:115 [ mulu16_sel::return#2 ] zp[2]:121 [ mulu16_sel::return#10 ] zp[2]:125 [ mulu16_sel::return#11 ] reg byte x [ mulu16_sel::select#5 ] 
Uplifting [sin16s] best 72417 combination zp[4]:19 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] zp[4]:101 [ sin16s::$4 ] zp[2]:109 [ sin16s::x2#0 ] zp[2]:117 [ sin16s::x3_6#0 ] zp[2]:123 [ sin16s::x4#0 ] zp[2]:127 [ sin16s::x5#0 ] zp[2]:129 [ sin16s::x5_128#0 ] zp[2]:113 [ sin16s::x3#0 ] zp[2]:131 [ sin16s::usinx#1 ] zp[2]:105 [ sin16s::x1#0 ] zp[2]:67 [ sin16s::return#0 ] zp[2]:119 [ sin16s::usinx#0 ] reg byte y [ sin16s::isUpper#2 ] 
Uplifting [mul16s] best 72417 combination zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 ] zp[2]:137 [ mul16s::$6 ] zp[2]:139 [ mul16s::$11 ] zp[4]:141 [ mul16s::return#1 ] zp[2]:69 [ mul16s::a#0 ] zp[4]:71 [ mul16s::return#0 ] 
Uplifting [sin16s_gen2] best 72417 combination zp[2]:8 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] zp[4]:75 [ sin16s_gen2::$6 ] zp[4]:10 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ] zp[2]:79 [ sin16s_gen2::$8 ] zp[2]:14 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ] zp[4]:63 [ sin16s_gen2::step#0 ] 
Uplifting [loop] best 72417 combination zp[2]:81 [ loop::$7 ] zp[2]:83 [ loop::$2 ] zp[2]:85 [ loop::xpos#0 ] 
Uplifting [] best 72417 combination zp[2]:16 [ xsin_idx#12 xsin_idx#21 xsin_idx#2 ] zp[2]:164 [ rem16u#14 ] 
Uplifting [memset] best 72401 combination zp[2]:6 [ memset::dst#2 memset::dst#4 memset::dst#1 ] zp[2]:57 [ memset::end#0 ] reg byte x [ memset::c#4 ] zp[2]:3 [ memset::str#3 ] 
Uplifting [div32u16u] best 72401 combination zp[2]:95 [ div32u16u::quotient_lo#0 ] zp[2]:91 [ div32u16u::quotient_hi#0 ] zp[4]:97 [ div32u16u::return#1 ] zp[4]:59 [ div32u16u::return#0 ] 
Uplifting [main] best 72281 combination reg byte x [ main::ch#2 main::ch#1 ] 
Uplifting [MOS6526_CIA] best 72281 combination 
Uplifting [MOS6569_VICII] best 72281 combination 
Uplifting [MOS6581_SID] best 72281 combination 
Attempting to uplift remaining variables inzp[1]:29 [ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ]
Uplifting [render_logo] best 67181 combination reg byte y [ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ] 
Attempting to uplift remaining variables inzp[1]:32 [ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ]
Uplifting [render_logo] best 62381 combination reg byte y [ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ] 
Attempting to uplift remaining variables inzp[1]:31 [ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ]
Uplifting [render_logo] best 62381 combination zp[1]:31 [ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ] 
Attempting to uplift remaining variables inzp[1]:30 [ render_logo::logo_idx#10 render_logo::logo_idx#3 ]
Uplifting [render_logo] best 62381 combination zp[1]:30 [ render_logo::logo_idx#10 render_logo::logo_idx#3 ] 
Attempting to uplift remaining variables inzp[1]:151 [ render_logo::$30 ]
Uplifting [render_logo] best 61981 combination reg byte a [ render_logo::$30 ] 
Attempting to uplift remaining variables inzp[1]:152 [ render_logo::$33 ]
Uplifting [render_logo] best 61581 combination reg byte a [ render_logo::$33 ] 
Attempting to uplift remaining variables inzp[1]:153 [ render_logo::$36 ]
Uplifting [render_logo] best 61181 combination reg byte a [ render_logo::$36 ] 
Attempting to uplift remaining variables inzp[1]:154 [ render_logo::$39 ]
Uplifting [render_logo] best 60781 combination reg byte a [ render_logo::$39 ] 
Attempting to uplift remaining variables inzp[1]:155 [ render_logo::$42 ]
Uplifting [render_logo] best 60381 combination reg byte a [ render_logo::$42 ] 
Attempting to uplift remaining variables inzp[1]:157 [ render_logo::$70 ]
Uplifting [render_logo] best 59981 combination reg byte a [ render_logo::$70 ] 
Attempting to uplift remaining variables inzp[1]:158 [ render_logo::$73 ]
Uplifting [render_logo] best 59581 combination reg byte a [ render_logo::$73 ] 
Attempting to uplift remaining variables inzp[1]:159 [ render_logo::$76 ]
Uplifting [render_logo] best 59181 combination reg byte a [ render_logo::$76 ] 
Attempting to uplift remaining variables inzp[1]:160 [ render_logo::$79 ]
Uplifting [render_logo] best 58781 combination reg byte a [ render_logo::$79 ] 
Attempting to uplift remaining variables inzp[1]:161 [ render_logo::$82 ]
Uplifting [render_logo] best 58381 combination reg byte a [ render_logo::$82 ] 
Attempting to uplift remaining variables inzp[1]:145 [ render_logo::$25 ]
Uplifting [render_logo] best 58375 combination reg byte a [ render_logo::$25 ] 
Attempting to uplift remaining variables inzp[1]:146 [ render_logo::$0 ]
Uplifting [render_logo] best 58369 combination reg byte a [ render_logo::$0 ] 
Attempting to uplift remaining variables inzp[1]:147 [ render_logo::$1 ]
Uplifting [render_logo] best 58363 combination reg byte a [ render_logo::$1 ] 
Attempting to uplift remaining variables inzp[1]:156 [ render_logo::logo_idx#1 ]
Uplifting [render_logo] best 58357 combination reg byte a [ render_logo::logo_idx#1 ] 
Attempting to uplift remaining variables inzp[1]:150 [ render_logo::x_char#0 ]
Uplifting [render_logo] best 58357 combination zp[1]:150 [ render_logo::x_char#0 ] 
Coalescing zero page register [ zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] ] with [ zp[2]:131 [ sin16s::usinx#1 ] ] - score: 2
Coalescing zero page register [ zp[2]:33 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] ] with [ zp[2]:164 [ rem16u#14 ] ] - score: 2
Coalescing zero page register [ zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ] ] with [ zp[2]:113 [ sin16s::x3#0 ] ] - score: 2
Coalescing zero page register [ zp[2]:3 [ memset::str#3 ] ] with [ zp[2]:6 [ memset::dst#2 memset::dst#4 memset::dst#1 ] ] - score: 1
Coalescing zero page register [ zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 ] ] with [ zp[2]:67 [ sin16s::return#0 ] ] - score: 1
Coalescing zero page register [ zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 ] ] with [ zp[4]:133 [ mul16u::return#3 ] ] - score: 1
Coalescing zero page register [ zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 mul16u::return#3 ] ] with [ zp[4]:141 [ mul16s::return#1 ] ] - score: 1
Coalescing zero page register [ zp[2]:37 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] ] with [ zp[2]:89 [ divr16u::return#2 ] ] - score: 1
Coalescing zero page register [ zp[2]:37 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 ] ] with [ zp[2]:93 [ divr16u::return#3 ] ] - score: 1
Coalescing zero page register [ zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 sin16s::x3#0 ] ] with [ zp[2]:109 [ sin16s::x2#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 sin16s::x3#0 sin16s::x2#0 ] ] with [ zp[2]:123 [ sin16s::x4#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:42 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ] ] with [ zp[2]:45 [ mul16u::b#2 mul16u::b#0 ] ] - score: 1
Coalescing zero page register [ zp[4]:49 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] ] with [ zp[4]:166 [ mul16u::return#0 ] ] - score: 1
Coalescing zero page register [ zp[4]:59 [ div32u16u::return#0 ] ] with [ zp[4]:63 [ sin16s_gen2::step#0 ] ] - score: 1
Coalescing zero page register [ zp[4]:59 [ div32u16u::return#0 sin16s_gen2::step#0 ] ] with [ zp[4]:97 [ div32u16u::return#1 ] ] - score: 1
Coalescing zero page register [ zp[4]:71 [ mul16s::return#0 ] ] with [ zp[4]:75 [ sin16s_gen2::$6 ] ] - score: 1
Coalescing zero page register [ zp[2]:81 [ loop::$7 ] ] with [ zp[2]:83 [ loop::$2 ] ] - score: 1
Coalescing zero page register [ zp[2]:85 [ loop::xpos#0 ] ] with [ zp[2]:87 [ render_logo::xpos#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:107 [ mulu16_sel::return#0 ] ] with [ zp[2]:178 [ mulu16_sel::return#12 ] ] - score: 1
Coalescing zero page register [ zp[2]:115 [ mulu16_sel::return#2 ] ] with [ zp[2]:117 [ sin16s::x3_6#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:125 [ mulu16_sel::return#11 ] ] with [ zp[2]:127 [ sin16s::x5#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:137 [ mul16s::$6 ] ] with [ zp[2]:139 [ mul16s::$11 ] ] - score: 1
Coalescing zero page register [ zp[4]:170 [ mulu16_sel::$0 ] ] with [ zp[4]:174 [ mulu16_sel::$1 ] ] - score: 1
Coalescing zero page register [ zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 ] ] with [ zp[2]:69 [ mul16s::a#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 mul16s::a#0 ] ] with [ zp[2]:119 [ sin16s::usinx#0 ] ] - score: 1
Coalescing zero page register [ zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 mul16u::return#3 mul16s::return#1 ] ] with [ zp[4]:49 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#0 ] ] - score: 1
Coalescing zero page register [ zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 mul16u::return#3 mul16s::return#1 mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#0 ] ] with [ zp[4]:71 [ mul16s::return#0 sin16s_gen2::$6 ] ] - score: 1
Coalescing zero page register [ zp[2]:37 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 ] ] with [ zp[2]:95 [ div32u16u::quotient_lo#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 ] ] with [ zp[2]:111 [ mulu16_sel::return#1 ] ] - score: 1
Coalescing zero page register [ zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mulu16_sel::return#1 ] ] with [ zp[2]:121 [ mulu16_sel::return#10 ] ] - score: 1
Coalescing zero page register [ zp[2]:81 [ loop::$7 loop::$2 ] ] with [ zp[2]:85 [ loop::xpos#0 render_logo::xpos#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:107 [ mulu16_sel::return#0 mulu16_sel::return#12 ] ] with [ zp[2]:115 [ mulu16_sel::return#2 sin16s::x3_6#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:107 [ mulu16_sel::return#0 mulu16_sel::return#12 mulu16_sel::return#2 sin16s::x3_6#0 ] ] with [ zp[2]:125 [ mulu16_sel::return#11 sin16s::x5#0 ] ] - score: 1
Coalescing zero page register [ zp[4]:25 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 mul16u::return#3 mul16s::return#1 mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#0 mul16s::return#0 sin16s_gen2::$6 ] ] with [ zp[4]:170 [ mulu16_sel::$0 mulu16_sel::$1 ] ] - score: 1
Coalescing zero page register [ zp[2]:107 [ mulu16_sel::return#0 mulu16_sel::return#12 mulu16_sel::return#2 sin16s::x3_6#0 mulu16_sel::return#11 sin16s::x5#0 ] ] with [ zp[2]:129 [ sin16s::x5_128#0 ] ] - score: 1
Coalescing zero page register [ zp[2]:8 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] ] with [ zp[2]:3 [ memset::str#3 memset::dst#2 memset::dst#4 memset::dst#1 ] ]
Coalescing zero page register [ zp[2]:16 [ xsin_idx#12 xsin_idx#21 xsin_idx#2 ] ] with [ zp[2]:14 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ] ]
Coalescing zero page register [ zp[2]:33 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 rem16u#14 ] ] with [ zp[2]:23 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 mul16s::a#0 sin16s::usinx#0 ] ]
Coalescing zero page register [ zp[2]:40 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mulu16_sel::return#1 mulu16_sel::return#10 ] ] with [ zp[2]:35 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] ]
Coalescing zero page register [ zp[2]:42 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 mul16u::b#2 mul16u::b#0 ] ] with [ zp[2]:37 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ] ]
Coalescing zero page register [ zp[2]:57 [ memset::end#0 ] ] with [ zp[2]:47 [ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ] ]
Coalescing zero page register [ zp[2]:81 [ loop::$7 loop::$2 loop::xpos#0 render_logo::xpos#0 ] ] with [ zp[2]:79 [ sin16s_gen2::$8 ] ]
Coalescing zero page register [ zp[4]:101 [ sin16s::$4 ] ] with [ zp[4]:53 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] ]
Coalescing zero page register [ zp[2]:105 [ sin16s::x1#0 ] ] with [ zp[2]:91 [ div32u16u::quotient_hi#0 ] ]
Coalescing zero page register [ zp[2]:137 [ mul16s::$6 mul16s::$11 ] ] with [ zp[2]:107 [ mulu16_sel::return#0 mulu16_sel::return#12 mulu16_sel::return#2 sin16s::x3_6#0 mulu16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 ] ]
Coalescing zero page register [ zp[2]:81 [ loop::$7 loop::$2 loop::xpos#0 render_logo::xpos#0 sin16s_gen2::$8 ] ] with [ zp[2]:33 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 rem16u#14 sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 mul16s::a#0 sin16s::usinx#0 ] ]
Coalescing zero page register [ zp[2]:137 [ mul16s::$6 mul16s::$11 mulu16_sel::return#0 mulu16_sel::return#12 mulu16_sel::return#2 sin16s::x3_6#0 mulu16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 ] ] with [ zp[2]:57 [ memset::end#0 mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ] ]
Coalescing zero page register [ zp[2]:148 [ render_logo::$2 ] ] with [ zp[2]:8 [ sin16s_gen2::i#2 sin16s_gen2::i#1 memset::str#3 memset::dst#2 memset::dst#4 memset::dst#1 ] ]
Allocated (was zp[4]:10) zp[4]:2 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ]
Allocated (was zp[2]:16) zp[2]:6 [ xsin_idx#12 xsin_idx#21 xsin_idx#2 sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ]
Allocated (was zp[4]:19) zp[4]:8 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ]
Allocated (was zp[4]:25) zp[4]:12 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 mul16u::return#3 mul16s::return#1 mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#0 mul16s::return#0 sin16s_gen2::$6 mulu16_sel::$0 mulu16_sel::$1 ]
Allocated (was zp[1]:30) zp[1]:16 [ render_logo::logo_idx#10 render_logo::logo_idx#3 ]
Allocated (was zp[1]:31) zp[1]:17 [ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ]
Allocated (was zp[2]:40) zp[2]:18 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mulu16_sel::return#1 mulu16_sel::return#10 divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ]
Allocated (was zp[2]:42) zp[2]:20 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 mul16u::b#2 mul16u::b#0 divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ]
Allocated (was zp[4]:59) zp[4]:22 [ div32u16u::return#0 sin16s_gen2::step#0 div32u16u::return#1 ]
Allocated (was zp[2]:81) zp[2]:26 [ loop::$7 loop::$2 loop::xpos#0 render_logo::xpos#0 sin16s_gen2::$8 divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 rem16u#14 sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 mul16s::a#0 sin16s::usinx#0 ]
Allocated (was zp[4]:101) zp[4]:28 [ sin16s::$4 mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
Allocated (was zp[2]:105) zp[2]:32 [ sin16s::x1#0 div32u16u::quotient_hi#0 ]
Allocated (was zp[2]:137) zp[2]:34 [ mul16s::$6 mul16s::$11 mulu16_sel::return#0 mulu16_sel::return#12 mulu16_sel::return#2 sin16s::x3_6#0 mulu16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 memset::end#0 mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ]
Allocated (was zp[2]:148) zp[2]:36 [ render_logo::$2 sin16s_gen2::i#2 sin16s_gen2::i#1 memset::str#3 memset::dst#2 memset::dst#4 memset::dst#1 ]
Allocated (was zp[1]:150) zp[1]:38 [ render_logo::x_char#0 ]

ASSEMBLER BEFORE OPTIMIZATION
  // File Comments
/// @file
/// Commodore 64 Registers and Constants
/// @file
/// The MOS 6526 Complex Interface Adapter (CIA)
///
/// http://archive.6502.org/datasheets/mos_6526_cia_recreated.pdf
  // Upstart
  // Commodore 64 PRG executable file
.file [name="scrolllogo.prg", type="prg", segments="Program"]
.segmentdef Program [segments="Basic, Code, Data"]
.segmentdef Basic [start=$0801]
.segmentdef Code [start=$80d]
.segmentdef Data [startAfter="Code"]
.segment Basic
:BasicUpstart(main)
  // Global Constants & labels
  /// $D016 Control register #2 Bit#4: MCM Turn Multicolor Mode on/off
  .const VICII_MCM = $10
  /// The colors of the C64
  .const BLACK = 0
  .const WHITE = 1
  .const DARK_GREY = $b
  // PI*2 in u[4.28] format
  .const PI2_u4f28 = $6487ed51
  // PI in u[4.28] format
  .const PI_u4f28 = $3243f6a9
  // PI/2 in u[4.28] format
  .const PI_HALF_u4f28 = $1921fb54
  .const XSIN_SIZE = $200
  .const SIZEOF_INT = 2
  .const OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR = $20
  .const OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1 = $22
  .const OFFSET_STRUCT_MOS6569_VICII_BG_COLOR = $21
  .const OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2 = $23
  .const OFFSET_STRUCT_MOS6569_VICII_RASTER = $12
  /// $D016 Control register 2
  /// @see #VICII_CONTROL2
  .label D016 = $d016
  /// $D018 VIC-II base addresses
  // @see #VICII_MEMORY
  .label D018 = $d018
  /// The VIC-II MOS 6567/6569
  .label VICII = $d000
  /// Color Ram
  .label COLS = $d800
  .label SCREEN = $400
  .label xsin_idx = 6
  // Remainder after unsigned 16-bit division
  .label rem16u = $1a
.segment Code
  // main
main: {
    .const toD0181_return = (>(SCREEN&$3fff)*4)|(>LOGO)/4&$f
    // asm { sei  }
    sei
    // [1] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = WHITE -- _deref_pbuc1=vbuc2 
    lda #WHITE
    sta VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR
    // [2] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) = DARK_GREY -- _deref_pbuc1=vbuc2 
    lda #DARK_GREY
    sta VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1
    // [3] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR) = *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) -- _deref_pbuc1=_deref_pbuc2 
    lda VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1
    sta VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR
    // [4] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2) = BLACK -- _deref_pbuc1=vbuc2 
    lda #BLACK
    sta VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2
    // [5] phi from main to main::toD0181 [phi:main->main::toD0181]
  toD0181_from_main:
    jmp toD0181
    // main::toD0181
  toD0181:
    jmp __b3
    // main::@3
  __b3:
    // [6] *D018 = main::toD0181_return#0 -- _deref_pbuc1=vbuc2 
    lda #toD0181_return
    sta D018
    // [7] *D016 = VICII_MCM -- _deref_pbuc1=vbuc2 
    lda #VICII_MCM
    sta D016
    // [8] call memset
    // [20] phi from main::@3 to memset [phi:main::@3->memset]
  memset_from___b3:
    // [20] phi memset::c#4 = BLACK [phi:main::@3->memset#0] -- vbuxx=vbuc1 
    ldx #BLACK
    // [20] phi memset::str#3 = (void *)SCREEN [phi:main::@3->memset#1] -- pvoz1=pvoc1 
    lda #<SCREEN
    sta.z memset.str
    lda #>SCREEN
    sta.z memset.str+1
    jsr memset
    // [9] phi from main::@3 to main::@4 [phi:main::@3->main::@4]
  __b4_from___b3:
    jmp __b4
    // main::@4
  __b4:
    // [10] call memset
    // [20] phi from main::@4 to memset [phi:main::@4->memset]
  memset_from___b4:
    // [20] phi memset::c#4 = WHITE|8 [phi:main::@4->memset#0] -- vbuxx=vbuc1 
    ldx #WHITE|8
    // [20] phi memset::str#3 = (void *)COLS [phi:main::@4->memset#1] -- pvoz1=pvoc1 
    lda #<COLS
    sta.z memset.str
    lda #>COLS
    sta.z memset.str+1
    jsr memset
    // [11] phi from main::@4 to main::@1 [phi:main::@4->main::@1]
  __b1_from___b4:
    // [11] phi main::ch#2 = 0 [phi:main::@4->main::@1#0] -- vbuxx=vbuc1 
    ldx #0
    jmp __b1
    // [11] phi from main::@1 to main::@1 [phi:main::@1->main::@1]
  __b1_from___b1:
    // [11] phi main::ch#2 = main::ch#1 [phi:main::@1->main::@1#0] -- register_copy 
    jmp __b1
    // main::@1
  __b1:
    // [12] SCREEN[main::ch#2] = main::ch#2 -- pbuc1_derefidx_vbuxx=vbuxx 
    txa
    sta SCREEN,x
    // [13] main::ch#1 = ++ main::ch#2 -- vbuxx=_inc_vbuxx 
    inx
    // [14] if(main::ch#1!=$f0) goto main::@1 -- vbuxx_neq_vbuc1_then_la1 
    cpx #$f0
    bne __b1_from___b1
    // [15] phi from main::@1 to main::@2 [phi:main::@1->main::@2]
  __b2_from___b1:
    jmp __b2
    // main::@2
  __b2:
    // [16] call sin16s_gen2
    // [28] phi from main::@2 to sin16s_gen2 [phi:main::@2->sin16s_gen2]
  sin16s_gen2_from___b2:
    jsr sin16s_gen2
    // [17] phi from main::@2 to main::@5 [phi:main::@2->main::@5]
  __b5_from___b2:
    jmp __b5
    // main::@5
  __b5:
    // [18] call loop
    // [47] phi from main::@5 to loop [phi:main::@5->loop]
  loop_from___b5:
    jsr loop
    jmp __breturn
    // main::@return
  __breturn:
    // [19] return 
    rts
}
  // memset
// Copies the character c (an unsigned char) to the first num characters of the object pointed to by the argument str.
// void * memset(__zp($24) void *str, __register(X) char c, unsigned int num)
memset: {
    .label end = $22
    .label dst = $24
    .label str = $24
    jmp __b1
    // memset::@1
  __b1:
    // [21] memset::end#0 = (char *)memset::str#3 + $3e8 -- pbuz1=pbuz2_plus_vwuc1 
    lda.z str
    clc
    adc #<$3e8
    sta.z end
    lda.z str+1
    adc #>$3e8
    sta.z end+1
    // [22] memset::dst#4 = (char *)memset::str#3
    // [23] phi from memset::@1 memset::@3 to memset::@2 [phi:memset::@1/memset::@3->memset::@2]
  __b2_from___b1:
  __b2_from___b3:
    // [23] phi memset::dst#2 = memset::dst#4 [phi:memset::@1/memset::@3->memset::@2#0] -- register_copy 
    jmp __b2
    // memset::@2
  __b2:
    // [24] if(memset::dst#2!=memset::end#0) goto memset::@3 -- pbuz1_neq_pbuz2_then_la1 
    lda.z dst+1
    cmp.z end+1
    bne __b3
    lda.z dst
    cmp.z end
    bne __b3
    jmp __breturn
    // memset::@return
  __breturn:
    // [25] return 
    rts
    // memset::@3
  __b3:
    // [26] *memset::dst#2 = memset::c#4 -- _deref_pbuz1=vbuxx 
    txa
    ldy #0
    sta (dst),y
    // [27] memset::dst#1 = ++ memset::dst#2 -- pbuz1=_inc_pbuz1 
    inc.z dst
    bne !+
    inc.z dst+1
  !:
    jmp __b2_from___b3
}
  // sin16s_gen2
// Generate signed int sine table - with values in the range min-max.
// sintab - the table to generate into
// wavelength - the number of sine points in a total sine wavelength (the size of the table)
// void sin16s_gen2(__zp(6) int *sintab, unsigned int wavelength, int min, int max)
sin16s_gen2: {
    .const min = -$140
    .const max = $140
    .label ampl = max-min
    .label __6 = $c
    .label __8 = $1a
    .label step = $16
    .label sintab = 6
    // u[4.28]
    // Iterate over the table
    .label x = 2
    .label i = $24
    // [29] call div32u16u
  // ampl is always positive so shifting left does not alter the sign
  // u[4.28] step = PI*2/wavelength
    // [61] phi from sin16s_gen2 to div32u16u [phi:sin16s_gen2->div32u16u]
  div32u16u_from_sin16s_gen2:
    jsr div32u16u
    // [30] div32u16u::return#0 = div32u16u::return#1
    jmp __b3
    // sin16s_gen2::@3
  __b3:
    // [31] sin16s_gen2::step#0 = div32u16u::return#0
    // [32] phi from sin16s_gen2::@3 to sin16s_gen2::@1 [phi:sin16s_gen2::@3->sin16s_gen2::@1]
  __b1_from___b3:
    // [32] phi sin16s_gen2::sintab#2 = xsin [phi:sin16s_gen2::@3->sin16s_gen2::@1#0] -- pwsz1=pwsc1 
    lda #<xsin
    sta.z sintab
    lda #>xsin
    sta.z sintab+1
    // [32] phi sin16s_gen2::x#2 = 0 [phi:sin16s_gen2::@3->sin16s_gen2::@1#1] -- vduz1=vduc1 
    lda #<0
    sta.z x
    lda #>0
    sta.z x+1
    lda #<0>>$10
    sta.z x+2
    lda #>0>>$10
    sta.z x+3
    // [32] phi sin16s_gen2::i#2 = 0 [phi:sin16s_gen2::@3->sin16s_gen2::@1#2] -- vwuz1=vwuc1 
    lda #<0
    sta.z i
    lda #>0
    sta.z i+1
    jmp __b1
  // u[4.28]
    // sin16s_gen2::@1
  __b1:
    // [33] if(sin16s_gen2::i#2<XSIN_SIZE) goto sin16s_gen2::@2 -- vwuz1_lt_vwuc1_then_la1 
    lda.z i+1
    cmp #>XSIN_SIZE
    bcc __b2
    bne !+
    lda.z i
    cmp #<XSIN_SIZE
    bcc __b2
  !:
    jmp __breturn
    // sin16s_gen2::@return
  __breturn:
    // [34] return 
    rts
    // sin16s_gen2::@2
  __b2:
    // [35] sin16s::x#0 = sin16s_gen2::x#2 -- vduz1=vduz2 
    lda.z x
    sta.z sin16s.x
    lda.z x+1
    sta.z sin16s.x+1
    lda.z x+2
    sta.z sin16s.x+2
    lda.z x+3
    sta.z sin16s.x+3
    // [36] call sin16s
    jsr sin16s
    // [37] sin16s::return#0 = sin16s::return#1
    jmp __b4
    // sin16s_gen2::@4
  __b4:
    // [38] mul16s::a#0 = sin16s::return#0
    // [39] call mul16s
    jsr mul16s
    // [40] mul16s::return#0 = mul16s::return#1
    jmp __b5
    // sin16s_gen2::@5
  __b5:
    // [41] sin16s_gen2::$6 = mul16s::return#0
    // [42] sin16s_gen2::$8 = word1  sin16s_gen2::$6 -- vwuz1=_word1_vdsz2 
    lda.z __6+2
    sta.z __8
    lda.z __6+3
    sta.z __8+1
    // [43] *sin16s_gen2::sintab#2 = (int)sin16s_gen2::$8 -- _deref_pwsz1=vwsz2 
    ldy #0
    lda.z __8
    sta (sintab),y
    iny
    lda.z __8+1
    sta (sintab),y
    // [44] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_INT -- pwsz1=pwsz1_plus_vbuc1 
    lda #SIZEOF_INT
    clc
    adc.z sintab
    sta.z sintab
    bcc !+
    inc.z sintab+1
  !:
    // [45] sin16s_gen2::x#1 = sin16s_gen2::x#2 + sin16s_gen2::step#0 -- vduz1=vduz1_plus_vduz2 
    clc
    lda.z x
    adc.z step
    sta.z x
    lda.z x+1
    adc.z step+1
    sta.z x+1
    lda.z x+2
    adc.z step+2
    sta.z x+2
    lda.z x+3
    adc.z step+3
    sta.z x+3
    // [46] sin16s_gen2::i#1 = ++ sin16s_gen2::i#2 -- vwuz1=_inc_vwuz1 
    inc.z i
    bne !+
    inc.z i+1
  !:
    // [32] phi from sin16s_gen2::@5 to sin16s_gen2::@1 [phi:sin16s_gen2::@5->sin16s_gen2::@1]
  __b1_from___b5:
    // [32] phi sin16s_gen2::sintab#2 = sin16s_gen2::sintab#0 [phi:sin16s_gen2::@5->sin16s_gen2::@1#0] -- register_copy 
    // [32] phi sin16s_gen2::x#2 = sin16s_gen2::x#1 [phi:sin16s_gen2::@5->sin16s_gen2::@1#1] -- register_copy 
    // [32] phi sin16s_gen2::i#2 = sin16s_gen2::i#1 [phi:sin16s_gen2::@5->sin16s_gen2::@1#2] -- register_copy 
    jmp __b1
}
  // loop
loop: {
    .label __2 = $1a
    .label __7 = $1a
    .label xpos = $1a
    // [48] phi from loop to loop::@1 [phi:loop->loop::@1]
  __b1_from_loop:
    // [48] phi xsin_idx#12 = 0 [phi:loop->loop::@1#0] -- vwuz1=vwuc1 
    lda #<0
    sta.z xsin_idx
    lda #>0
    sta.z xsin_idx+1
    jmp __b1
    // loop::@1
  __b1:
    jmp __b2
  // Wait for the raster to reach the bottom of the screen
    // loop::@2
  __b2:
    // [49] if(*((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER)!=$ff) goto loop::@2 -- _deref_pbuc1_neq_vbuc2_then_la1 
    lda #$ff
    cmp VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER
    bne __b2
    jmp __b3
    // loop::@3
  __b3:
    // [50] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = ++ *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) -- _deref_pbuc1=_inc__deref_pbuc1 
    inc VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR
    // [51] loop::$7 = xsin_idx#12 << 1 -- vwuz1=vwuz2_rol_1 
    lda.z xsin_idx
    asl
    sta.z __7
    lda.z xsin_idx+1
    rol
    sta.z __7+1
    // [52] loop::$2 = xsin + loop::$7 -- pwsz1=pwsc1_plus_vwuz1 
    lda.z __2
    clc
    adc #<xsin
    sta.z __2
    lda.z __2+1
    adc #>xsin
    sta.z __2+1
    // [53] loop::xpos#0 = *loop::$2 -- vwsz1=_deref_pwsz1 
    ldy #0
    lda (xpos),y
    pha
    iny
    lda (xpos),y
    sta.z xpos+1
    pla
    sta.z xpos
    // [54] render_logo::xpos#0 = loop::xpos#0
    // [55] call render_logo
    jsr render_logo
    jmp __b5
    // loop::@5
  __b5:
    // [56] xsin_idx#2 = ++ xsin_idx#12 -- vwuz1=_inc_vwuz1 
    inc.z xsin_idx
    bne !+
    inc.z xsin_idx+1
  !:
    // [57] if(xsin_idx#2!=XSIN_SIZE) goto loop::@6 -- vwuz1_neq_vwuc1_then_la1 
    lda.z xsin_idx+1
    cmp #>XSIN_SIZE
    bne __b6_from___b5
    lda.z xsin_idx
    cmp #<XSIN_SIZE
    bne __b6_from___b5
    // [59] phi from loop::@5 to loop::@4 [phi:loop::@5->loop::@4]
  __b4_from___b5:
    // [59] phi xsin_idx#21 = 0 [phi:loop::@5->loop::@4#0] -- vwuz1=vbuc1 
    lda #<0
    sta.z xsin_idx
    lda #>0
    sta.z xsin_idx+1
    jmp __b4
    // [58] phi from loop::@5 to loop::@6 [phi:loop::@5->loop::@6]
  __b6_from___b5:
    jmp __b6
    // loop::@6
  __b6:
    // [59] phi from loop::@6 to loop::@4 [phi:loop::@6->loop::@4]
  __b4_from___b6:
    // [59] phi xsin_idx#21 = xsin_idx#2 [phi:loop::@6->loop::@4#0] -- register_copy 
    jmp __b4
    // loop::@4
  __b4:
    // [60] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = -- *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) -- _deref_pbuc1=_dec__deref_pbuc1 
    dec VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR
    // [48] phi from loop::@4 to loop::@1 [phi:loop::@4->loop::@1]
  __b1_from___b4:
    // [48] phi xsin_idx#12 = xsin_idx#21 [phi:loop::@4->loop::@1#0] -- register_copy 
    jmp __b1
}
  // div32u16u
// Divide unsigned 32-bit unsigned long dividend with a 16-bit unsigned int divisor
// The 16-bit unsigned int remainder can be found in rem16u after the division
// __zp($16) unsigned long div32u16u(unsigned long dividend, unsigned int divisor)
div32u16u: {
    .label return = $16
    .label quotient_hi = $20
    .label quotient_lo = $14
    // [62] call divr16u
    // [180] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
  divr16u_from_div32u16u:
    // [180] phi divr16u::dividend#5 = word1 PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
    lda #<PI2_u4f28>>$10
    sta.z divr16u.dividend
    lda #>PI2_u4f28>>$10
    sta.z divr16u.dividend+1
    // [180] phi divr16u::rem#10 = 0 [phi:div32u16u->divr16u#1] -- vwuz1=vbuc1 
    lda #<0
    sta.z divr16u.rem
    lda #>0
    sta.z divr16u.rem+1
    jsr divr16u
    // [63] divr16u::return#2 = divr16u::return#0
    jmp __b1
    // div32u16u::@1
  __b1:
    // [64] div32u16u::quotient_hi#0 = divr16u::return#2 -- vwuz1=vwuz2 
    lda.z divr16u.return
    sta.z quotient_hi
    lda.z divr16u.return+1
    sta.z quotient_hi+1
    // [65] divr16u::rem#4 = rem16u#14
    // [66] call divr16u
    // [180] phi from div32u16u::@1 to divr16u [phi:div32u16u::@1->divr16u]
  divr16u_from___b1:
    // [180] phi divr16u::dividend#5 = word0 PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
    lda #<PI2_u4f28&$ffff
    sta.z divr16u.dividend
    lda #>PI2_u4f28&$ffff
    sta.z divr16u.dividend+1
    // [180] phi divr16u::rem#10 = divr16u::rem#4 [phi:div32u16u::@1->divr16u#1] -- register_copy 
    jsr divr16u
    // [67] divr16u::return#3 = divr16u::return#0
    jmp __b2
    // div32u16u::@2
  __b2:
    // [68] div32u16u::quotient_lo#0 = divr16u::return#3
    // [69] div32u16u::return#1 = div32u16u::quotient_hi#0 dw= div32u16u::quotient_lo#0 -- vduz1=vwuz2_dword_vwuz3 
    lda.z quotient_hi
    sta.z return+2
    lda.z quotient_hi+1
    sta.z return+3
    lda.z quotient_lo
    sta.z return
    lda.z quotient_lo+1
    sta.z return+1
    jmp __breturn
    // div32u16u::@return
  __breturn:
    // [70] return 
    rts
}
  // sin16s
// Calculate signed int sine sin(x)
// x: unsigned long input u[4.28] in the interval $00000000 - PI2_u4f28
// result: signed int sin(x) s[0.15] - using the full range  -$7fff - $7fff
// __zp($1a) int sin16s(__zp(8) unsigned long x)
sin16s: {
    .label __4 = $1c
    .label x = 8
    .label return = $1a
    .label x1 = $20
    .label x2 = $12
    .label x3 = $12
    .label x3_6 = $22
    .label usinx = $1a
    .label x4 = $12
    .label x5 = $22
    .label x5_128 = $22
    .label sinx = $1a
    // [71] if(sin16s::x#0<PI_u4f28) goto sin16s::@1 -- vduz1_lt_vduc1_then_la1 
    lda.z x+3
    cmp #>PI_u4f28>>$10
    bcc __b1_from_sin16s
    bne !+
    lda.z x+2
    cmp #<PI_u4f28>>$10
    bcc __b1_from_sin16s
    bne !+
    lda.z x+1
    cmp #>PI_u4f28
    bcc __b1_from_sin16s
    bne !+
    lda.z x
    cmp #<PI_u4f28
    bcc __b1_from_sin16s
  !:
    jmp __b4
    // sin16s::@4
  __b4:
    // [72] sin16s::x#1 = sin16s::x#0 - PI_u4f28 -- vduz1=vduz1_minus_vduc1 
    lda.z x
    sec
    sbc #<PI_u4f28
    sta.z x
    lda.z x+1
    sbc #>PI_u4f28
    sta.z x+1
    lda.z x+2
    sbc #<PI_u4f28>>$10
    sta.z x+2
    lda.z x+3
    sbc #>PI_u4f28>>$10
    sta.z x+3
    // [73] phi from sin16s::@4 to sin16s::@1 [phi:sin16s::@4->sin16s::@1]
  __b1_from___b4:
    // [73] phi sin16s::isUpper#2 = 1 [phi:sin16s::@4->sin16s::@1#0] -- vbuyy=vbuc1 
    ldy #1
    // [73] phi sin16s::x#4 = sin16s::x#1 [phi:sin16s::@4->sin16s::@1#1] -- register_copy 
    jmp __b1
    // [73] phi from sin16s to sin16s::@1 [phi:sin16s->sin16s::@1]
  __b1_from_sin16s:
    // [73] phi sin16s::isUpper#2 = 0 [phi:sin16s->sin16s::@1#0] -- vbuyy=vbuc1 
    ldy #0
    // [73] phi sin16s::x#4 = sin16s::x#0 [phi:sin16s->sin16s::@1#1] -- register_copy 
    jmp __b1
    // sin16s::@1
  __b1:
    // [74] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 -- vduz1_lt_vduc1_then_la1 
    lda.z x+3
    cmp #>PI_HALF_u4f28>>$10
    bcc __b2_from___b1
    bne !+
    lda.z x+2
    cmp #<PI_HALF_u4f28>>$10
    bcc __b2_from___b1
    bne !+
    lda.z x+1
    cmp #>PI_HALF_u4f28
    bcc __b2_from___b1
    bne !+
    lda.z x
    cmp #<PI_HALF_u4f28
    bcc __b2_from___b1
  !:
    jmp __b5
    // sin16s::@5
  __b5:
    // [75] sin16s::x#2 = PI_u4f28 - sin16s::x#4 -- vduz1=vduc1_minus_vduz1 
    lda #<PI_u4f28
    sec
    sbc.z x
    sta.z x
    lda #>PI_u4f28
    sbc.z x+1
    sta.z x+1
    lda #<PI_u4f28>>$10
    sbc.z x+2
    sta.z x+2
    lda #>PI_u4f28>>$10
    sbc.z x+3
    sta.z x+3
    // [76] phi from sin16s::@1 sin16s::@5 to sin16s::@2 [phi:sin16s::@1/sin16s::@5->sin16s::@2]
  __b2_from___b1:
  __b2_from___b5:
    // [76] phi sin16s::x#6 = sin16s::x#4 [phi:sin16s::@1/sin16s::@5->sin16s::@2#0] -- register_copy 
    jmp __b2
    // sin16s::@2
  __b2:
    // [77] sin16s::$4 = sin16s::x#6 << 3 -- vduz1=vduz2_rol_3 
    lda.z x
    asl
    sta.z __4
    lda.z x+1
    rol
    sta.z __4+1
    lda.z x+2
    rol
    sta.z __4+2
    lda.z x+3
    rol
    sta.z __4+3
    asl.z __4
    rol.z __4+1
    rol.z __4+2
    rol.z __4+3
    asl.z __4
    rol.z __4+1
    rol.z __4+2
    rol.z __4+3
    // [78] sin16s::x1#0 = word1  sin16s::$4 -- vwuz1=_word1_vduz2 
    // sinx = x - x^3/6 + x5/128;
    lda.z __4+2
    sta.z x1
    lda.z __4+3
    sta.z x1+1
    // [79] mulu16_sel::v1#0 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v1
    lda.z x1+1
    sta.z mulu16_sel.v1+1
    // [80] mulu16_sel::v2#0 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v2
    lda.z x1+1
    sta.z mulu16_sel.v2+1
    // [81] call mulu16_sel
  // u[1.15]
    // [198] phi from sin16s::@2 to mulu16_sel [phi:sin16s::@2->mulu16_sel]
  mulu16_sel_from___b2:
    // [198] phi mulu16_sel::select#5 = 0 [phi:sin16s::@2->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #0
    // [198] phi mulu16_sel::v2#5 = mulu16_sel::v2#0 [phi:sin16s::@2->mulu16_sel#1] -- register_copy 
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#0 [phi:sin16s::@2->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // [82] mulu16_sel::return#0 = mulu16_sel::return#12
    jmp __b7
    // sin16s::@7
  __b7:
    // [83] sin16s::x2#0 = mulu16_sel::return#0 -- vwuz1=vwuz2 
    lda.z mulu16_sel.return
    sta.z x2
    lda.z mulu16_sel.return+1
    sta.z x2+1
    // [84] mulu16_sel::v1#1 = sin16s::x2#0
    // [85] mulu16_sel::v2#1 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v2
    lda.z x1+1
    sta.z mulu16_sel.v2+1
    // [86] call mulu16_sel
  // u[2.14] x^2
    // [198] phi from sin16s::@7 to mulu16_sel [phi:sin16s::@7->mulu16_sel]
  mulu16_sel_from___b7:
    // [198] phi mulu16_sel::select#5 = 1 [phi:sin16s::@7->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #1
    // [198] phi mulu16_sel::v2#5 = mulu16_sel::v2#1 [phi:sin16s::@7->mulu16_sel#1] -- register_copy 
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#1 [phi:sin16s::@7->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // [87] mulu16_sel::return#1 = mulu16_sel::return#12 -- vwuz1=vwuz2 
    lda.z mulu16_sel.return
    sta.z mulu16_sel.return_1
    lda.z mulu16_sel.return+1
    sta.z mulu16_sel.return_1+1
    jmp __b8
    // sin16s::@8
  __b8:
    // [88] sin16s::x3#0 = mulu16_sel::return#1
    // [89] mulu16_sel::v1#2 = sin16s::x3#0
    // [90] call mulu16_sel
  // u[2.14] x^3
    // [198] phi from sin16s::@8 to mulu16_sel [phi:sin16s::@8->mulu16_sel]
  mulu16_sel_from___b8:
    // [198] phi mulu16_sel::select#5 = 1 [phi:sin16s::@8->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #1
    // [198] phi mulu16_sel::v2#5 = (unsigned int)$10000/6 [phi:sin16s::@8->mulu16_sel#1] -- vwuz1=vwuc1 
    lda #<$10000/6
    sta.z mulu16_sel.v2
    lda #>$10000/6
    sta.z mulu16_sel.v2+1
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#2 [phi:sin16s::@8->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // [91] mulu16_sel::return#2 = mulu16_sel::return#12
    jmp __b9
    // sin16s::@9
  __b9:
    // [92] sin16s::x3_6#0 = mulu16_sel::return#2
    // [93] sin16s::usinx#0 = sin16s::x1#0 - sin16s::x3_6#0 -- vwuz1=vwuz2_minus_vwuz3 
    // u[1.15] x^3/6;
    lda.z x1
    sec
    sbc.z x3_6
    sta.z usinx
    lda.z x1+1
    sbc.z x3_6+1
    sta.z usinx+1
    // [94] mulu16_sel::v1#3 = sin16s::x3#0
    // [95] mulu16_sel::v2#3 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v2
    lda.z x1+1
    sta.z mulu16_sel.v2+1
    // [96] call mulu16_sel
  // u[1.15] x - x^3/6
    // [198] phi from sin16s::@9 to mulu16_sel [phi:sin16s::@9->mulu16_sel]
  mulu16_sel_from___b9:
    // [198] phi mulu16_sel::select#5 = 0 [phi:sin16s::@9->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #0
    // [198] phi mulu16_sel::v2#5 = mulu16_sel::v2#3 [phi:sin16s::@9->mulu16_sel#1] -- register_copy 
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#3 [phi:sin16s::@9->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // [97] mulu16_sel::return#10 = mulu16_sel::return#12 -- vwuz1=vwuz2 
    lda.z mulu16_sel.return
    sta.z mulu16_sel.return_1
    lda.z mulu16_sel.return+1
    sta.z mulu16_sel.return_1+1
    jmp __b10
    // sin16s::@10
  __b10:
    // [98] sin16s::x4#0 = mulu16_sel::return#10
    // [99] mulu16_sel::v1#4 = sin16s::x4#0
    // [100] mulu16_sel::v2#4 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v2
    lda.z x1+1
    sta.z mulu16_sel.v2+1
    // [101] call mulu16_sel
  // u[3.13] x^4
    // [198] phi from sin16s::@10 to mulu16_sel [phi:sin16s::@10->mulu16_sel]
  mulu16_sel_from___b10:
    // [198] phi mulu16_sel::select#5 = 0 [phi:sin16s::@10->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #0
    // [198] phi mulu16_sel::v2#5 = mulu16_sel::v2#4 [phi:sin16s::@10->mulu16_sel#1] -- register_copy 
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#4 [phi:sin16s::@10->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // [102] mulu16_sel::return#11 = mulu16_sel::return#12
    jmp __b11
    // sin16s::@11
  __b11:
    // [103] sin16s::x5#0 = mulu16_sel::return#11
    // [104] sin16s::x5_128#0 = sin16s::x5#0 >> 4 -- vwuz1=vwuz1_ror_4 
    // u[4.12] x^5
    lsr.z x5_128+1
    ror.z x5_128
    lsr.z x5_128+1
    ror.z x5_128
    lsr.z x5_128+1
    ror.z x5_128
    lsr.z x5_128+1
    ror.z x5_128
    // [105] sin16s::usinx#1 = sin16s::usinx#0 + sin16s::x5_128#0 -- vwuz1=vwuz1_plus_vwuz2 
    clc
    lda.z usinx
    adc.z x5_128
    sta.z usinx
    lda.z usinx+1
    adc.z x5_128+1
    sta.z usinx+1
    // [106] if(sin16s::isUpper#2==0) goto sin16s::@12 -- vbuyy_eq_0_then_la1 
    cpy #0
    beq __b12
    jmp __b6
    // sin16s::@6
  __b6:
    // [107] sin16s::sinx#1 = - (int)sin16s::usinx#1 -- vwsz1=_neg_vwsz1 
    lda #0
    sec
    sbc.z sinx
    sta.z sinx
    lda #0
    sbc.z sinx+1
    sta.z sinx+1
    // [108] phi from sin16s::@12 sin16s::@6 to sin16s::@3 [phi:sin16s::@12/sin16s::@6->sin16s::@3]
  __b3_from___b12:
  __b3_from___b6:
    // [108] phi sin16s::return#1 = sin16s::return#5 [phi:sin16s::@12/sin16s::@6->sin16s::@3#0] -- register_copy 
    jmp __b3
    // sin16s::@3
  __b3:
    jmp __breturn
    // sin16s::@return
  __breturn:
    // [109] return 
    rts
    // sin16s::@12
  __b12:
    // [110] sin16s::return#5 = (int)sin16s::usinx#1
    jmp __b3_from___b12
}
  // mul16s
// Multiply of two signed ints to a signed long
// Fixes offsets introduced by using unsigned multiplication
// __zp($c) long mul16s(__zp($1a) int a, int b)
mul16s: {
    .label __6 = $22
    .label __11 = $22
    .label a = $1a
    .label return = $c
    .label m = $c
    // [111] mul16u::a#2 = (unsigned int)mul16s::a#0 -- vwuz1=vwuz2 
    lda.z a
    sta.z mul16u.a
    lda.z a+1
    sta.z mul16u.a+1
    // [112] call mul16u
    // [207] phi from mul16s to mul16u [phi:mul16s->mul16u]
  mul16u_from_mul16s:
    // [207] phi mul16u::a#6 = mul16u::a#2 [phi:mul16s->mul16u#0] -- register_copy 
    // [207] phi mul16u::b#2 = (unsigned int)sin16s_gen2::ampl#0 [phi:mul16s->mul16u#1] -- vwuz1=vwuc1 
    lda #<sin16s_gen2.ampl
    sta.z mul16u.b
    lda #>sin16s_gen2.ampl
    sta.z mul16u.b+1
    jsr mul16u
    // [113] mul16u::return#3 = mul16u::res#2
    jmp __b4
    // mul16s::@4
  __b4:
    // [114] mul16s::m#0 = mul16u::return#3
    // [115] if(mul16s::a#0>=0) goto mul16s::@1 -- vwsz1_ge_0_then_la1 
    lda.z a+1
    bpl __b1_from___b4
    jmp __b3
    // mul16s::@3
  __b3:
    // [116] mul16s::$6 = word1  mul16s::m#0 -- vwuz1=_word1_vduz2 
    lda.z m+2
    sta.z __6
    lda.z m+3
    sta.z __6+1
    // [117] mul16s::$11 = mul16s::$6 - (unsigned int)sin16s_gen2::ampl#0 -- vwuz1=vwuz1_minus_vwuc1 
    lda.z __11
    sec
    sbc #<sin16s_gen2.ampl
    sta.z __11
    lda.z __11+1
    sbc #>sin16s_gen2.ampl
    sta.z __11+1
    // [118] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11 -- vduz1=vduz1_setword1_vwuz2 
    lda.z __11
    sta.z m+2
    lda.z __11+1
    sta.z m+3
    // [119] phi from mul16s::@3 mul16s::@4 to mul16s::@1 [phi:mul16s::@3/mul16s::@4->mul16s::@1]
  __b1_from___b3:
  __b1_from___b4:
    // [119] phi mul16s::m#4 = mul16s::m#1 [phi:mul16s::@3/mul16s::@4->mul16s::@1#0] -- register_copy 
    jmp __b1
    // mul16s::@1
  __b1:
    jmp __b2
    // mul16s::@2
  __b2:
    // [120] mul16s::return#1 = (long)mul16s::m#4
    jmp __breturn
    // mul16s::@return
  __breturn:
    // [121] return 
    rts
}
  // render_logo
// void render_logo(__zp($1a) int xpos)
render_logo: {
    .label __2 = $24
    .label xpos = $1a
    .label x_char = $26
    .label logo_idx = $10
    .label logo_idx_1 = $11
    // [122] render_logo::$25 = (char)render_logo::xpos#0 -- vbuaa=_byte_vwsz1 
    lda.z xpos
    // [123] render_logo::$0 = render_logo::$25 & 7 -- vbuaa=vbuaa_band_vbuc1 
    and #7
    // [124] render_logo::$1 = VICII_MCM | render_logo::$0 -- vbuaa=vbuc1_bor_vbuaa 
    ora #VICII_MCM
    // [125] *D016 = render_logo::$1 -- _deref_pbuc1=vbuaa 
    sta D016
    // [126] render_logo::$2 = render_logo::xpos#0 >> 3 -- vwsz1=vwsz2_ror_3 
    lda.z xpos+1
    cmp #$80
    ror
    sta.z __2+1
    lda.z xpos
    ror
    sta.z __2
    lda.z __2+1
    cmp #$80
    ror.z __2+1
    ror.z __2
    lda.z __2+1
    cmp #$80
    ror.z __2+1
    ror.z __2
    // [127] render_logo::x_char#0 = (signed char)render_logo::$2 -- vbsz1=_sbyte_vwsz2 
    lda.z __2
    sta.z x_char
    // [128] if(render_logo::xpos#0<0) goto render_logo::@1 -- vwsz1_lt_0_then_la1 
    lda.z xpos+1
    bmi __b1
    // [129] phi from render_logo to render_logo::@2 [phi:render_logo->render_logo::@2]
  __b2_from_render_logo:
    // [129] phi render_logo::screen_idx#18 = 0 [phi:render_logo->render_logo::@2#0] -- vbuyy=vbuc1 
    ldy #0
    jmp __b2
    // render_logo::@2
  __b2:
    // [130] if(render_logo::screen_idx#18!=(char)render_logo::x_char#0) goto render_logo::@3 -- vbuyy_neq_vbuz1_then_la1 
    cpy.z x_char
    bne __b3
    // [131] phi from render_logo::@2 to render_logo::@5 [phi:render_logo::@2->render_logo::@5]
  __b5_from___b2:
    // [131] phi render_logo::logo_idx#10 = 0 [phi:render_logo::@2->render_logo::@5#0] -- vbuz1=vbuc1 
    lda #0
    sta.z logo_idx
    // [131] phi render_logo::screen_idx#10 = render_logo::screen_idx#18 [phi:render_logo::@2->render_logo::@5#1] -- register_copy 
    jmp __b5
    // render_logo::@5
  __b5:
    // [132] if(render_logo::screen_idx#10!=$28) goto render_logo::@6 -- vbuyy_neq_vbuc1_then_la1 
    cpy #$28
    bne __b6
    jmp __breturn
    // render_logo::@return
  __breturn:
    // [133] return 
    rts
    // render_logo::@6
  __b6:
    // [134] SCREEN[render_logo::screen_idx#10] = render_logo::logo_idx#10 -- pbuc1_derefidx_vbuyy=vbuz1 
    lda.z logo_idx
    sta SCREEN,y
    jmp __b10_1
    // render_logo::@10_1
  __b10_1:
    // [135] render_logo::$30 = render_logo::logo_idx#10 + $28*1 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*1
    clc
    adc.z logo_idx
    // [136] (SCREEN+$28*1)[render_logo::screen_idx#10] = render_logo::$30 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*1,y
    jmp __b10_2
    // render_logo::@10_2
  __b10_2:
    // [137] render_logo::$33 = render_logo::logo_idx#10 + $28*2 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*2
    clc
    adc.z logo_idx
    // [138] (SCREEN+$28*2)[render_logo::screen_idx#10] = render_logo::$33 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*2,y
    jmp __b10_3
    // render_logo::@10_3
  __b10_3:
    // [139] render_logo::$36 = render_logo::logo_idx#10 + $28*3 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*3
    clc
    adc.z logo_idx
    // [140] (SCREEN+$28*3)[render_logo::screen_idx#10] = render_logo::$36 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*3,y
    jmp __b10_4
    // render_logo::@10_4
  __b10_4:
    // [141] render_logo::$39 = render_logo::logo_idx#10 + $28*4 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*4
    clc
    adc.z logo_idx
    // [142] (SCREEN+$28*4)[render_logo::screen_idx#10] = render_logo::$39 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*4,y
    jmp __b10_5
    // render_logo::@10_5
  __b10_5:
    // [143] render_logo::$42 = render_logo::logo_idx#10 + $28*5 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*5
    clc
    adc.z logo_idx
    // [144] (SCREEN+$28*5)[render_logo::screen_idx#10] = render_logo::$42 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*5,y
    jmp __b7
    // render_logo::@7
  __b7:
    // [145] render_logo::screen_idx#4 = ++ render_logo::screen_idx#10 -- vbuyy=_inc_vbuyy 
    iny
    // [146] render_logo::logo_idx#3 = ++ render_logo::logo_idx#10 -- vbuz1=_inc_vbuz1 
    inc.z logo_idx
    // [131] phi from render_logo::@7 to render_logo::@5 [phi:render_logo::@7->render_logo::@5]
  __b5_from___b7:
    // [131] phi render_logo::logo_idx#10 = render_logo::logo_idx#3 [phi:render_logo::@7->render_logo::@5#0] -- register_copy 
    // [131] phi render_logo::screen_idx#10 = render_logo::screen_idx#4 [phi:render_logo::@7->render_logo::@5#1] -- register_copy 
    jmp __b5
    // render_logo::@3
  __b3:
    // [147] SCREEN[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN,y
    jmp __b6_1
    // render_logo::@6_1
  __b6_1:
    // [148] (SCREEN+$28*1)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*1,y
    jmp __b6_2
    // render_logo::@6_2
  __b6_2:
    // [149] (SCREEN+$28*2)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*2,y
    jmp __b6_3
    // render_logo::@6_3
  __b6_3:
    // [150] (SCREEN+$28*3)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*3,y
    jmp __b6_4
    // render_logo::@6_4
  __b6_4:
    // [151] (SCREEN+$28*4)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*4,y
    jmp __b6_5
    // render_logo::@6_5
  __b6_5:
    // [152] (SCREEN+$28*5)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*5,y
    jmp __b4
    // render_logo::@4
  __b4:
    // [153] render_logo::screen_idx#3 = ++ render_logo::screen_idx#18 -- vbuyy=_inc_vbuyy 
    iny
    // [129] phi from render_logo::@4 to render_logo::@2 [phi:render_logo::@4->render_logo::@2]
  __b2_from___b4:
    // [129] phi render_logo::screen_idx#18 = render_logo::screen_idx#3 [phi:render_logo::@4->render_logo::@2#0] -- register_copy 
    jmp __b2
    // render_logo::@1
  __b1:
    // [154] render_logo::logo_idx#1 = - render_logo::x_char#0 -- vbsaa=_neg_vbsz1 
    lda.z x_char
    eor #$ff
    clc
    adc #1
    // [155] render_logo::logo_idx#14 = (char)render_logo::logo_idx#1 -- vbuz1=vbuaa 
    sta.z logo_idx_1
    // [156] phi from render_logo::@1 to render_logo::@8 [phi:render_logo::@1->render_logo::@8]
  __b8_from___b1:
    // [156] phi render_logo::screen_idx#21 = 0 [phi:render_logo::@1->render_logo::@8#0] -- vbuyy=vbuc1 
    ldy #0
    // [156] phi render_logo::logo_idx#11 = render_logo::logo_idx#14 [phi:render_logo::@1->render_logo::@8#1] -- register_copy 
    jmp __b8
    // render_logo::@8
  __b8:
    // [157] if(render_logo::logo_idx#11!=$28) goto render_logo::@9 -- vbuz1_neq_vbuc1_then_la1 
    lda #$28
    cmp.z logo_idx_1
    bne __b9
    // [158] phi from render_logo::@13 render_logo::@8 to render_logo::@11 [phi:render_logo::@13/render_logo::@8->render_logo::@11]
  __b11_from___b13:
  __b11_from___b8:
    // [158] phi render_logo::screen_idx#15 = render_logo::screen_idx#6 [phi:render_logo::@13/render_logo::@8->render_logo::@11#0] -- register_copy 
    jmp __b11
    // render_logo::@11
  __b11:
    // [159] if(render_logo::screen_idx#15!=$28) goto render_logo::@12 -- vbuyy_neq_vbuc1_then_la1 
    cpy #$28
    bne __b12
    jmp __breturn
    // render_logo::@12
  __b12:
    // [160] SCREEN[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN,y
    jmp __b18_1
    // render_logo::@18_1
  __b18_1:
    // [161] (SCREEN+$28*1)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*1,y
    jmp __b18_2
    // render_logo::@18_2
  __b18_2:
    // [162] (SCREEN+$28*2)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*2,y
    jmp __b18_3
    // render_logo::@18_3
  __b18_3:
    // [163] (SCREEN+$28*3)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*3,y
    jmp __b18_4
    // render_logo::@18_4
  __b18_4:
    // [164] (SCREEN+$28*4)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*4,y
    jmp __b18_5
    // render_logo::@18_5
  __b18_5:
    // [165] (SCREEN+$28*5)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN+$28*5,y
    jmp __b13
    // render_logo::@13
  __b13:
    // [166] render_logo::screen_idx#6 = ++ render_logo::screen_idx#15 -- vbuyy=_inc_vbuyy 
    iny
    jmp __b11_from___b13
    // render_logo::@9
  __b9:
    // [167] SCREEN[render_logo::screen_idx#21] = render_logo::logo_idx#11 -- pbuc1_derefidx_vbuyy=vbuz1 
    lda.z logo_idx_1
    sta SCREEN,y
    jmp __b14_1
    // render_logo::@14_1
  __b14_1:
    // [168] render_logo::$70 = render_logo::logo_idx#11 + $28*1 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*1
    clc
    adc.z logo_idx_1
    // [169] (SCREEN+$28*1)[render_logo::screen_idx#21] = render_logo::$70 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*1,y
    jmp __b14_2
    // render_logo::@14_2
  __b14_2:
    // [170] render_logo::$73 = render_logo::logo_idx#11 + $28*2 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*2
    clc
    adc.z logo_idx_1
    // [171] (SCREEN+$28*2)[render_logo::screen_idx#21] = render_logo::$73 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*2,y
    jmp __b14_3
    // render_logo::@14_3
  __b14_3:
    // [172] render_logo::$76 = render_logo::logo_idx#11 + $28*3 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*3
    clc
    adc.z logo_idx_1
    // [173] (SCREEN+$28*3)[render_logo::screen_idx#21] = render_logo::$76 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*3,y
    jmp __b14_4
    // render_logo::@14_4
  __b14_4:
    // [174] render_logo::$79 = render_logo::logo_idx#11 + $28*4 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*4
    clc
    adc.z logo_idx_1
    // [175] (SCREEN+$28*4)[render_logo::screen_idx#21] = render_logo::$79 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*4,y
    jmp __b14_5
    // render_logo::@14_5
  __b14_5:
    // [176] render_logo::$82 = render_logo::logo_idx#11 + $28*5 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*5
    clc
    adc.z logo_idx_1
    // [177] (SCREEN+$28*5)[render_logo::screen_idx#21] = render_logo::$82 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*5,y
    jmp __b10
    // render_logo::@10
  __b10:
    // [178] render_logo::screen_idx#5 = ++ render_logo::screen_idx#21 -- vbuyy=_inc_vbuyy 
    iny
    // [179] render_logo::logo_idx#4 = ++ render_logo::logo_idx#11 -- vbuz1=_inc_vbuz1 
    inc.z logo_idx_1
    // [156] phi from render_logo::@10 to render_logo::@8 [phi:render_logo::@10->render_logo::@8]
  __b8_from___b10:
    // [156] phi render_logo::screen_idx#21 = render_logo::screen_idx#5 [phi:render_logo::@10->render_logo::@8#0] -- register_copy 
    // [156] phi render_logo::logo_idx#11 = render_logo::logo_idx#4 [phi:render_logo::@10->render_logo::@8#1] -- register_copy 
    jmp __b8
}
  // divr16u
// Performs division on two 16 bit unsigned ints and an initial remainder
// Returns the quotient dividend/divisor.
// The final remainder will be set into the global variable rem16u
// Implemented using simple binary division
// __zp($14) unsigned int divr16u(__zp($12) unsigned int dividend, unsigned int divisor, __zp($1a) unsigned int rem)
divr16u: {
    .label rem = $1a
    .label dividend = $12
    .label quotient = $14
    .label return = $14
    // [181] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
  __b1_from_divr16u:
    // [181] phi divr16u::i#2 = 0 [phi:divr16u->divr16u::@1#0] -- vbuxx=vbuc1 
    ldx #0
    // [181] phi divr16u::quotient#3 = 0 [phi:divr16u->divr16u::@1#1] -- vwuz1=vwuc1 
    lda #<0
    sta.z quotient
    lda #>0
    sta.z quotient+1
    // [181] phi divr16u::dividend#3 = divr16u::dividend#5 [phi:divr16u->divr16u::@1#2] -- register_copy 
    // [181] phi divr16u::rem#5 = divr16u::rem#10 [phi:divr16u->divr16u::@1#3] -- register_copy 
    jmp __b1
    // [181] phi from divr16u::@3 to divr16u::@1 [phi:divr16u::@3->divr16u::@1]
  __b1_from___b3:
    // [181] phi divr16u::i#2 = divr16u::i#1 [phi:divr16u::@3->divr16u::@1#0] -- register_copy 
    // [181] phi divr16u::quotient#3 = divr16u::return#0 [phi:divr16u::@3->divr16u::@1#1] -- register_copy 
    // [181] phi divr16u::dividend#3 = divr16u::dividend#0 [phi:divr16u::@3->divr16u::@1#2] -- register_copy 
    // [181] phi divr16u::rem#5 = divr16u::rem#11 [phi:divr16u::@3->divr16u::@1#3] -- register_copy 
    jmp __b1
    // divr16u::@1
  __b1:
    // [182] divr16u::rem#0 = divr16u::rem#5 << 1 -- vwuz1=vwuz1_rol_1 
    asl.z rem
    rol.z rem+1
    // [183] divr16u::$1 = byte1  divr16u::dividend#3 -- vbuaa=_byte1_vwuz1 
    lda.z dividend+1
    // [184] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
    and #$80
    // [185] if(divr16u::$2==0) goto divr16u::@2 -- vbuaa_eq_0_then_la1 
    cmp #0
    beq __b2_from___b1
    jmp __b4
    // divr16u::@4
  __b4:
    // [186] divr16u::rem#1 = divr16u::rem#0 | 1 -- vwuz1=vwuz1_bor_vbuc1 
    lda #1
    ora.z rem
    sta.z rem
    // [187] phi from divr16u::@1 divr16u::@4 to divr16u::@2 [phi:divr16u::@1/divr16u::@4->divr16u::@2]
  __b2_from___b1:
  __b2_from___b4:
    // [187] phi divr16u::rem#6 = divr16u::rem#0 [phi:divr16u::@1/divr16u::@4->divr16u::@2#0] -- register_copy 
    jmp __b2
    // divr16u::@2
  __b2:
    // [188] divr16u::dividend#0 = divr16u::dividend#3 << 1 -- vwuz1=vwuz1_rol_1 
    asl.z dividend
    rol.z dividend+1
    // [189] divr16u::quotient#1 = divr16u::quotient#3 << 1 -- vwuz1=vwuz1_rol_1 
    asl.z quotient
    rol.z quotient+1
    // [190] if(divr16u::rem#6<XSIN_SIZE) goto divr16u::@3 -- vwuz1_lt_vwuc1_then_la1 
    lda.z rem+1
    cmp #>XSIN_SIZE
    bcc __b3_from___b2
    bne !+
    lda.z rem
    cmp #<XSIN_SIZE
    bcc __b3_from___b2
  !:
    jmp __b5
    // divr16u::@5
  __b5:
    // [191] divr16u::quotient#2 = ++ divr16u::quotient#1 -- vwuz1=_inc_vwuz1 
    inc.z quotient
    bne !+
    inc.z quotient+1
  !:
    // [192] divr16u::rem#2 = divr16u::rem#6 - XSIN_SIZE -- vwuz1=vwuz1_minus_vwuc1 
    lda.z rem
    sec
    sbc #<XSIN_SIZE
    sta.z rem
    lda.z rem+1
    sbc #>XSIN_SIZE
    sta.z rem+1
    // [193] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
  __b3_from___b2:
  __b3_from___b5:
    // [193] phi divr16u::return#0 = divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy 
    // [193] phi divr16u::rem#11 = divr16u::rem#6 [phi:divr16u::@2/divr16u::@5->divr16u::@3#1] -- register_copy 
    jmp __b3
    // divr16u::@3
  __b3:
    // [194] divr16u::i#1 = ++ divr16u::i#2 -- vbuxx=_inc_vbuxx 
    inx
    // [195] if(divr16u::i#1!=$10) goto divr16u::@1 -- vbuxx_neq_vbuc1_then_la1 
    cpx #$10
    bne __b1_from___b3
    jmp __b6
    // divr16u::@6
  __b6:
    // [196] rem16u#14 = divr16u::rem#11
    jmp __breturn
    // divr16u::@return
  __breturn:
    // [197] return 
    rts
}
  // mulu16_sel
// Calculate val*val for two unsigned int values - the result is 16 selected bits of the 32-bit result.
// The select parameter indicates how many of the highest bits of the 32-bit result to skip
// __zp($22) unsigned int mulu16_sel(__zp($12) unsigned int v1, __zp($14) unsigned int v2, __register(X) char select)
mulu16_sel: {
    .label __0 = $c
    .label __1 = $c
    .label v1 = $12
    .label v2 = $14
    .label return = $22
    .label return_1 = $12
    // [199] mul16u::a#0 = mulu16_sel::v1#5 -- vwuz1=vwuz2 
    lda.z v1
    sta.z mul16u.a
    lda.z v1+1
    sta.z mul16u.a+1
    // [200] mul16u::b#0 = mulu16_sel::v2#5
    // [201] call mul16u
    // [207] phi from mulu16_sel to mul16u [phi:mulu16_sel->mul16u]
  mul16u_from_mulu16_sel:
    // [207] phi mul16u::a#6 = mul16u::a#0 [phi:mulu16_sel->mul16u#0] -- register_copy 
    // [207] phi mul16u::b#2 = mul16u::b#0 [phi:mulu16_sel->mul16u#1] -- register_copy 
    jsr mul16u
    // [202] mul16u::return#0 = mul16u::res#2
    jmp __b1
    // mulu16_sel::@1
  __b1:
    // [203] mulu16_sel::$0 = mul16u::return#0
    // [204] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 -- vduz1=vduz1_rol_vbuxx 
    cpx #0
    beq !e+
  !:
    asl.z __1
    rol.z __1+1
    rol.z __1+2
    rol.z __1+3
    dex
    bne !-
  !e:
    // [205] mulu16_sel::return#12 = word1  mulu16_sel::$1 -- vwuz1=_word1_vduz2 
    lda.z __1+2
    sta.z return
    lda.z __1+3
    sta.z return+1
    jmp __breturn
    // mulu16_sel::@return
  __breturn:
    // [206] return 
    rts
}
  // mul16u
// Perform binary multiplication of two unsigned 16-bit unsigned ints into a 32-bit unsigned long
// __zp($c) unsigned long mul16u(__zp($22) unsigned int a, __zp($14) unsigned int b)
mul16u: {
    .label a = $22
    .label b = $14
    .label return = $c
    .label mb = $1c
    .label res = $c
    // [208] mul16u::mb#0 = (unsigned long)mul16u::b#2 -- vduz1=_dword_vwuz2 
    lda.z b
    sta.z mb
    lda.z b+1
    sta.z mb+1
    lda #0
    sta.z mb+2
    sta.z mb+3
    // [209] phi from mul16u to mul16u::@1 [phi:mul16u->mul16u::@1]
  __b1_from_mul16u:
    // [209] phi mul16u::mb#2 = mul16u::mb#0 [phi:mul16u->mul16u::@1#0] -- register_copy 
    // [209] phi mul16u::res#2 = 0 [phi:mul16u->mul16u::@1#1] -- vduz1=vduc1 
    lda #<0
    sta.z res
    lda #>0
    sta.z res+1
    lda #<0>>$10
    sta.z res+2
    lda #>0>>$10
    sta.z res+3
    // [209] phi mul16u::a#3 = mul16u::a#6 [phi:mul16u->mul16u::@1#2] -- register_copy 
    jmp __b1
    // mul16u::@1
  __b1:
    // [210] if(mul16u::a#3!=0) goto mul16u::@2 -- vwuz1_neq_0_then_la1 
    lda.z a
    ora.z a+1
    bne __b2
    jmp __breturn
    // mul16u::@return
  __breturn:
    // [211] return 
    rts
    // mul16u::@2
  __b2:
    // [212] mul16u::$1 = mul16u::a#3 & 1 -- vbuaa=vwuz1_band_vbuc1 
    lda #1
    and.z a
    // [213] if(mul16u::$1==0) goto mul16u::@3 -- vbuaa_eq_0_then_la1 
    cmp #0
    beq __b3_from___b2
    jmp __b4
    // mul16u::@4
  __b4:
    // [214] mul16u::res#1 = mul16u::res#2 + mul16u::mb#2 -- vduz1=vduz1_plus_vduz2 
    clc
    lda.z res
    adc.z mb
    sta.z res
    lda.z res+1
    adc.z mb+1
    sta.z res+1
    lda.z res+2
    adc.z mb+2
    sta.z res+2
    lda.z res+3
    adc.z mb+3
    sta.z res+3
    // [215] phi from mul16u::@2 mul16u::@4 to mul16u::@3 [phi:mul16u::@2/mul16u::@4->mul16u::@3]
  __b3_from___b2:
  __b3_from___b4:
    // [215] phi mul16u::res#6 = mul16u::res#2 [phi:mul16u::@2/mul16u::@4->mul16u::@3#0] -- register_copy 
    jmp __b3
    // mul16u::@3
  __b3:
    // [216] mul16u::a#1 = mul16u::a#3 >> 1 -- vwuz1=vwuz1_ror_1 
    lsr.z a+1
    ror.z a
    // [217] mul16u::mb#1 = mul16u::mb#2 << 1 -- vduz1=vduz1_rol_1 
    asl.z mb
    rol.z mb+1
    rol.z mb+2
    rol.z mb+3
    // [209] phi from mul16u::@3 to mul16u::@1 [phi:mul16u::@3->mul16u::@1]
  __b1_from___b3:
    // [209] phi mul16u::mb#2 = mul16u::mb#1 [phi:mul16u::@3->mul16u::@1#0] -- register_copy 
    // [209] phi mul16u::res#2 = mul16u::res#6 [phi:mul16u::@3->mul16u::@1#1] -- register_copy 
    // [209] phi mul16u::a#3 = mul16u::a#1 [phi:mul16u::@3->mul16u::@1#2] -- register_copy 
    jmp __b1
}
  // File Data
.segment Data
  .align $100
  xsin: .fill 2*XSIN_SIZE, 0
.pc = $2000 "LOGO"
LOGO:
.var logoPic = LoadPicture("logo.png", List().add($444444, $808080, $000000, $ffffff))
    .for (var y=0; y<6	; y++)
        .for (var x=0;x<40; x++)
            .for(var cp=0; cp<8; cp++)
                .byte logoPic.getMulticolorByte(x,cp+y*8)


ASSEMBLER OPTIMIZATIONS
Removing instruction jmp toD0181
Removing instruction jmp __b3
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Removing instruction jmp __breturn
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Succesful ASM optimization Pass5NextJumpElimination
Removing instruction lda VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1
Removing instruction lda #>0
Removing instruction lda #>0
Removing instruction lda #>0
Removing instruction lda #>0
Removing instruction lda #>0
Replacing instruction lda #<0 with TXA
Removing instruction lda #>0
Removing instruction lda #>0
Succesful ASM optimization Pass5UnnecesaryLoadElimination
Replacing label __b1_from___b1 with __b1
Replacing label __b2_from___b3 with __b2
Replacing label __b6_from___b5 with __b4
Replacing label __b6_from___b5 with __b4
Replacing label __b2_from___b1 with __b2
Replacing label __b2_from___b1 with __b2
Replacing label __b2_from___b1 with __b2
Replacing label __b2_from___b1 with __b2
Replacing label __b3_from___b12 with __b3
Replacing label __b1_from___b4 with __b2
Replacing label __b11_from___b13 with __b11
Replacing label __b2_from___b1 with __b2
Replacing label __b3_from___b2 with __b3
Replacing label __b3_from___b2 with __b3
Replacing label __b1_from___b3 with __b1
Replacing label __b3_from___b2 with __b3
Removing instruction toD0181_from_main:
Removing instruction toD0181:
Removing instruction __b4_from___b3:
Removing instruction memset_from___b4:
Removing instruction __b1_from___b1:
Removing instruction __b2_from___b1:
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Removing instruction loop_from___b5:
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Succesful ASM optimization Pass5RedundantLabelElimination
Removing instruction __b3:
Removing instruction memset_from___b3:
Removing instruction __b4:
Removing instruction __b1_from___b4:
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Removing instruction __breturn:
Removing instruction div32u16u_from_sin16s_gen2:
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Removing instruction divr16u_from_div32u16u:
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Removing instruction __b7:
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Removing instruction __b8:
Removing instruction mulu16_sel_from___b8:
Removing instruction __b9:
Removing instruction mulu16_sel_from___b9:
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Removing instruction mulu16_sel_from___b10:
Removing instruction __b11:
Removing instruction __b6:
Removing instruction mul16u_from_mul16s:
Removing instruction __b4:
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Removing instruction __b2_from_render_logo:
Removing instruction __b5_from___b2:
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Removing instruction __b10:
Removing instruction __b8_from___b10:
Removing instruction __b1_from_divr16u:
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Removing instruction mul16u_from_mulu16_sel:
Removing instruction __b1:
Removing instruction __breturn:
Removing instruction __b1_from_mul16u:
Removing instruction __breturn:
Removing instruction __b4:
Removing instruction __b1_from___b3:
Succesful ASM optimization Pass5UnusedLabelElimination
Skipping double jump to __b3 in beq __b12
Replacing jump to rts with rts in jmp __b3
Replacing jump to rts with rts in jmp __breturn
Succesful ASM optimization Pass5DoubleJumpElimination
Relabelling long label __b1_from_sin16s to __b4
Succesful ASM optimization Pass5RelabelLongLabels
Removing instruction jmp __b1
Removing instruction jmp __b4
Removing instruction jmp __b1
Succesful ASM optimization Pass5NextJumpElimination
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #0
Removing instruction lda #<0
Succesful ASM optimization Pass5UnnecesaryLoadElimination
Removing instruction __b12:
Removing instruction __breturn:
Succesful ASM optimization Pass5UnusedLabelElimination
Removing unreachable instruction rts
Succesful ASM optimization Pass5UnreachableCodeElimination

FINAL SYMBOL TABLE
__constant const char BLACK = 0
__constant char * const COLS = (char *) 55296
__constant char * const D016 = (char *) 53270
__constant char * const D018 = (char *) 53272
__constant const char DARK_GREY = $b
__constant char LOGO[6*$28*8] = kickasm {{ .var logoPic = LoadPicture("logo.png", List().add($444444, $808080, $000000, $ffffff))
    .for (var y=0; y<6	; y++)
        .for (var x=0;x<40; x++)
            .for(var cp=0; cp<8; cp++)
                .byte logoPic.getMulticolorByte(x,cp+y*8)
 }}
__constant char OFFSET_STRUCT_MOS6569_VICII_BG_COLOR = $21
__constant char OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1 = $22
__constant char OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2 = $23
__constant char OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR = $20
__constant char OFFSET_STRUCT_MOS6569_VICII_RASTER = $12
__constant const unsigned long PI2_u4f28 = $6487ed51
__constant const unsigned long PI_HALF_u4f28 = $1921fb54
__constant const unsigned long PI_u4f28 = $3243f6a9
__constant char *SCREEN = (char *) 1024
__constant char SIZEOF_INT = 2
__constant struct MOS6569_VICII * const VICII = (struct MOS6569_VICII *) 53248
__constant const char VICII_MCM = $10
__constant const char WHITE = 1
__constant const unsigned int XSIN_SIZE = $200
unsigned long div32u16u(unsigned long dividend , unsigned int divisor)
unsigned long div32u16u::dividend
unsigned int div32u16u::divisor
unsigned long div32u16u::quotient
unsigned int div32u16u::quotient_hi
unsigned int div32u16u::quotient_hi#0 // quotient_hi zp[2]:32 40.4
unsigned int div32u16u::quotient_lo
unsigned int div32u16u::quotient_lo#0 // quotient_lo zp[2]:20 202.0
unsigned long div32u16u::return
unsigned long div32u16u::return#0 // return zp[4]:22 22.0
unsigned long div32u16u::return#1 // return zp[4]:22 37.33333333333333
unsigned int divr16u(unsigned int dividend , unsigned int divisor , unsigned int rem)
char divr16u::$1 // reg byte a 20002.0
char divr16u::$2 // reg byte a 20002.0
unsigned int divr16u::dividend
unsigned int divr16u::dividend#0 // dividend zp[2]:18 2500.25
unsigned int divr16u::dividend#3 // dividend zp[2]:18 4429.142857142857
unsigned int divr16u::dividend#5 // dividend zp[2]:18 1001.0
unsigned int divr16u::divisor
char divr16u::i
char divr16u::i#1 // reg byte x 15001.5
char divr16u::i#2 // reg byte x 1538.6153846153845
unsigned int divr16u::quotient
unsigned int divr16u::quotient#1 // quotient zp[2]:20 15001.5
unsigned int divr16u::quotient#2 // quotient zp[2]:20 10001.0
unsigned int divr16u::quotient#3 // quotient zp[2]:20 2500.25
unsigned int divr16u::rem
unsigned int divr16u::rem#0 // rem zp[2]:26 7500.75
unsigned int divr16u::rem#1 // rem zp[2]:26 20002.0
unsigned int divr16u::rem#10 // rem zp[2]:26 1102.0
unsigned int divr16u::rem#11 // rem zp[2]:26 10334.666666666666
unsigned int divr16u::rem#2 // rem zp[2]:26 20002.0
unsigned int divr16u::rem#4 // rem zp[2]:26 202.0
unsigned int divr16u::rem#5 // rem zp[2]:26 21003.0
unsigned int divr16u::rem#6 // rem zp[2]:26 10001.0
unsigned int divr16u::return
unsigned int divr16u::return#0 // return zp[2]:20 4315.0
unsigned int divr16u::return#2 // return zp[2]:20 202.0
unsigned int divr16u::return#3 // return zp[2]:20 202.0
void loop()
int *loop::$2 // zp[2]:26 202.0
unsigned int loop::$7 // zp[2]:26 202.0
int loop::xpos
int loop::xpos#0 // xpos zp[2]:26 202.0
void main()
char main::ch
char main::ch#1 // reg byte x 16.5
char main::ch#2 // reg byte x 22.0
char *main::toD0181_gfx
char main::toD0181_return
__constant char main::toD0181_return#0 = byte1 (unsigned int)SCREEN&$3fff*4|byte1 (unsigned int)LOGO/4&$f // toD0181_return
char *main::toD0181_screen
void * memset(void *str , char c , unsigned int num)
char memset::c
char memset::c#4 // reg byte x 14.428571428571429
char *memset::dst
char *memset::dst#1 // dst zp[2]:36 202.0
char *memset::dst#2 // dst zp[2]:36 138.33333333333331
char *memset::dst#4 // dst zp[2]:36 22.0
char *memset::end
char *memset::end#0 // end zp[2]:34 18.666666666666664
unsigned int memset::num
void *memset::return
void *memset::str
void *memset::str#3 // str zp[2]:36
long mul16s(int a , int b)
unsigned int mul16s::$11 // zp[2]:34 2002.0
unsigned int mul16s::$6 // zp[2]:34 2002.0
int mul16s::a
int mul16s::a#0 // a zp[2]:26 220.39999999999998
int mul16s::b
unsigned long mul16s::m
unsigned long mul16s::m#0 // m zp[4]:12 1001.0
unsigned long mul16s::m#1 // m zp[4]:12 2002.0
unsigned long mul16s::m#4 // m zp[4]:12 2002.0
long mul16s::return
long mul16s::return#0 // return zp[4]:12 202.0
long mul16s::return#1 // return zp[4]:12 367.33333333333337
unsigned long mul16u(unsigned int a , unsigned int b)
char mul16u::$1 // reg byte a 2.0000002E7
unsigned int mul16u::a
unsigned int mul16u::a#0 // a zp[2]:34 10001.0
unsigned int mul16u::a#1 // a zp[2]:34 1.0000001E7
unsigned int mul16u::a#2 // a zp[2]:34 2002.0
unsigned int mul16u::a#3 // a zp[2]:34 6683334.166666666
unsigned int mul16u::a#6 // a zp[2]:34 55501.5
unsigned int mul16u::b
unsigned int mul16u::b#0 // b zp[2]:20 20002.0
unsigned int mul16u::b#2 // b zp[2]:20 10001.0
unsigned long mul16u::mb
unsigned long mul16u::mb#0 // mb zp[4]:28 200002.0
unsigned long mul16u::mb#1 // mb zp[4]:28 2.0000002E7
unsigned long mul16u::mb#2 // mb zp[4]:28 4300000.571428571
unsigned long mul16u::res
unsigned long mul16u::res#1 // res zp[4]:12 2.0000002E7
unsigned long mul16u::res#2 // res zp[4]:12 4287286.428571429
unsigned long mul16u::res#6 // res zp[4]:12 1.0000001E7
unsigned long mul16u::return
unsigned long mul16u::return#0 // return zp[4]:12 20002.0
unsigned long mul16u::return#3 // return zp[4]:12 2002.0
unsigned int mulu16_sel(unsigned int v1 , unsigned int v2 , char select)
unsigned long mulu16_sel::$0 // zp[4]:12 20002.0
unsigned long mulu16_sel::$1 // zp[4]:12 20002.0
unsigned int mulu16_sel::return
unsigned int mulu16_sel::return#0 // return zp[2]:34 2002.0
unsigned int mulu16_sel::return#1 // return_1 zp[2]:18 2002.0
unsigned int mulu16_sel::return#10 // return_1 zp[2]:18 2002.0
unsigned int mulu16_sel::return#11 // return zp[2]:34 2002.0
unsigned int mulu16_sel::return#12 // return zp[2]:34 2143.714285714286
unsigned int mulu16_sel::return#2 // return zp[2]:34 2002.0
char mulu16_sel::select
char mulu16_sel::select#5 // reg byte x 1666.8333333333333
unsigned int mulu16_sel::v1
unsigned int mulu16_sel::v1#0 // v1 zp[2]:18 1001.0
unsigned int mulu16_sel::v1#1 // v1 zp[2]:18 1001.0
unsigned int mulu16_sel::v1#2 // v1 zp[2]:18 2002.0
unsigned int mulu16_sel::v1#3 // v1 zp[2]:18 1001.0
unsigned int mulu16_sel::v1#4 // v1 zp[2]:18 1001.0
unsigned int mulu16_sel::v1#5 // v1 zp[2]:18 15006.0
unsigned int mulu16_sel::v2
unsigned int mulu16_sel::v2#0 // v2 zp[2]:20 2002.0
unsigned int mulu16_sel::v2#1 // v2 zp[2]:20 2002.0
unsigned int mulu16_sel::v2#3 // v2 zp[2]:20 2002.0
unsigned int mulu16_sel::v2#4 // v2 zp[2]:20 2002.0
unsigned int mulu16_sel::v2#5 // v2 zp[2]:20 7002.5
unsigned int rem16u
unsigned int rem16u#14 // rem16u zp[2]:26 220.39999999999998
void render_logo(int xpos)
char render_logo::$0 // reg byte a 2002.0
char render_logo::$1 // reg byte a 2002.0
int render_logo::$2 // zp[2]:36 1001.0
char render_logo::$25 // reg byte a 2002.0
char render_logo::$30 // reg byte a 200002.0
char render_logo::$33 // reg byte a 200002.0
char render_logo::$36 // reg byte a 200002.0
char render_logo::$39 // reg byte a 200002.0
char render_logo::$42 // reg byte a 200002.0
char render_logo::$70 // reg byte a 200002.0
char render_logo::$73 // reg byte a 200002.0
char render_logo::$76 // reg byte a 200002.0
char render_logo::$79 // reg byte a 200002.0
char render_logo::$82 // reg byte a 200002.0
char render_logo::line
char render_logo::line1
char render_logo::line2
char render_logo::line3
char render_logo::logo_idx
signed char render_logo::logo_idx#1 // reg byte a 1001.0
char render_logo::logo_idx#10 // logo_idx zp[1]:16 57143.42857142857
char render_logo::logo_idx#11 // logo_idx_1 zp[1]:17 64357.857142857145
char render_logo::logo_idx#14 // logo_idx_1 zp[1]:17 2002.0
char render_logo::logo_idx#3 // logo_idx zp[1]:16 200002.0
char render_logo::logo_idx#4 // logo_idx_1 zp[1]:17 200002.0
char render_logo::logo_start
char render_logo::screen_idx
char render_logo::screen_idx#10 // reg byte y 76923.84615384616
char render_logo::screen_idx#15 // reg byte y 125001.25
char render_logo::screen_idx#18 // reg byte y 125001.25
char render_logo::screen_idx#21 // reg byte y 69231.46153846155
char render_logo::screen_idx#3 // reg byte y 200002.0
char render_logo::screen_idx#4 // reg byte y 100001.0
char render_logo::screen_idx#5 // reg byte y 100001.0
char render_logo::screen_idx#6 // reg byte y 200002.0
signed char render_logo::x_char
signed char render_logo::x_char#0 // x_char zp[1]:38 182.0
int render_logo::xpos
int render_logo::xpos#0 // xpos zp[2]:26 300.42857142857144
int sin16s(unsigned long x)
unsigned long sin16s::$4 // zp[4]:28 2002.0
char sin16s::isUpper
char sin16s::isUpper#2 // reg byte y 30.333333333333332
int sin16s::return
int sin16s::return#0 // return zp[2]:26 202.0
int sin16s::return#1 // return zp[2]:26 701.0
int sin16s::return#5 // return zp[2]:26 2002.0
int sin16s::sinx
int sin16s::sinx#1 // sinx zp[2]:26 2002.0
unsigned int sin16s::usinx
unsigned int sin16s::usinx#0 // usinx zp[2]:26 166.83333333333334
unsigned int sin16s::usinx#1 // usinx zp[2]:26 500.5
unsigned long sin16s::x
unsigned long sin16s::x#0 // x zp[4]:8 1552.0
unsigned long sin16s::x#1 // x zp[4]:8 2002.0
unsigned long sin16s::x#2 // x zp[4]:8 2002.0
unsigned long sin16s::x#4 // x zp[4]:8 2502.5
unsigned long sin16s::x#6 // x zp[4]:8 3003.0
unsigned int sin16s::x1
unsigned int sin16s::x1#0 // x1 zp[2]:32 318.5
unsigned int sin16s::x2
unsigned int sin16s::x2#0 // x2 zp[2]:18 2002.0
unsigned int sin16s::x3
unsigned int sin16s::x3#0 // x3 zp[2]:18 500.5
unsigned int sin16s::x3_6
unsigned int sin16s::x3_6#0 // x3_6 zp[2]:34 2002.0
unsigned int sin16s::x4
unsigned int sin16s::x4#0 // x4 zp[2]:18 2002.0
unsigned int sin16s::x5
unsigned int sin16s::x5#0 // x5 zp[2]:34 2002.0
unsigned int sin16s::x5_128
unsigned int sin16s::x5_128#0 // x5_128 zp[2]:34 2002.0
void sin16s_gen2(int *sintab , unsigned int wavelength , int min , int max)
long sin16s_gen2::$6 // zp[4]:12 202.0
unsigned int sin16s_gen2::$8 // zp[2]:26 101.0
int sin16s_gen2::ampl
__constant int sin16s_gen2::ampl#0 = sin16s_gen2::max#0-sin16s_gen2::min#0 // ampl
unsigned int sin16s_gen2::i
unsigned int sin16s_gen2::i#1 // i zp[2]:36 202.0
unsigned int sin16s_gen2::i#2 // i zp[2]:36 23.307692307692307
int sin16s_gen2::max
__constant int sin16s_gen2::max#0 = $140 // max
int sin16s_gen2::min
__constant int sin16s_gen2::min#0 = -$140 // min
int sin16s_gen2::offs
int *sin16s_gen2::sintab
int *sin16s_gen2::sintab#0 // sintab zp[2]:6 67.33333333333333
int *sin16s_gen2::sintab#2 // sintab zp[2]:6 27.545454545454547
unsigned long sin16s_gen2::step
unsigned long sin16s_gen2::step#0 // step zp[4]:22 7.466666666666667
unsigned int sin16s_gen2::wavelength
unsigned long sin16s_gen2::x
unsigned long sin16s_gen2::x#1 // x zp[4]:2 101.0
unsigned long sin16s_gen2::x#2 // x zp[4]:2 25.25
__constant int xsin[XSIN_SIZE] = { fill( XSIN_SIZE, 0) }
unsigned int xsin_idx
unsigned int xsin_idx#12 // xsin_idx zp[2]:6 37.875
unsigned int xsin_idx#2 // xsin_idx zp[2]:6 101.0
unsigned int xsin_idx#21 // xsin_idx zp[2]:6 101.0

reg byte x [ main::ch#2 main::ch#1 ]
reg byte x [ memset::c#4 ]
zp[4]:2 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ]
zp[2]:6 [ xsin_idx#12 xsin_idx#21 xsin_idx#2 sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ]
reg byte y [ sin16s::isUpper#2 ]
zp[4]:8 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ]
zp[4]:12 [ mul16s::m#4 mul16s::m#1 mul16s::m#0 mul16u::return#3 mul16s::return#1 mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#0 mul16s::return#0 sin16s_gen2::$6 mulu16_sel::$0 mulu16_sel::$1 ]
reg byte y [ render_logo::screen_idx#10 render_logo::screen_idx#4 render_logo::screen_idx#18 render_logo::screen_idx#3 ]
zp[1]:16 [ render_logo::logo_idx#10 render_logo::logo_idx#3 ]
zp[1]:17 [ render_logo::logo_idx#11 render_logo::logo_idx#14 render_logo::logo_idx#4 ]
reg byte y [ render_logo::screen_idx#15 render_logo::screen_idx#21 render_logo::screen_idx#5 render_logo::screen_idx#6 ]
reg byte x [ divr16u::i#2 divr16u::i#1 ]
zp[2]:18 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mulu16_sel::return#1 mulu16_sel::return#10 divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ]
zp[2]:20 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 mul16u::b#2 mul16u::b#0 divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ]
reg byte x [ mulu16_sel::select#5 ]
zp[4]:22 [ div32u16u::return#0 sin16s_gen2::step#0 div32u16u::return#1 ]
zp[2]:26 [ loop::$7 loop::$2 loop::xpos#0 render_logo::xpos#0 sin16s_gen2::$8 divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 rem16u#14 sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 mul16s::a#0 sin16s::usinx#0 ]
zp[4]:28 [ sin16s::$4 mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
zp[2]:32 [ sin16s::x1#0 div32u16u::quotient_hi#0 ]
zp[2]:34 [ mul16s::$6 mul16s::$11 mulu16_sel::return#0 mulu16_sel::return#12 mulu16_sel::return#2 sin16s::x3_6#0 mulu16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 memset::end#0 mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ]
reg byte a [ render_logo::$25 ]
reg byte a [ render_logo::$0 ]
reg byte a [ render_logo::$1 ]
zp[2]:36 [ render_logo::$2 sin16s_gen2::i#2 sin16s_gen2::i#1 memset::str#3 memset::dst#2 memset::dst#4 memset::dst#1 ]
zp[1]:38 [ render_logo::x_char#0 ]
reg byte a [ render_logo::$30 ]
reg byte a [ render_logo::$33 ]
reg byte a [ render_logo::$36 ]
reg byte a [ render_logo::$39 ]
reg byte a [ render_logo::$42 ]
reg byte a [ render_logo::logo_idx#1 ]
reg byte a [ render_logo::$70 ]
reg byte a [ render_logo::$73 ]
reg byte a [ render_logo::$76 ]
reg byte a [ render_logo::$79 ]
reg byte a [ render_logo::$82 ]
reg byte a [ divr16u::$1 ]
reg byte a [ divr16u::$2 ]
reg byte a [ mul16u::$1 ]


FINAL ASSEMBLER
Score: 43921

  // File Comments
/// @file
/// Commodore 64 Registers and Constants
/// @file
/// The MOS 6526 Complex Interface Adapter (CIA)
///
/// http://archive.6502.org/datasheets/mos_6526_cia_recreated.pdf
  // Upstart
  // Commodore 64 PRG executable file
.file [name="scrolllogo.prg", type="prg", segments="Program"]
.segmentdef Program [segments="Basic, Code, Data"]
.segmentdef Basic [start=$0801]
.segmentdef Code [start=$80d]
.segmentdef Data [startAfter="Code"]
.segment Basic
:BasicUpstart(main)
  // Global Constants & labels
  /// $D016 Control register #2 Bit#4: MCM Turn Multicolor Mode on/off
  .const VICII_MCM = $10
  /// The colors of the C64
  .const BLACK = 0
  .const WHITE = 1
  .const DARK_GREY = $b
  // PI*2 in u[4.28] format
  .const PI2_u4f28 = $6487ed51
  // PI in u[4.28] format
  .const PI_u4f28 = $3243f6a9
  // PI/2 in u[4.28] format
  .const PI_HALF_u4f28 = $1921fb54
  .const XSIN_SIZE = $200
  .const SIZEOF_INT = 2
  .const OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR = $20
  .const OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1 = $22
  .const OFFSET_STRUCT_MOS6569_VICII_BG_COLOR = $21
  .const OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2 = $23
  .const OFFSET_STRUCT_MOS6569_VICII_RASTER = $12
  /// $D016 Control register 2
  /// @see #VICII_CONTROL2
  .label D016 = $d016
  /// $D018 VIC-II base addresses
  // @see #VICII_MEMORY
  .label D018 = $d018
  /// The VIC-II MOS 6567/6569
  .label VICII = $d000
  /// Color Ram
  .label COLS = $d800
  .label SCREEN = $400
  .label xsin_idx = 6
  // Remainder after unsigned 16-bit division
  .label rem16u = $1a
.segment Code
  // main
main: {
    .const toD0181_return = (>(SCREEN&$3fff)*4)|(>LOGO)/4&$f
    // asm
    // asm { sei  }
    sei
    // VICII->BORDER_COLOR = WHITE
    // [1] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = WHITE -- _deref_pbuc1=vbuc2 
    lda #WHITE
    sta VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR
    // VICII->BG_COLOR1 = DARK_GREY
    // [2] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) = DARK_GREY -- _deref_pbuc1=vbuc2 
    lda #DARK_GREY
    sta VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1
    // VICII->BG_COLOR = VICII->BG_COLOR1 = DARK_GREY
    // [3] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR) = *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR1) -- _deref_pbuc1=_deref_pbuc2 
    sta VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR
    // VICII->BG_COLOR2 = BLACK
    // [4] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2) = BLACK -- _deref_pbuc1=vbuc2 
    lda #BLACK
    sta VICII+OFFSET_STRUCT_MOS6569_VICII_BG_COLOR2
    // [5] phi from main to main::toD0181 [phi:main->main::toD0181]
    // main::toD0181
    // main::@3
    // *D018 = toD018(SCREEN, LOGO)
    // [6] *D018 = main::toD0181_return#0 -- _deref_pbuc1=vbuc2 
    lda #toD0181_return
    sta D018
    // *D016 = VICII_MCM
    // [7] *D016 = VICII_MCM -- _deref_pbuc1=vbuc2 
    lda #VICII_MCM
    sta D016
    // memset(SCREEN, BLACK, 1000)
    // [8] call memset
    // [20] phi from main::@3 to memset [phi:main::@3->memset]
    // [20] phi memset::c#4 = BLACK [phi:main::@3->memset#0] -- vbuxx=vbuc1 
    ldx #BLACK
    // [20] phi memset::str#3 = (void *)SCREEN [phi:main::@3->memset#1] -- pvoz1=pvoc1 
    lda #<SCREEN
    sta.z memset.str
    lda #>SCREEN
    sta.z memset.str+1
    jsr memset
    // [9] phi from main::@3 to main::@4 [phi:main::@3->main::@4]
    // main::@4
    // memset(COLS, WHITE|8, 1000)
    // [10] call memset
    // [20] phi from main::@4 to memset [phi:main::@4->memset]
    // [20] phi memset::c#4 = WHITE|8 [phi:main::@4->memset#0] -- vbuxx=vbuc1 
    ldx #WHITE|8
    // [20] phi memset::str#3 = (void *)COLS [phi:main::@4->memset#1] -- pvoz1=pvoc1 
    lda #<COLS
    sta.z memset.str
    lda #>COLS
    sta.z memset.str+1
    jsr memset
    // [11] phi from main::@4 to main::@1 [phi:main::@4->main::@1]
    // [11] phi main::ch#2 = 0 [phi:main::@4->main::@1#0] -- vbuxx=vbuc1 
    ldx #0
    // [11] phi from main::@1 to main::@1 [phi:main::@1->main::@1]
    // [11] phi main::ch#2 = main::ch#1 [phi:main::@1->main::@1#0] -- register_copy 
    // main::@1
  __b1:
    // SCREEN[ch] = ch
    // [12] SCREEN[main::ch#2] = main::ch#2 -- pbuc1_derefidx_vbuxx=vbuxx 
    txa
    sta SCREEN,x
    // for(char ch: 0..239)
    // [13] main::ch#1 = ++ main::ch#2 -- vbuxx=_inc_vbuxx 
    inx
    // [14] if(main::ch#1!=$f0) goto main::@1 -- vbuxx_neq_vbuc1_then_la1 
    cpx #$f0
    bne __b1
    // [15] phi from main::@1 to main::@2 [phi:main::@1->main::@2]
    // main::@2
    // sin16s_gen2(xsin, XSIN_SIZE, -320, 320)
    // [16] call sin16s_gen2
    // [28] phi from main::@2 to sin16s_gen2 [phi:main::@2->sin16s_gen2]
    jsr sin16s_gen2
    // [17] phi from main::@2 to main::@5 [phi:main::@2->main::@5]
    // main::@5
    // loop()
    // [18] call loop
    // [47] phi from main::@5 to loop [phi:main::@5->loop]
    jsr loop
    // main::@return
    // }
    // [19] return 
    rts
}
  // memset
// Copies the character c (an unsigned char) to the first num characters of the object pointed to by the argument str.
// void * memset(__zp($24) void *str, __register(X) char c, unsigned int num)
memset: {
    .label end = $22
    .label dst = $24
    .label str = $24
    // memset::@1
    // char* end = (char*)str + num
    // [21] memset::end#0 = (char *)memset::str#3 + $3e8 -- pbuz1=pbuz2_plus_vwuc1 
    lda.z str
    clc
    adc #<$3e8
    sta.z end
    lda.z str+1
    adc #>$3e8
    sta.z end+1
    // [22] memset::dst#4 = (char *)memset::str#3
    // [23] phi from memset::@1 memset::@3 to memset::@2 [phi:memset::@1/memset::@3->memset::@2]
    // [23] phi memset::dst#2 = memset::dst#4 [phi:memset::@1/memset::@3->memset::@2#0] -- register_copy 
    // memset::@2
  __b2:
    // for(char* dst = str; dst!=end; dst++)
    // [24] if(memset::dst#2!=memset::end#0) goto memset::@3 -- pbuz1_neq_pbuz2_then_la1 
    lda.z dst+1
    cmp.z end+1
    bne __b3
    lda.z dst
    cmp.z end
    bne __b3
    // memset::@return
    // }
    // [25] return 
    rts
    // memset::@3
  __b3:
    // *dst = c
    // [26] *memset::dst#2 = memset::c#4 -- _deref_pbuz1=vbuxx 
    txa
    ldy #0
    sta (dst),y
    // for(char* dst = str; dst!=end; dst++)
    // [27] memset::dst#1 = ++ memset::dst#2 -- pbuz1=_inc_pbuz1 
    inc.z dst
    bne !+
    inc.z dst+1
  !:
    jmp __b2
}
  // sin16s_gen2
// Generate signed int sine table - with values in the range min-max.
// sintab - the table to generate into
// wavelength - the number of sine points in a total sine wavelength (the size of the table)
// void sin16s_gen2(__zp(6) int *sintab, unsigned int wavelength, int min, int max)
sin16s_gen2: {
    .const min = -$140
    .const max = $140
    .label ampl = max-min
    .label __6 = $c
    .label __8 = $1a
    .label step = $16
    .label sintab = 6
    // u[4.28]
    // Iterate over the table
    .label x = 2
    .label i = $24
    // unsigned long step = div32u16u(PI2_u4f28, wavelength)
    // [29] call div32u16u
  // ampl is always positive so shifting left does not alter the sign
  // u[4.28] step = PI*2/wavelength
    // [61] phi from sin16s_gen2 to div32u16u [phi:sin16s_gen2->div32u16u]
    jsr div32u16u
    // unsigned long step = div32u16u(PI2_u4f28, wavelength)
    // [30] div32u16u::return#0 = div32u16u::return#1
    // sin16s_gen2::@3
    // [31] sin16s_gen2::step#0 = div32u16u::return#0
    // [32] phi from sin16s_gen2::@3 to sin16s_gen2::@1 [phi:sin16s_gen2::@3->sin16s_gen2::@1]
    // [32] phi sin16s_gen2::sintab#2 = xsin [phi:sin16s_gen2::@3->sin16s_gen2::@1#0] -- pwsz1=pwsc1 
    lda #<xsin
    sta.z sintab
    lda #>xsin
    sta.z sintab+1
    // [32] phi sin16s_gen2::x#2 = 0 [phi:sin16s_gen2::@3->sin16s_gen2::@1#1] -- vduz1=vduc1 
    lda #<0
    sta.z x
    sta.z x+1
    lda #<0>>$10
    sta.z x+2
    lda #>0>>$10
    sta.z x+3
    // [32] phi sin16s_gen2::i#2 = 0 [phi:sin16s_gen2::@3->sin16s_gen2::@1#2] -- vwuz1=vwuc1 
    lda #<0
    sta.z i
    sta.z i+1
  // u[4.28]
    // sin16s_gen2::@1
  __b1:
    // for( unsigned int i=0; i<wavelength; i++)
    // [33] if(sin16s_gen2::i#2<XSIN_SIZE) goto sin16s_gen2::@2 -- vwuz1_lt_vwuc1_then_la1 
    lda.z i+1
    cmp #>XSIN_SIZE
    bcc __b2
    bne !+
    lda.z i
    cmp #<XSIN_SIZE
    bcc __b2
  !:
    // sin16s_gen2::@return
    // }
    // [34] return 
    rts
    // sin16s_gen2::@2
  __b2:
    // sin16s(x)
    // [35] sin16s::x#0 = sin16s_gen2::x#2 -- vduz1=vduz2 
    lda.z x
    sta.z sin16s.x
    lda.z x+1
    sta.z sin16s.x+1
    lda.z x+2
    sta.z sin16s.x+2
    lda.z x+3
    sta.z sin16s.x+3
    // [36] call sin16s
    jsr sin16s
    // [37] sin16s::return#0 = sin16s::return#1
    // sin16s_gen2::@4
    // mul16s(sin16s(x), ampl)
    // [38] mul16s::a#0 = sin16s::return#0
    // [39] call mul16s
    jsr mul16s
    // [40] mul16s::return#0 = mul16s::return#1
    // sin16s_gen2::@5
    // [41] sin16s_gen2::$6 = mul16s::return#0
    // WORD1(mul16s(sin16s(x), ampl))
    // [42] sin16s_gen2::$8 = word1  sin16s_gen2::$6 -- vwuz1=_word1_vdsz2 
    lda.z __6+2
    sta.z __8
    lda.z __6+3
    sta.z __8+1
    // *sintab++ = offs + (signed int)WORD1(mul16s(sin16s(x), ampl))
    // [43] *sin16s_gen2::sintab#2 = (int)sin16s_gen2::$8 -- _deref_pwsz1=vwsz2 
    ldy #0
    lda.z __8
    sta (sintab),y
    iny
    lda.z __8+1
    sta (sintab),y
    // *sintab++ = offs + (signed int)WORD1(mul16s(sin16s(x), ampl));
    // [44] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_INT -- pwsz1=pwsz1_plus_vbuc1 
    lda #SIZEOF_INT
    clc
    adc.z sintab
    sta.z sintab
    bcc !+
    inc.z sintab+1
  !:
    // x = x + step
    // [45] sin16s_gen2::x#1 = sin16s_gen2::x#2 + sin16s_gen2::step#0 -- vduz1=vduz1_plus_vduz2 
    clc
    lda.z x
    adc.z step
    sta.z x
    lda.z x+1
    adc.z step+1
    sta.z x+1
    lda.z x+2
    adc.z step+2
    sta.z x+2
    lda.z x+3
    adc.z step+3
    sta.z x+3
    // for( unsigned int i=0; i<wavelength; i++)
    // [46] sin16s_gen2::i#1 = ++ sin16s_gen2::i#2 -- vwuz1=_inc_vwuz1 
    inc.z i
    bne !+
    inc.z i+1
  !:
    // [32] phi from sin16s_gen2::@5 to sin16s_gen2::@1 [phi:sin16s_gen2::@5->sin16s_gen2::@1]
    // [32] phi sin16s_gen2::sintab#2 = sin16s_gen2::sintab#0 [phi:sin16s_gen2::@5->sin16s_gen2::@1#0] -- register_copy 
    // [32] phi sin16s_gen2::x#2 = sin16s_gen2::x#1 [phi:sin16s_gen2::@5->sin16s_gen2::@1#1] -- register_copy 
    // [32] phi sin16s_gen2::i#2 = sin16s_gen2::i#1 [phi:sin16s_gen2::@5->sin16s_gen2::@1#2] -- register_copy 
    jmp __b1
}
  // loop
loop: {
    .label __2 = $1a
    .label __7 = $1a
    .label xpos = $1a
    // [48] phi from loop to loop::@1 [phi:loop->loop::@1]
    // [48] phi xsin_idx#12 = 0 [phi:loop->loop::@1#0] -- vwuz1=vwuc1 
    lda #<0
    sta.z xsin_idx
    sta.z xsin_idx+1
    // loop::@1
  __b1:
  // Wait for the raster to reach the bottom of the screen
    // loop::@2
  __b2:
    // while(VICII->RASTER!=$ff)
    // [49] if(*((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER)!=$ff) goto loop::@2 -- _deref_pbuc1_neq_vbuc2_then_la1 
    lda #$ff
    cmp VICII+OFFSET_STRUCT_MOS6569_VICII_RASTER
    bne __b2
    // loop::@3
    // (VICII->BORDER_COLOR)++;
    // [50] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = ++ *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) -- _deref_pbuc1=_inc__deref_pbuc1 
    inc VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR
    // xsin+xsin_idx
    // [51] loop::$7 = xsin_idx#12 << 1 -- vwuz1=vwuz2_rol_1 
    lda.z xsin_idx
    asl
    sta.z __7
    lda.z xsin_idx+1
    rol
    sta.z __7+1
    // [52] loop::$2 = xsin + loop::$7 -- pwsz1=pwsc1_plus_vwuz1 
    lda.z __2
    clc
    adc #<xsin
    sta.z __2
    lda.z __2+1
    adc #>xsin
    sta.z __2+1
    // signed int xpos = *(xsin+xsin_idx)
    // [53] loop::xpos#0 = *loop::$2 -- vwsz1=_deref_pwsz1 
    ldy #0
    lda (xpos),y
    pha
    iny
    lda (xpos),y
    sta.z xpos+1
    pla
    sta.z xpos
    // render_logo(xpos)
    // [54] render_logo::xpos#0 = loop::xpos#0
    // [55] call render_logo
    jsr render_logo
    // loop::@5
    // if(++xsin_idx==XSIN_SIZE)
    // [56] xsin_idx#2 = ++ xsin_idx#12 -- vwuz1=_inc_vwuz1 
    inc.z xsin_idx
    bne !+
    inc.z xsin_idx+1
  !:
    // [57] if(xsin_idx#2!=XSIN_SIZE) goto loop::@6 -- vwuz1_neq_vwuc1_then_la1 
    lda.z xsin_idx+1
    cmp #>XSIN_SIZE
    bne __b4
    lda.z xsin_idx
    cmp #<XSIN_SIZE
    bne __b4
    // [59] phi from loop::@5 to loop::@4 [phi:loop::@5->loop::@4]
    // [59] phi xsin_idx#21 = 0 [phi:loop::@5->loop::@4#0] -- vwuz1=vbuc1 
    lda #<0
    sta.z xsin_idx
    sta.z xsin_idx+1
    // [58] phi from loop::@5 to loop::@6 [phi:loop::@5->loop::@6]
    // loop::@6
    // [59] phi from loop::@6 to loop::@4 [phi:loop::@6->loop::@4]
    // [59] phi xsin_idx#21 = xsin_idx#2 [phi:loop::@6->loop::@4#0] -- register_copy 
    // loop::@4
  __b4:
    // (VICII->BORDER_COLOR)--;
    // [60] *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) = -- *((char *)VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR) -- _deref_pbuc1=_dec__deref_pbuc1 
    dec VICII+OFFSET_STRUCT_MOS6569_VICII_BORDER_COLOR
    // [48] phi from loop::@4 to loop::@1 [phi:loop::@4->loop::@1]
    // [48] phi xsin_idx#12 = xsin_idx#21 [phi:loop::@4->loop::@1#0] -- register_copy 
    jmp __b1
}
  // div32u16u
// Divide unsigned 32-bit unsigned long dividend with a 16-bit unsigned int divisor
// The 16-bit unsigned int remainder can be found in rem16u after the division
// __zp($16) unsigned long div32u16u(unsigned long dividend, unsigned int divisor)
div32u16u: {
    .label return = $16
    .label quotient_hi = $20
    .label quotient_lo = $14
    // unsigned int quotient_hi = divr16u(WORD1(dividend), divisor, 0)
    // [62] call divr16u
    // [180] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
    // [180] phi divr16u::dividend#5 = word1 PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
    lda #<PI2_u4f28>>$10
    sta.z divr16u.dividend
    lda #>PI2_u4f28>>$10
    sta.z divr16u.dividend+1
    // [180] phi divr16u::rem#10 = 0 [phi:div32u16u->divr16u#1] -- vwuz1=vbuc1 
    lda #<0
    sta.z divr16u.rem
    sta.z divr16u.rem+1
    jsr divr16u
    // unsigned int quotient_hi = divr16u(WORD1(dividend), divisor, 0)
    // [63] divr16u::return#2 = divr16u::return#0
    // div32u16u::@1
    // [64] div32u16u::quotient_hi#0 = divr16u::return#2 -- vwuz1=vwuz2 
    lda.z divr16u.return
    sta.z quotient_hi
    lda.z divr16u.return+1
    sta.z quotient_hi+1
    // unsigned int quotient_lo = divr16u(WORD0(dividend), divisor, rem16u)
    // [65] divr16u::rem#4 = rem16u#14
    // [66] call divr16u
    // [180] phi from div32u16u::@1 to divr16u [phi:div32u16u::@1->divr16u]
    // [180] phi divr16u::dividend#5 = word0 PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
    lda #<PI2_u4f28&$ffff
    sta.z divr16u.dividend
    lda #>PI2_u4f28&$ffff
    sta.z divr16u.dividend+1
    // [180] phi divr16u::rem#10 = divr16u::rem#4 [phi:div32u16u::@1->divr16u#1] -- register_copy 
    jsr divr16u
    // unsigned int quotient_lo = divr16u(WORD0(dividend), divisor, rem16u)
    // [67] divr16u::return#3 = divr16u::return#0
    // div32u16u::@2
    // [68] div32u16u::quotient_lo#0 = divr16u::return#3
    // unsigned long quotient = MAKELONG( quotient_hi, quotient_lo )
    // [69] div32u16u::return#1 = div32u16u::quotient_hi#0 dw= div32u16u::quotient_lo#0 -- vduz1=vwuz2_dword_vwuz3 
    lda.z quotient_hi
    sta.z return+2
    lda.z quotient_hi+1
    sta.z return+3
    lda.z quotient_lo
    sta.z return
    lda.z quotient_lo+1
    sta.z return+1
    // div32u16u::@return
    // }
    // [70] return 
    rts
}
  // sin16s
// Calculate signed int sine sin(x)
// x: unsigned long input u[4.28] in the interval $00000000 - PI2_u4f28
// result: signed int sin(x) s[0.15] - using the full range  -$7fff - $7fff
// __zp($1a) int sin16s(__zp(8) unsigned long x)
sin16s: {
    .label __4 = $1c
    .label x = 8
    .label return = $1a
    .label x1 = $20
    .label x2 = $12
    .label x3 = $12
    .label x3_6 = $22
    .label usinx = $1a
    .label x4 = $12
    .label x5 = $22
    .label x5_128 = $22
    .label sinx = $1a
    // if(x >= PI_u4f28 )
    // [71] if(sin16s::x#0<PI_u4f28) goto sin16s::@1 -- vduz1_lt_vduc1_then_la1 
    lda.z x+3
    cmp #>PI_u4f28>>$10
    bcc __b4
    bne !+
    lda.z x+2
    cmp #<PI_u4f28>>$10
    bcc __b4
    bne !+
    lda.z x+1
    cmp #>PI_u4f28
    bcc __b4
    bne !+
    lda.z x
    cmp #<PI_u4f28
    bcc __b4
  !:
    // sin16s::@4
    // x = x - PI_u4f28
    // [72] sin16s::x#1 = sin16s::x#0 - PI_u4f28 -- vduz1=vduz1_minus_vduc1 
    lda.z x
    sec
    sbc #<PI_u4f28
    sta.z x
    lda.z x+1
    sbc #>PI_u4f28
    sta.z x+1
    lda.z x+2
    sbc #<PI_u4f28>>$10
    sta.z x+2
    lda.z x+3
    sbc #>PI_u4f28>>$10
    sta.z x+3
    // [73] phi from sin16s::@4 to sin16s::@1 [phi:sin16s::@4->sin16s::@1]
    // [73] phi sin16s::isUpper#2 = 1 [phi:sin16s::@4->sin16s::@1#0] -- vbuyy=vbuc1 
    ldy #1
    // [73] phi sin16s::x#4 = sin16s::x#1 [phi:sin16s::@4->sin16s::@1#1] -- register_copy 
    jmp __b1
    // [73] phi from sin16s to sin16s::@1 [phi:sin16s->sin16s::@1]
  __b4:
    // [73] phi sin16s::isUpper#2 = 0 [phi:sin16s->sin16s::@1#0] -- vbuyy=vbuc1 
    ldy #0
    // [73] phi sin16s::x#4 = sin16s::x#0 [phi:sin16s->sin16s::@1#1] -- register_copy 
    // sin16s::@1
  __b1:
    // if(x >= PI_HALF_u4f28 )
    // [74] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 -- vduz1_lt_vduc1_then_la1 
    lda.z x+3
    cmp #>PI_HALF_u4f28>>$10
    bcc __b2
    bne !+
    lda.z x+2
    cmp #<PI_HALF_u4f28>>$10
    bcc __b2
    bne !+
    lda.z x+1
    cmp #>PI_HALF_u4f28
    bcc __b2
    bne !+
    lda.z x
    cmp #<PI_HALF_u4f28
    bcc __b2
  !:
    // sin16s::@5
    // x = PI_u4f28 - x
    // [75] sin16s::x#2 = PI_u4f28 - sin16s::x#4 -- vduz1=vduc1_minus_vduz1 
    lda #<PI_u4f28
    sec
    sbc.z x
    sta.z x
    lda #>PI_u4f28
    sbc.z x+1
    sta.z x+1
    lda #<PI_u4f28>>$10
    sbc.z x+2
    sta.z x+2
    lda #>PI_u4f28>>$10
    sbc.z x+3
    sta.z x+3
    // [76] phi from sin16s::@1 sin16s::@5 to sin16s::@2 [phi:sin16s::@1/sin16s::@5->sin16s::@2]
    // [76] phi sin16s::x#6 = sin16s::x#4 [phi:sin16s::@1/sin16s::@5->sin16s::@2#0] -- register_copy 
    // sin16s::@2
  __b2:
    // x<<3
    // [77] sin16s::$4 = sin16s::x#6 << 3 -- vduz1=vduz2_rol_3 
    lda.z x
    asl
    sta.z __4
    lda.z x+1
    rol
    sta.z __4+1
    lda.z x+2
    rol
    sta.z __4+2
    lda.z x+3
    rol
    sta.z __4+3
    asl.z __4
    rol.z __4+1
    rol.z __4+2
    rol.z __4+3
    asl.z __4
    rol.z __4+1
    rol.z __4+2
    rol.z __4+3
    // unsigned int x1 = WORD1(x<<3)
    // [78] sin16s::x1#0 = word1  sin16s::$4 -- vwuz1=_word1_vduz2 
    // sinx = x - x^3/6 + x5/128;
    lda.z __4+2
    sta.z x1
    lda.z __4+3
    sta.z x1+1
    // unsigned int x2 = mulu16_sel(x1, x1, 0)
    // [79] mulu16_sel::v1#0 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v1
    lda.z x1+1
    sta.z mulu16_sel.v1+1
    // [80] mulu16_sel::v2#0 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v2
    lda.z x1+1
    sta.z mulu16_sel.v2+1
    // [81] call mulu16_sel
  // u[1.15]
    // [198] phi from sin16s::@2 to mulu16_sel [phi:sin16s::@2->mulu16_sel]
    // [198] phi mulu16_sel::select#5 = 0 [phi:sin16s::@2->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #0
    // [198] phi mulu16_sel::v2#5 = mulu16_sel::v2#0 [phi:sin16s::@2->mulu16_sel#1] -- register_copy 
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#0 [phi:sin16s::@2->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // unsigned int x2 = mulu16_sel(x1, x1, 0)
    // [82] mulu16_sel::return#0 = mulu16_sel::return#12
    // sin16s::@7
    // [83] sin16s::x2#0 = mulu16_sel::return#0 -- vwuz1=vwuz2 
    lda.z mulu16_sel.return
    sta.z x2
    lda.z mulu16_sel.return+1
    sta.z x2+1
    // unsigned int x3 = mulu16_sel(x2, x1, 1)
    // [84] mulu16_sel::v1#1 = sin16s::x2#0
    // [85] mulu16_sel::v2#1 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v2
    lda.z x1+1
    sta.z mulu16_sel.v2+1
    // [86] call mulu16_sel
  // u[2.14] x^2
    // [198] phi from sin16s::@7 to mulu16_sel [phi:sin16s::@7->mulu16_sel]
    // [198] phi mulu16_sel::select#5 = 1 [phi:sin16s::@7->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #1
    // [198] phi mulu16_sel::v2#5 = mulu16_sel::v2#1 [phi:sin16s::@7->mulu16_sel#1] -- register_copy 
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#1 [phi:sin16s::@7->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // unsigned int x3 = mulu16_sel(x2, x1, 1)
    // [87] mulu16_sel::return#1 = mulu16_sel::return#12 -- vwuz1=vwuz2 
    lda.z mulu16_sel.return
    sta.z mulu16_sel.return_1
    lda.z mulu16_sel.return+1
    sta.z mulu16_sel.return_1+1
    // sin16s::@8
    // [88] sin16s::x3#0 = mulu16_sel::return#1
    // unsigned int x3_6 = mulu16_sel(x3, $10000/6, 1)
    // [89] mulu16_sel::v1#2 = sin16s::x3#0
    // [90] call mulu16_sel
  // u[2.14] x^3
    // [198] phi from sin16s::@8 to mulu16_sel [phi:sin16s::@8->mulu16_sel]
    // [198] phi mulu16_sel::select#5 = 1 [phi:sin16s::@8->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #1
    // [198] phi mulu16_sel::v2#5 = (unsigned int)$10000/6 [phi:sin16s::@8->mulu16_sel#1] -- vwuz1=vwuc1 
    lda #<$10000/6
    sta.z mulu16_sel.v2
    lda #>$10000/6
    sta.z mulu16_sel.v2+1
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#2 [phi:sin16s::@8->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // unsigned int x3_6 = mulu16_sel(x3, $10000/6, 1)
    // [91] mulu16_sel::return#2 = mulu16_sel::return#12
    // sin16s::@9
    // [92] sin16s::x3_6#0 = mulu16_sel::return#2
    // unsigned int usinx = x1 - x3_6
    // [93] sin16s::usinx#0 = sin16s::x1#0 - sin16s::x3_6#0 -- vwuz1=vwuz2_minus_vwuz3 
    // u[1.15] x^3/6;
    lda.z x1
    sec
    sbc.z x3_6
    sta.z usinx
    lda.z x1+1
    sbc.z x3_6+1
    sta.z usinx+1
    // unsigned int x4 = mulu16_sel(x3, x1, 0)
    // [94] mulu16_sel::v1#3 = sin16s::x3#0
    // [95] mulu16_sel::v2#3 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v2
    lda.z x1+1
    sta.z mulu16_sel.v2+1
    // [96] call mulu16_sel
  // u[1.15] x - x^3/6
    // [198] phi from sin16s::@9 to mulu16_sel [phi:sin16s::@9->mulu16_sel]
    // [198] phi mulu16_sel::select#5 = 0 [phi:sin16s::@9->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #0
    // [198] phi mulu16_sel::v2#5 = mulu16_sel::v2#3 [phi:sin16s::@9->mulu16_sel#1] -- register_copy 
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#3 [phi:sin16s::@9->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // unsigned int x4 = mulu16_sel(x3, x1, 0)
    // [97] mulu16_sel::return#10 = mulu16_sel::return#12 -- vwuz1=vwuz2 
    lda.z mulu16_sel.return
    sta.z mulu16_sel.return_1
    lda.z mulu16_sel.return+1
    sta.z mulu16_sel.return_1+1
    // sin16s::@10
    // [98] sin16s::x4#0 = mulu16_sel::return#10
    // unsigned int x5 = mulu16_sel(x4, x1, 0)
    // [99] mulu16_sel::v1#4 = sin16s::x4#0
    // [100] mulu16_sel::v2#4 = sin16s::x1#0 -- vwuz1=vwuz2 
    lda.z x1
    sta.z mulu16_sel.v2
    lda.z x1+1
    sta.z mulu16_sel.v2+1
    // [101] call mulu16_sel
  // u[3.13] x^4
    // [198] phi from sin16s::@10 to mulu16_sel [phi:sin16s::@10->mulu16_sel]
    // [198] phi mulu16_sel::select#5 = 0 [phi:sin16s::@10->mulu16_sel#0] -- vbuxx=vbuc1 
    ldx #0
    // [198] phi mulu16_sel::v2#5 = mulu16_sel::v2#4 [phi:sin16s::@10->mulu16_sel#1] -- register_copy 
    // [198] phi mulu16_sel::v1#5 = mulu16_sel::v1#4 [phi:sin16s::@10->mulu16_sel#2] -- register_copy 
    jsr mulu16_sel
    // unsigned int x5 = mulu16_sel(x4, x1, 0)
    // [102] mulu16_sel::return#11 = mulu16_sel::return#12
    // sin16s::@11
    // [103] sin16s::x5#0 = mulu16_sel::return#11
    // unsigned int x5_128 = x5>>4
    // [104] sin16s::x5_128#0 = sin16s::x5#0 >> 4 -- vwuz1=vwuz1_ror_4 
    // u[4.12] x^5
    lsr.z x5_128+1
    ror.z x5_128
    lsr.z x5_128+1
    ror.z x5_128
    lsr.z x5_128+1
    ror.z x5_128
    lsr.z x5_128+1
    ror.z x5_128
    // usinx = usinx + x5_128
    // [105] sin16s::usinx#1 = sin16s::usinx#0 + sin16s::x5_128#0 -- vwuz1=vwuz1_plus_vwuz2 
    clc
    lda.z usinx
    adc.z x5_128
    sta.z usinx
    lda.z usinx+1
    adc.z x5_128+1
    sta.z usinx+1
    // if(isUpper!=0)
    // [106] if(sin16s::isUpper#2==0) goto sin16s::@12 -- vbuyy_eq_0_then_la1 
    cpy #0
    beq __b3
    // sin16s::@6
    // sinx = -(signed int)usinx
    // [107] sin16s::sinx#1 = - (int)sin16s::usinx#1 -- vwsz1=_neg_vwsz1 
    lda #0
    sec
    sbc.z sinx
    sta.z sinx
    lda #0
    sbc.z sinx+1
    sta.z sinx+1
    // [108] phi from sin16s::@12 sin16s::@6 to sin16s::@3 [phi:sin16s::@12/sin16s::@6->sin16s::@3]
    // [108] phi sin16s::return#1 = sin16s::return#5 [phi:sin16s::@12/sin16s::@6->sin16s::@3#0] -- register_copy 
    // sin16s::@3
  __b3:
    // sin16s::@return
    // }
    // [109] return 
    rts
    // sin16s::@12
    // [110] sin16s::return#5 = (int)sin16s::usinx#1
}
  // mul16s
// Multiply of two signed ints to a signed long
// Fixes offsets introduced by using unsigned multiplication
// __zp($c) long mul16s(__zp($1a) int a, int b)
mul16s: {
    .label __6 = $22
    .label __11 = $22
    .label a = $1a
    .label return = $c
    .label m = $c
    // unsigned long m = mul16u((unsigned int)a, (unsigned int) b)
    // [111] mul16u::a#2 = (unsigned int)mul16s::a#0 -- vwuz1=vwuz2 
    lda.z a
    sta.z mul16u.a
    lda.z a+1
    sta.z mul16u.a+1
    // [112] call mul16u
    // [207] phi from mul16s to mul16u [phi:mul16s->mul16u]
    // [207] phi mul16u::a#6 = mul16u::a#2 [phi:mul16s->mul16u#0] -- register_copy 
    // [207] phi mul16u::b#2 = (unsigned int)sin16s_gen2::ampl#0 [phi:mul16s->mul16u#1] -- vwuz1=vwuc1 
    lda #<sin16s_gen2.ampl
    sta.z mul16u.b
    lda #>sin16s_gen2.ampl
    sta.z mul16u.b+1
    jsr mul16u
    // unsigned long m = mul16u((unsigned int)a, (unsigned int) b)
    // [113] mul16u::return#3 = mul16u::res#2
    // mul16s::@4
    // [114] mul16s::m#0 = mul16u::return#3
    // if(a<0)
    // [115] if(mul16s::a#0>=0) goto mul16s::@1 -- vwsz1_ge_0_then_la1 
    lda.z a+1
    bpl __b2
    // mul16s::@3
    // WORD1(m)
    // [116] mul16s::$6 = word1  mul16s::m#0 -- vwuz1=_word1_vduz2 
    lda.z m+2
    sta.z __6
    lda.z m+3
    sta.z __6+1
    // WORD1(m) = WORD1(m)-(unsigned int)b
    // [117] mul16s::$11 = mul16s::$6 - (unsigned int)sin16s_gen2::ampl#0 -- vwuz1=vwuz1_minus_vwuc1 
    lda.z __11
    sec
    sbc #<sin16s_gen2.ampl
    sta.z __11
    lda.z __11+1
    sbc #>sin16s_gen2.ampl
    sta.z __11+1
    // [118] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11 -- vduz1=vduz1_setword1_vwuz2 
    lda.z __11
    sta.z m+2
    lda.z __11+1
    sta.z m+3
    // [119] phi from mul16s::@3 mul16s::@4 to mul16s::@1 [phi:mul16s::@3/mul16s::@4->mul16s::@1]
    // [119] phi mul16s::m#4 = mul16s::m#1 [phi:mul16s::@3/mul16s::@4->mul16s::@1#0] -- register_copy 
    // mul16s::@1
    // mul16s::@2
  __b2:
    // return (signed long)m;
    // [120] mul16s::return#1 = (long)mul16s::m#4
    // mul16s::@return
    // }
    // [121] return 
    rts
}
  // render_logo
// void render_logo(__zp($1a) int xpos)
render_logo: {
    .label __2 = $24
    .label xpos = $1a
    .label x_char = $26
    .label logo_idx = $10
    .label logo_idx_1 = $11
    // (char)xpos&7
    // [122] render_logo::$25 = (char)render_logo::xpos#0 -- vbuaa=_byte_vwsz1 
    lda.z xpos
    // [123] render_logo::$0 = render_logo::$25 & 7 -- vbuaa=vbuaa_band_vbuc1 
    and #7
    // VICII_MCM|((char)xpos&7)
    // [124] render_logo::$1 = VICII_MCM | render_logo::$0 -- vbuaa=vbuc1_bor_vbuaa 
    ora #VICII_MCM
    // *D016 = VICII_MCM|((char)xpos&7)
    // [125] *D016 = render_logo::$1 -- _deref_pbuc1=vbuaa 
    sta D016
    // xpos/8
    // [126] render_logo::$2 = render_logo::xpos#0 >> 3 -- vwsz1=vwsz2_ror_3 
    lda.z xpos+1
    cmp #$80
    ror
    sta.z __2+1
    lda.z xpos
    ror
    sta.z __2
    lda.z __2+1
    cmp #$80
    ror.z __2+1
    ror.z __2
    lda.z __2+1
    cmp #$80
    ror.z __2+1
    ror.z __2
    // signed char x_char = (signed char)(xpos/8)
    // [127] render_logo::x_char#0 = (signed char)render_logo::$2 -- vbsz1=_sbyte_vwsz2 
    lda.z __2
    sta.z x_char
    // if(xpos<0)
    // [128] if(render_logo::xpos#0<0) goto render_logo::@1 -- vwsz1_lt_0_then_la1 
    lda.z xpos+1
    bmi __b1
    // [129] phi from render_logo to render_logo::@2 [phi:render_logo->render_logo::@2]
    // [129] phi render_logo::screen_idx#18 = 0 [phi:render_logo->render_logo::@2#0] -- vbuyy=vbuc1 
    ldy #0
    // render_logo::@2
  __b2:
    // while(screen_idx!=logo_start)
    // [130] if(render_logo::screen_idx#18!=(char)render_logo::x_char#0) goto render_logo::@3 -- vbuyy_neq_vbuz1_then_la1 
    cpy.z x_char
    bne __b3
    // [131] phi from render_logo::@2 to render_logo::@5 [phi:render_logo::@2->render_logo::@5]
    // [131] phi render_logo::logo_idx#10 = 0 [phi:render_logo::@2->render_logo::@5#0] -- vbuz1=vbuc1 
    lda #0
    sta.z logo_idx
    // [131] phi render_logo::screen_idx#10 = render_logo::screen_idx#18 [phi:render_logo::@2->render_logo::@5#1] -- register_copy 
    // render_logo::@5
  __b5:
    // while(screen_idx!=40)
    // [132] if(render_logo::screen_idx#10!=$28) goto render_logo::@6 -- vbuyy_neq_vbuc1_then_la1 
    cpy #$28
    bne __b6
    // render_logo::@return
    // }
    // [133] return 
    rts
    // render_logo::@6
  __b6:
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [134] SCREEN[render_logo::screen_idx#10] = render_logo::logo_idx#10 -- pbuc1_derefidx_vbuyy=vbuz1 
    lda.z logo_idx
    sta SCREEN,y
    // render_logo::@10_1
    // logo_idx+40*line
    // [135] render_logo::$30 = render_logo::logo_idx#10 + $28*1 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*1
    clc
    adc.z logo_idx
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [136] (SCREEN+$28*1)[render_logo::screen_idx#10] = render_logo::$30 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*1,y
    // render_logo::@10_2
    // logo_idx+40*line
    // [137] render_logo::$33 = render_logo::logo_idx#10 + $28*2 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*2
    clc
    adc.z logo_idx
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [138] (SCREEN+$28*2)[render_logo::screen_idx#10] = render_logo::$33 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*2,y
    // render_logo::@10_3
    // logo_idx+40*line
    // [139] render_logo::$36 = render_logo::logo_idx#10 + $28*3 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*3
    clc
    adc.z logo_idx
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [140] (SCREEN+$28*3)[render_logo::screen_idx#10] = render_logo::$36 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*3,y
    // render_logo::@10_4
    // logo_idx+40*line
    // [141] render_logo::$39 = render_logo::logo_idx#10 + $28*4 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*4
    clc
    adc.z logo_idx
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [142] (SCREEN+$28*4)[render_logo::screen_idx#10] = render_logo::$39 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*4,y
    // render_logo::@10_5
    // logo_idx+40*line
    // [143] render_logo::$42 = render_logo::logo_idx#10 + $28*5 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*5
    clc
    adc.z logo_idx
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [144] (SCREEN+$28*5)[render_logo::screen_idx#10] = render_logo::$42 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*5,y
    // render_logo::@7
    // screen_idx++;
    // [145] render_logo::screen_idx#4 = ++ render_logo::screen_idx#10 -- vbuyy=_inc_vbuyy 
    iny
    // logo_idx++;
    // [146] render_logo::logo_idx#3 = ++ render_logo::logo_idx#10 -- vbuz1=_inc_vbuz1 
    inc.z logo_idx
    // [131] phi from render_logo::@7 to render_logo::@5 [phi:render_logo::@7->render_logo::@5]
    // [131] phi render_logo::logo_idx#10 = render_logo::logo_idx#3 [phi:render_logo::@7->render_logo::@5#0] -- register_copy 
    // [131] phi render_logo::screen_idx#10 = render_logo::screen_idx#4 [phi:render_logo::@7->render_logo::@5#1] -- register_copy 
    jmp __b5
    // render_logo::@3
  __b3:
    // (SCREEN+40*line)[screen_idx] = $00
    // [147] SCREEN[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN,y
    // render_logo::@6_1
    // [148] (SCREEN+$28*1)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*1,y
    // render_logo::@6_2
    // [149] (SCREEN+$28*2)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*2,y
    // render_logo::@6_3
    // [150] (SCREEN+$28*3)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*3,y
    // render_logo::@6_4
    // [151] (SCREEN+$28*4)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*4,y
    // render_logo::@6_5
    // [152] (SCREEN+$28*5)[render_logo::screen_idx#18] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*5,y
    // render_logo::@4
    // screen_idx++;
    // [153] render_logo::screen_idx#3 = ++ render_logo::screen_idx#18 -- vbuyy=_inc_vbuyy 
    iny
    // [129] phi from render_logo::@4 to render_logo::@2 [phi:render_logo::@4->render_logo::@2]
    // [129] phi render_logo::screen_idx#18 = render_logo::screen_idx#3 [phi:render_logo::@4->render_logo::@2#0] -- register_copy 
    jmp __b2
    // render_logo::@1
  __b1:
    // -x_char
    // [154] render_logo::logo_idx#1 = - render_logo::x_char#0 -- vbsaa=_neg_vbsz1 
    lda.z x_char
    eor #$ff
    clc
    adc #1
    // [155] render_logo::logo_idx#14 = (char)render_logo::logo_idx#1 -- vbuz1=vbuaa 
    sta.z logo_idx_1
    // [156] phi from render_logo::@1 to render_logo::@8 [phi:render_logo::@1->render_logo::@8]
    // [156] phi render_logo::screen_idx#21 = 0 [phi:render_logo::@1->render_logo::@8#0] -- vbuyy=vbuc1 
    ldy #0
    // [156] phi render_logo::logo_idx#11 = render_logo::logo_idx#14 [phi:render_logo::@1->render_logo::@8#1] -- register_copy 
    // render_logo::@8
  __b8:
    // while(logo_idx!=40)
    // [157] if(render_logo::logo_idx#11!=$28) goto render_logo::@9 -- vbuz1_neq_vbuc1_then_la1 
    lda #$28
    cmp.z logo_idx_1
    bne __b9
    // [158] phi from render_logo::@13 render_logo::@8 to render_logo::@11 [phi:render_logo::@13/render_logo::@8->render_logo::@11]
    // [158] phi render_logo::screen_idx#15 = render_logo::screen_idx#6 [phi:render_logo::@13/render_logo::@8->render_logo::@11#0] -- register_copy 
    // render_logo::@11
  __b11:
    // while(screen_idx!=40)
    // [159] if(render_logo::screen_idx#15!=$28) goto render_logo::@12 -- vbuyy_neq_vbuc1_then_la1 
    cpy #$28
    bne __b12
    rts
    // render_logo::@12
  __b12:
    // (SCREEN+40*line)[screen_idx] = $00
    // [160] SCREEN[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    lda #0
    sta SCREEN,y
    // render_logo::@18_1
    // [161] (SCREEN+$28*1)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*1,y
    // render_logo::@18_2
    // [162] (SCREEN+$28*2)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*2,y
    // render_logo::@18_3
    // [163] (SCREEN+$28*3)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*3,y
    // render_logo::@18_4
    // [164] (SCREEN+$28*4)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*4,y
    // render_logo::@18_5
    // [165] (SCREEN+$28*5)[render_logo::screen_idx#15] = 0 -- pbuc1_derefidx_vbuyy=vbuc2 
    sta SCREEN+$28*5,y
    // render_logo::@13
    // screen_idx++;
    // [166] render_logo::screen_idx#6 = ++ render_logo::screen_idx#15 -- vbuyy=_inc_vbuyy 
    iny
    jmp __b11
    // render_logo::@9
  __b9:
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [167] SCREEN[render_logo::screen_idx#21] = render_logo::logo_idx#11 -- pbuc1_derefidx_vbuyy=vbuz1 
    lda.z logo_idx_1
    sta SCREEN,y
    // render_logo::@14_1
    // logo_idx+40*line
    // [168] render_logo::$70 = render_logo::logo_idx#11 + $28*1 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*1
    clc
    adc.z logo_idx_1
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [169] (SCREEN+$28*1)[render_logo::screen_idx#21] = render_logo::$70 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*1,y
    // render_logo::@14_2
    // logo_idx+40*line
    // [170] render_logo::$73 = render_logo::logo_idx#11 + $28*2 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*2
    clc
    adc.z logo_idx_1
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [171] (SCREEN+$28*2)[render_logo::screen_idx#21] = render_logo::$73 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*2,y
    // render_logo::@14_3
    // logo_idx+40*line
    // [172] render_logo::$76 = render_logo::logo_idx#11 + $28*3 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*3
    clc
    adc.z logo_idx_1
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [173] (SCREEN+$28*3)[render_logo::screen_idx#21] = render_logo::$76 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*3,y
    // render_logo::@14_4
    // logo_idx+40*line
    // [174] render_logo::$79 = render_logo::logo_idx#11 + $28*4 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*4
    clc
    adc.z logo_idx_1
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [175] (SCREEN+$28*4)[render_logo::screen_idx#21] = render_logo::$79 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*4,y
    // render_logo::@14_5
    // logo_idx+40*line
    // [176] render_logo::$82 = render_logo::logo_idx#11 + $28*5 -- vbuaa=vbuz1_plus_vbuc1 
    lda #$28*5
    clc
    adc.z logo_idx_1
    // (SCREEN+40*line)[screen_idx] = logo_idx+40*line
    // [177] (SCREEN+$28*5)[render_logo::screen_idx#21] = render_logo::$82 -- pbuc1_derefidx_vbuyy=vbuaa 
    sta SCREEN+$28*5,y
    // render_logo::@10
    // screen_idx++;
    // [178] render_logo::screen_idx#5 = ++ render_logo::screen_idx#21 -- vbuyy=_inc_vbuyy 
    iny
    // logo_idx++;
    // [179] render_logo::logo_idx#4 = ++ render_logo::logo_idx#11 -- vbuz1=_inc_vbuz1 
    inc.z logo_idx_1
    // [156] phi from render_logo::@10 to render_logo::@8 [phi:render_logo::@10->render_logo::@8]
    // [156] phi render_logo::screen_idx#21 = render_logo::screen_idx#5 [phi:render_logo::@10->render_logo::@8#0] -- register_copy 
    // [156] phi render_logo::logo_idx#11 = render_logo::logo_idx#4 [phi:render_logo::@10->render_logo::@8#1] -- register_copy 
    jmp __b8
}
  // divr16u
// Performs division on two 16 bit unsigned ints and an initial remainder
// Returns the quotient dividend/divisor.
// The final remainder will be set into the global variable rem16u
// Implemented using simple binary division
// __zp($14) unsigned int divr16u(__zp($12) unsigned int dividend, unsigned int divisor, __zp($1a) unsigned int rem)
divr16u: {
    .label rem = $1a
    .label dividend = $12
    .label quotient = $14
    .label return = $14
    // [181] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
    // [181] phi divr16u::i#2 = 0 [phi:divr16u->divr16u::@1#0] -- vbuxx=vbuc1 
    ldx #0
    // [181] phi divr16u::quotient#3 = 0 [phi:divr16u->divr16u::@1#1] -- vwuz1=vwuc1 
    txa
    sta.z quotient
    sta.z quotient+1
    // [181] phi divr16u::dividend#3 = divr16u::dividend#5 [phi:divr16u->divr16u::@1#2] -- register_copy 
    // [181] phi divr16u::rem#5 = divr16u::rem#10 [phi:divr16u->divr16u::@1#3] -- register_copy 
    // [181] phi from divr16u::@3 to divr16u::@1 [phi:divr16u::@3->divr16u::@1]
    // [181] phi divr16u::i#2 = divr16u::i#1 [phi:divr16u::@3->divr16u::@1#0] -- register_copy 
    // [181] phi divr16u::quotient#3 = divr16u::return#0 [phi:divr16u::@3->divr16u::@1#1] -- register_copy 
    // [181] phi divr16u::dividend#3 = divr16u::dividend#0 [phi:divr16u::@3->divr16u::@1#2] -- register_copy 
    // [181] phi divr16u::rem#5 = divr16u::rem#11 [phi:divr16u::@3->divr16u::@1#3] -- register_copy 
    // divr16u::@1
  __b1:
    // rem = rem << 1
    // [182] divr16u::rem#0 = divr16u::rem#5 << 1 -- vwuz1=vwuz1_rol_1 
    asl.z rem
    rol.z rem+1
    // BYTE1(dividend)
    // [183] divr16u::$1 = byte1  divr16u::dividend#3 -- vbuaa=_byte1_vwuz1 
    lda.z dividend+1
    // BYTE1(dividend) & $80
    // [184] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
    and #$80
    // if( (BYTE1(dividend) & $80) != 0 )
    // [185] if(divr16u::$2==0) goto divr16u::@2 -- vbuaa_eq_0_then_la1 
    cmp #0
    beq __b2
    // divr16u::@4
    // rem = rem | 1
    // [186] divr16u::rem#1 = divr16u::rem#0 | 1 -- vwuz1=vwuz1_bor_vbuc1 
    lda #1
    ora.z rem
    sta.z rem
    // [187] phi from divr16u::@1 divr16u::@4 to divr16u::@2 [phi:divr16u::@1/divr16u::@4->divr16u::@2]
    // [187] phi divr16u::rem#6 = divr16u::rem#0 [phi:divr16u::@1/divr16u::@4->divr16u::@2#0] -- register_copy 
    // divr16u::@2
  __b2:
    // dividend = dividend << 1
    // [188] divr16u::dividend#0 = divr16u::dividend#3 << 1 -- vwuz1=vwuz1_rol_1 
    asl.z dividend
    rol.z dividend+1
    // quotient = quotient << 1
    // [189] divr16u::quotient#1 = divr16u::quotient#3 << 1 -- vwuz1=vwuz1_rol_1 
    asl.z quotient
    rol.z quotient+1
    // if(rem>=divisor)
    // [190] if(divr16u::rem#6<XSIN_SIZE) goto divr16u::@3 -- vwuz1_lt_vwuc1_then_la1 
    lda.z rem+1
    cmp #>XSIN_SIZE
    bcc __b3
    bne !+
    lda.z rem
    cmp #<XSIN_SIZE
    bcc __b3
  !:
    // divr16u::@5
    // quotient++;
    // [191] divr16u::quotient#2 = ++ divr16u::quotient#1 -- vwuz1=_inc_vwuz1 
    inc.z quotient
    bne !+
    inc.z quotient+1
  !:
    // rem = rem - divisor
    // [192] divr16u::rem#2 = divr16u::rem#6 - XSIN_SIZE -- vwuz1=vwuz1_minus_vwuc1 
    lda.z rem
    sec
    sbc #<XSIN_SIZE
    sta.z rem
    lda.z rem+1
    sbc #>XSIN_SIZE
    sta.z rem+1
    // [193] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
    // [193] phi divr16u::return#0 = divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy 
    // [193] phi divr16u::rem#11 = divr16u::rem#6 [phi:divr16u::@2/divr16u::@5->divr16u::@3#1] -- register_copy 
    // divr16u::@3
  __b3:
    // for( char i : 0..15)
    // [194] divr16u::i#1 = ++ divr16u::i#2 -- vbuxx=_inc_vbuxx 
    inx
    // [195] if(divr16u::i#1!=$10) goto divr16u::@1 -- vbuxx_neq_vbuc1_then_la1 
    cpx #$10
    bne __b1
    // divr16u::@6
    // rem16u = rem
    // [196] rem16u#14 = divr16u::rem#11
    // divr16u::@return
    // }
    // [197] return 
    rts
}
  // mulu16_sel
// Calculate val*val for two unsigned int values - the result is 16 selected bits of the 32-bit result.
// The select parameter indicates how many of the highest bits of the 32-bit result to skip
// __zp($22) unsigned int mulu16_sel(__zp($12) unsigned int v1, __zp($14) unsigned int v2, __register(X) char select)
mulu16_sel: {
    .label __0 = $c
    .label __1 = $c
    .label v1 = $12
    .label v2 = $14
    .label return = $22
    .label return_1 = $12
    // mul16u(v1, v2)
    // [199] mul16u::a#0 = mulu16_sel::v1#5 -- vwuz1=vwuz2 
    lda.z v1
    sta.z mul16u.a
    lda.z v1+1
    sta.z mul16u.a+1
    // [200] mul16u::b#0 = mulu16_sel::v2#5
    // [201] call mul16u
    // [207] phi from mulu16_sel to mul16u [phi:mulu16_sel->mul16u]
    // [207] phi mul16u::a#6 = mul16u::a#0 [phi:mulu16_sel->mul16u#0] -- register_copy 
    // [207] phi mul16u::b#2 = mul16u::b#0 [phi:mulu16_sel->mul16u#1] -- register_copy 
    jsr mul16u
    // mul16u(v1, v2)
    // [202] mul16u::return#0 = mul16u::res#2
    // mulu16_sel::@1
    // [203] mulu16_sel::$0 = mul16u::return#0
    // mul16u(v1, v2)<<select
    // [204] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 -- vduz1=vduz1_rol_vbuxx 
    cpx #0
    beq !e+
  !:
    asl.z __1
    rol.z __1+1
    rol.z __1+2
    rol.z __1+3
    dex
    bne !-
  !e:
    // WORD1(mul16u(v1, v2)<<select)
    // [205] mulu16_sel::return#12 = word1  mulu16_sel::$1 -- vwuz1=_word1_vduz2 
    lda.z __1+2
    sta.z return
    lda.z __1+3
    sta.z return+1
    // mulu16_sel::@return
    // }
    // [206] return 
    rts
}
  // mul16u
// Perform binary multiplication of two unsigned 16-bit unsigned ints into a 32-bit unsigned long
// __zp($c) unsigned long mul16u(__zp($22) unsigned int a, __zp($14) unsigned int b)
mul16u: {
    .label a = $22
    .label b = $14
    .label return = $c
    .label mb = $1c
    .label res = $c
    // unsigned long mb = b
    // [208] mul16u::mb#0 = (unsigned long)mul16u::b#2 -- vduz1=_dword_vwuz2 
    lda.z b
    sta.z mb
    lda.z b+1
    sta.z mb+1
    lda #0
    sta.z mb+2
    sta.z mb+3
    // [209] phi from mul16u to mul16u::@1 [phi:mul16u->mul16u::@1]
    // [209] phi mul16u::mb#2 = mul16u::mb#0 [phi:mul16u->mul16u::@1#0] -- register_copy 
    // [209] phi mul16u::res#2 = 0 [phi:mul16u->mul16u::@1#1] -- vduz1=vduc1 
    sta.z res
    sta.z res+1
    lda #<0>>$10
    sta.z res+2
    lda #>0>>$10
    sta.z res+3
    // [209] phi mul16u::a#3 = mul16u::a#6 [phi:mul16u->mul16u::@1#2] -- register_copy 
    // mul16u::@1
  __b1:
    // while(a!=0)
    // [210] if(mul16u::a#3!=0) goto mul16u::@2 -- vwuz1_neq_0_then_la1 
    lda.z a
    ora.z a+1
    bne __b2
    // mul16u::@return
    // }
    // [211] return 
    rts
    // mul16u::@2
  __b2:
    // a&1
    // [212] mul16u::$1 = mul16u::a#3 & 1 -- vbuaa=vwuz1_band_vbuc1 
    lda #1
    and.z a
    // if( (a&1) != 0)
    // [213] if(mul16u::$1==0) goto mul16u::@3 -- vbuaa_eq_0_then_la1 
    cmp #0
    beq __b3
    // mul16u::@4
    // res = res + mb
    // [214] mul16u::res#1 = mul16u::res#2 + mul16u::mb#2 -- vduz1=vduz1_plus_vduz2 
    clc
    lda.z res
    adc.z mb
    sta.z res
    lda.z res+1
    adc.z mb+1
    sta.z res+1
    lda.z res+2
    adc.z mb+2
    sta.z res+2
    lda.z res+3
    adc.z mb+3
    sta.z res+3
    // [215] phi from mul16u::@2 mul16u::@4 to mul16u::@3 [phi:mul16u::@2/mul16u::@4->mul16u::@3]
    // [215] phi mul16u::res#6 = mul16u::res#2 [phi:mul16u::@2/mul16u::@4->mul16u::@3#0] -- register_copy 
    // mul16u::@3
  __b3:
    // a = a>>1
    // [216] mul16u::a#1 = mul16u::a#3 >> 1 -- vwuz1=vwuz1_ror_1 
    lsr.z a+1
    ror.z a
    // mb = mb<<1
    // [217] mul16u::mb#1 = mul16u::mb#2 << 1 -- vduz1=vduz1_rol_1 
    asl.z mb
    rol.z mb+1
    rol.z mb+2
    rol.z mb+3
    // [209] phi from mul16u::@3 to mul16u::@1 [phi:mul16u::@3->mul16u::@1]
    // [209] phi mul16u::mb#2 = mul16u::mb#1 [phi:mul16u::@3->mul16u::@1#0] -- register_copy 
    // [209] phi mul16u::res#2 = mul16u::res#6 [phi:mul16u::@3->mul16u::@1#1] -- register_copy 
    // [209] phi mul16u::a#3 = mul16u::a#1 [phi:mul16u::@3->mul16u::@1#2] -- register_copy 
    jmp __b1
}
  // File Data
.segment Data
  .align $100
  xsin: .fill 2*XSIN_SIZE, 0
.pc = $2000 "LOGO"
LOGO:
.var logoPic = LoadPicture("logo.png", List().add($444444, $808080, $000000, $ffffff))
    .for (var y=0; y<6	; y++)
        .for (var x=0;x<40; x++)
            .for(var cp=0; cp<8; cp++)
                .byte logoPic.getMulticolorByte(x,cp+y*8)


