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Merge branch 'fix-tests' into 'master'

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Fixed a single test

See merge request camelot/kickc!48
This commit is contained in:
Jesper Balman Gravgaard 2023-04-24 06:15:19 +00:00
commit 1142bcb008
3 changed files with 131 additions and 132 deletions
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19
src/test/ref/examples/cx16/cx16-rasterbars.asm
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@ -9,7 +9,6 @@
.segmentdef Data [startAfter="Code"] .segmentdef Data [startAfter="Code"]
.segment Basic .segment Basic
:BasicUpstart(__start) :BasicUpstart(__start)
.const VERA_DCSEL = 2 .const VERA_DCSEL = 2
.const VERA_LINE = 2 .const VERA_LINE = 2
.const isr_vsync = $314 .const isr_vsync = $314
@ -55,17 +54,17 @@
.label BRAM = 0 .label BRAM = 0
.label BROM = 1 .label BROM = 1
// The horizontal start // The horizontal start
.label hstart = $26 .label hstart = 6
// The horizontal stop // The horizontal stop
.label hstop = $27 .label hstop = 7
// The vertical start // The vertical start
.label vstart = $28 .label vstart = 8
// The vertical stop // The vertical stop
.label vstop = $29 .label vstop = 9
// The countdown // The countdown
.label cnt = $25 .label cnt = 5
// The sin idx // The sin idx
.label sin_idx = $2a .label sin_idx = $a
.segment Code .segment Code
__start: { __start: {
// __export volatile __address(0x00) unsigned char BRAM = 0 // __export volatile __address(0x00) unsigned char BRAM = 0
@ -97,8 +96,8 @@ __start: {
} }
// LINE Interrupt Routine // LINE Interrupt Routine
irq_line: { irq_line: {
.label idx = $24 .label idx = 4
.label bar = $22 .label bar = 2
// *VERA_CTRL |= VERA_DCSEL // *VERA_CTRL |= VERA_DCSEL
// Update the border // Update the border
lda #VERA_DCSEL lda #VERA_DCSEL
@ -253,7 +252,7 @@ memset: {
.const c = 0 .const c = 0
.label str = BARS .label str = BARS
.label end = str+num .label end = str+num
.label dst = $22 .label dst = 2
lda #<str lda #<str
sta.z dst sta.z dst
lda #>str lda #>str

204
src/test/ref/examples/cx16/cx16-rasterbars.log
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@ -49,6 +49,8 @@ Inlined call call bank_set_bram(memcpy_vram_bram::sbank_bram)
Inlined call call bank_set_bram(memcpy_vram_bram::sbank_bram) Inlined call call bank_set_bram(memcpy_vram_bram::sbank_bram)
Inlined call call bank_set_bram(memcpy_vram_bram::sbank_bram) Inlined call call bank_set_bram(memcpy_vram_bram::sbank_bram)
Inlined call call bank_set_bram(memcpy_vram_bram::bank) Inlined call call bank_set_bram(memcpy_vram_bram::bank)
Inlined call call bank_push_set_bram(memcpy_vram_bram_fast::sbank_bram)
Inlined call call bank_pull_bram
Inlined call call SEI Inlined call call SEI
Inlined call call CLI Inlined call call CLI
Inlined call call __init Inlined call call __init
@ -880,20 +882,20 @@ Complete equivalence classes
[ cnt ] [ cnt ]
[ sin_idx ] [ sin_idx ]
[ irq_line::bar#0 ] [ irq_line::bar#0 ]
Allocated zp[1]:34 [ irq_line::i2#2 irq_line::i2#1 ] Allocated zp[1]:2 [ irq_line::i2#2 irq_line::i2#1 ]
Allocated zp[1]:35 [ irq_line::i#2 irq_line::i#1 ] Allocated zp[1]:3 [ irq_line::i#2 irq_line::i#1 ]
Allocated zp[1]:36 [ irq_line::i1#2 irq_line::i1#1 ] Allocated zp[1]:4 [ irq_line::i1#2 irq_line::i1#1 ]
Allocated zp[2]:37 [ memset::dst#2 memset::dst#1 ] Allocated zp[2]:5 [ memset::dst#2 memset::dst#1 ]
Allocated zp[1]:39 [ irq_line::b#2 irq_line::b#1 ] Allocated zp[1]:7 [ irq_line::b#2 irq_line::b#1 ]
Allocated zp[1]:40 [ irq_line::l#2 irq_line::l#1 ] Allocated zp[1]:8 [ irq_line::l#2 irq_line::l#1 ]
Allocated zp[2]:41 [ irq_line::bar#0 ] Allocated zp[2]:9 [ irq_line::bar#0 ]
Allocated zp[1]:43 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] Allocated zp[1]:11 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
Allocated zp[1]:44 [ cnt ] Allocated zp[1]:12 [ cnt ]
Allocated zp[1]:45 [ hstart ] Allocated zp[1]:13 [ hstart ]
Allocated zp[1]:46 [ hstop ] Allocated zp[1]:14 [ hstop ]
Allocated zp[1]:47 [ vstart ] Allocated zp[1]:15 [ vstart ]
Allocated zp[1]:48 [ vstop ] Allocated zp[1]:16 [ vstop ]
Allocated zp[1]:49 [ sin_idx ] Allocated zp[1]:17 [ sin_idx ]
REGISTER UPLIFT POTENTIAL REGISTERS REGISTER UPLIFT POTENTIAL REGISTERS
Statement [1] BRAM = 0 [ ] ( [ ] { } ) always clobbers reg byte a Statement [1] BRAM = 0 [ ] ( [ ] { } ) always clobbers reg byte a
Statement [2] BROM = 4 [ ] ( [ ] { } ) always clobbers reg byte a Statement [2] BROM = 4 [ ] ( [ ] { } ) always clobbers reg byte a
@ -914,13 +916,13 @@ Statement [22] cnt = 2 [ hstart hstop vstart vstop sin_idx ] ( [ hstart hstop v
Statement [23] if(hstart>=(char)$140/4+1) goto irq_line::@1 [ hstart hstop vstart vstop sin_idx ] ( [ hstart hstop vstart vstop sin_idx ] { } ) always clobbers reg byte a Statement [23] if(hstart>=(char)$140/4+1) goto irq_line::@1 [ hstart hstop vstart vstop sin_idx ] ( [ hstart hstop vstart vstop sin_idx ] { } ) always clobbers reg byte a
Statement [34] *VERA_ISR = VERA_LINE [ ] ( [ ] { } ) always clobbers reg byte a Statement [34] *VERA_ISR = VERA_LINE [ ] ( [ ] { } ) always clobbers reg byte a
Statement [36] irq_line::bar#0 = BARS + SIN[irq_line::idx#2] [ irq_line::b#2 irq_line::idx#2 irq_line::bar#0 ] ( [ irq_line::b#2 irq_line::idx#2 irq_line::bar#0 ] { } ) always clobbers reg byte a Statement [36] irq_line::bar#0 = BARS + SIN[irq_line::idx#2] [ irq_line::b#2 irq_line::idx#2 irq_line::bar#0 ] ( [ irq_line::b#2 irq_line::idx#2 irq_line::bar#0 ] { } ) always clobbers reg byte a
Removing always clobbered register reg byte a as potential for zp[1]:39 [ irq_line::b#2 irq_line::b#1 ] Removing always clobbered register reg byte a as potential for zp[1]:7 [ irq_line::b#2 irq_line::b#1 ]
Removing always clobbered register reg byte a as potential for zp[1]:43 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] Removing always clobbered register reg byte a as potential for zp[1]:11 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
Statement [39] irq_line::idx#1 = irq_line::idx#2 + $d [ irq_line::b#2 irq_line::idx#1 ] ( [ irq_line::b#2 irq_line::idx#1 ] { } ) always clobbers reg byte a Statement [39] irq_line::idx#1 = irq_line::idx#2 + $d [ irq_line::b#2 irq_line::idx#1 ] ( [ irq_line::b#2 irq_line::idx#1 ] { } ) always clobbers reg byte a
Statement [41] irq_line::bar#0[irq_line::i2#2] = BAR[irq_line::i2#2] [ irq_line::b#2 irq_line::idx#2 irq_line::bar#0 irq_line::i2#2 ] ( [ irq_line::b#2 irq_line::idx#2 irq_line::bar#0 irq_line::i2#2 ] { } ) always clobbers reg byte a Statement [41] irq_line::bar#0[irq_line::i2#2] = BAR[irq_line::i2#2] [ irq_line::b#2 irq_line::idx#2 irq_line::bar#0 irq_line::i2#2 ] ( [ irq_line::b#2 irq_line::idx#2 irq_line::bar#0 irq_line::i2#2 ] { } ) always clobbers reg byte a
Removing always clobbered register reg byte a as potential for zp[1]:34 [ irq_line::i2#2 irq_line::i2#1 ] Removing always clobbered register reg byte a as potential for zp[1]:2 [ irq_line::i2#2 irq_line::i2#1 ]
Statement [43] *VERA_DC_BORDER = BARS[irq_line::l#2] [ hstart hstop vstart vstop cnt sin_idx irq_line::l#2 ] ( [ hstart hstop vstart vstop cnt sin_idx irq_line::l#2 ] { } ) always clobbers reg byte a Statement [43] *VERA_DC_BORDER = BARS[irq_line::l#2] [ hstart hstop vstart vstop cnt sin_idx irq_line::l#2 ] ( [ hstart hstop vstart vstop cnt sin_idx irq_line::l#2 ] { } ) always clobbers reg byte a
Removing always clobbered register reg byte a as potential for zp[1]:40 [ irq_line::l#2 irq_line::l#1 ] Removing always clobbered register reg byte a as potential for zp[1]:8 [ irq_line::l#2 irq_line::l#1 ]
Statement [46] *VERA_DC_BORDER = 0 [ hstart hstop vstart vstop cnt sin_idx irq_line::l#2 ] ( [ hstart hstop vstart vstop cnt sin_idx irq_line::l#2 ] { } ) always clobbers reg byte a Statement [46] *VERA_DC_BORDER = 0 [ hstart hstop vstart vstop cnt sin_idx irq_line::l#2 ] ( [ hstart hstop vstart vstop cnt sin_idx irq_line::l#2 ] { } ) always clobbers reg byte a
Statement [55] *KERNEL_IRQ = &irq_line [ ] ( main:10 [ ] { } ) always clobbers reg byte a Statement [55] *KERNEL_IRQ = &irq_line [ ] ( main:10 [ ] { } ) always clobbers reg byte a
Statement [56] *VERA_IEN = VERA_LINE [ ] ( main:10 [ ] { } ) always clobbers reg byte a Statement [56] *VERA_IEN = VERA_LINE [ ] ( main:10 [ ] { } ) always clobbers reg byte a
@ -955,71 +957,71 @@ Statement [56] *VERA_IEN = VERA_LINE [ ] ( main:10 [ ] { } ) always clobbers re
Statement [57] *VERA_IRQLINE_L = 5 [ ] ( main:10 [ ] { } ) always clobbers reg byte a Statement [57] *VERA_IRQLINE_L = 5 [ ] ( main:10 [ ] { } ) always clobbers reg byte a
Statement [62] if(memset::dst#2!=memset::end#0) goto memset::@2 [ memset::dst#2 ] ( memset:29 [ sin_idx memset::dst#2 ] { } ) always clobbers reg byte a Statement [62] if(memset::dst#2!=memset::end#0) goto memset::@2 [ memset::dst#2 ] ( memset:29 [ sin_idx memset::dst#2 ] { } ) always clobbers reg byte a
Statement [64] *memset::dst#2 = memset::c#0 [ memset::dst#2 ] ( memset:29 [ sin_idx memset::dst#2 ] { } ) always clobbers reg byte a reg byte y Statement [64] *memset::dst#2 = memset::c#0 [ memset::dst#2 ] ( memset:29 [ sin_idx memset::dst#2 ] { } ) always clobbers reg byte a reg byte y
Potential registers zp[1]:40 [ irq_line::l#2 irq_line::l#1 ] : zp[1]:40 , reg byte x , reg byte y , Potential registers zp[1]:8 [ irq_line::l#2 irq_line::l#1 ] : zp[1]:8 , reg byte x , reg byte y ,
Potential registers zp[1]:39 [ irq_line::b#2 irq_line::b#1 ] : zp[1]:39 , reg byte x , reg byte y , Potential registers zp[1]:7 [ irq_line::b#2 irq_line::b#1 ] : zp[1]:7 , reg byte x , reg byte y ,
Potential registers zp[1]:43 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] : zp[1]:43 , reg byte x , reg byte y , Potential registers zp[1]:11 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] : zp[1]:11 , reg byte x , reg byte y ,
Potential registers zp[1]:34 [ irq_line::i2#2 irq_line::i2#1 ] : zp[1]:34 , reg byte x , reg byte y , Potential registers zp[1]:2 [ irq_line::i2#2 irq_line::i2#1 ] : zp[1]:2 , reg byte x , reg byte y ,
Potential registers zp[1]:35 [ irq_line::i#2 irq_line::i#1 ] : zp[1]:35 , reg byte a , reg byte x , reg byte y , Potential registers zp[1]:3 [ irq_line::i#2 irq_line::i#1 ] : zp[1]:3 , reg byte a , reg byte x , reg byte y ,
Potential registers zp[1]:36 [ irq_line::i1#2 irq_line::i1#1 ] : zp[1]:36 , reg byte a , reg byte x , reg byte y , Potential registers zp[1]:4 [ irq_line::i1#2 irq_line::i1#1 ] : zp[1]:4 , reg byte a , reg byte x , reg byte y ,
Potential registers zp[2]:37 [ memset::dst#2 memset::dst#1 ] : zp[2]:37 , Potential registers zp[2]:5 [ memset::dst#2 memset::dst#1 ] : zp[2]:5 ,
Potential registers zp[1]:0 [ BRAM ] : zp[1]:0 , Potential registers zp[1]:0 [ BRAM ] : zp[1]:0 ,
Potential registers zp[1]:1 [ BROM ] : zp[1]:1 , Potential registers zp[1]:1 [ BROM ] : zp[1]:1 ,
Potential registers zp[1]:45 [ hstart ] : zp[1]:45 , Potential registers zp[1]:13 [ hstart ] : zp[1]:13 ,
Potential registers zp[1]:46 [ hstop ] : zp[1]:46 , Potential registers zp[1]:14 [ hstop ] : zp[1]:14 ,
Potential registers zp[1]:47 [ vstart ] : zp[1]:47 , Potential registers zp[1]:15 [ vstart ] : zp[1]:15 ,
Potential registers zp[1]:48 [ vstop ] : zp[1]:48 , Potential registers zp[1]:16 [ vstop ] : zp[1]:16 ,
Potential registers zp[1]:44 [ cnt ] : zp[1]:44 , Potential registers zp[1]:12 [ cnt ] : zp[1]:12 ,
Potential registers zp[1]:49 [ sin_idx ] : zp[1]:49 , Potential registers zp[1]:17 [ sin_idx ] : zp[1]:17 ,
Potential registers zp[2]:41 [ irq_line::bar#0 ] : zp[2]:41 , Potential registers zp[2]:9 [ irq_line::bar#0 ] : zp[2]:9 ,
REGISTER UPLIFT SCOPES REGISTER UPLIFT SCOPES
Uplift Scope [irq_line] 370.33: zp[1]:34 [ irq_line::i2#2 irq_line::i2#1 ] 353.5: zp[1]:35 [ irq_line::i#2 irq_line::i#1 ] 353.5: zp[1]:36 [ irq_line::i1#2 irq_line::i1#1 ] 26.12: zp[1]:39 [ irq_line::b#2 irq_line::b#1 ] 26: zp[1]:40 [ irq_line::l#2 irq_line::l#1 ] 22.4: zp[2]:41 [ irq_line::bar#0 ] 18: zp[1]:43 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] Uplift Scope [irq_line] 370.33: zp[1]:2 [ irq_line::i2#2 irq_line::i2#1 ] 353.5: zp[1]:3 [ irq_line::i#2 irq_line::i#1 ] 353.5: zp[1]:4 [ irq_line::i1#2 irq_line::i1#1 ] 26.12: zp[1]:7 [ irq_line::b#2 irq_line::b#1 ] 26: zp[1]:8 [ irq_line::l#2 irq_line::l#1 ] 22.4: zp[2]:9 [ irq_line::bar#0 ] 18: zp[1]:11 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
Uplift Scope [memset] 336.67: zp[2]:37 [ memset::dst#2 memset::dst#1 ] Uplift Scope [memset] 336.67: zp[2]:5 [ memset::dst#2 memset::dst#1 ]
Uplift Scope [] 20: zp[1]:0 [ BRAM ] 20: zp[1]:1 [ BROM ] 0.53: zp[1]:44 [ cnt ] 0.45: zp[1]:45 [ hstart ] 0.35: zp[1]:46 [ hstop ] 0.33: zp[1]:47 [ vstart ] 0.32: zp[1]:48 [ vstop ] 0.28: zp[1]:49 [ sin_idx ] Uplift Scope [] 20: zp[1]:0 [ BRAM ] 20: zp[1]:1 [ BROM ] 0.53: zp[1]:12 [ cnt ] 0.45: zp[1]:13 [ hstart ] 0.35: zp[1]:14 [ hstop ] 0.33: zp[1]:15 [ vstart ] 0.32: zp[1]:16 [ vstop ] 0.28: zp[1]:17 [ sin_idx ]
Uplift Scope [MOS6522_VIA] Uplift Scope [MOS6522_VIA]
Uplift Scope [RADIX] Uplift Scope [RADIX]
Uplift Scope [VERA_SPRITE] Uplift Scope [VERA_SPRITE]
Uplift Scope [main] Uplift Scope [main]
Uplift Scope [__start] Uplift Scope [__start]
Uplifting [irq_line] best 8211 combination reg byte y [ irq_line::i2#2 irq_line::i2#1 ] reg byte a [ irq_line::i#2 irq_line::i#1 ] reg byte a [ irq_line::i1#2 irq_line::i1#1 ] reg byte x [ irq_line::b#2 irq_line::b#1 ] zp[1]:40 [ irq_line::l#2 irq_line::l#1 ] zp[2]:41 [ irq_line::bar#0 ] zp[1]:43 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] Uplifting [irq_line] best 8211 combination reg byte y [ irq_line::i2#2 irq_line::i2#1 ] reg byte a [ irq_line::i#2 irq_line::i#1 ] reg byte a [ irq_line::i1#2 irq_line::i1#1 ] reg byte x [ irq_line::b#2 irq_line::b#1 ] zp[1]:8 [ irq_line::l#2 irq_line::l#1 ] zp[2]:9 [ irq_line::bar#0 ] zp[1]:11 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
Limited combination testing to 100 combinations of 1296 possible. Limited combination testing to 100 combinations of 1296 possible.
Uplifting [memset] best 8211 combination zp[2]:37 [ memset::dst#2 memset::dst#1 ] Uplifting [memset] best 8211 combination zp[2]:5 [ memset::dst#2 memset::dst#1 ]
Uplifting [] best 8211 combination zp[1]:0 [ BRAM ] zp[1]:1 [ BROM ] zp[1]:44 [ cnt ] zp[1]:45 [ hstart ] zp[1]:46 [ hstop ] zp[1]:47 [ vstart ] zp[1]:48 [ vstop ] zp[1]:49 [ sin_idx ] Uplifting [] best 8211 combination zp[1]:0 [ BRAM ] zp[1]:1 [ BROM ] zp[1]:12 [ cnt ] zp[1]:13 [ hstart ] zp[1]:14 [ hstop ] zp[1]:15 [ vstart ] zp[1]:16 [ vstop ] zp[1]:17 [ sin_idx ]
Uplifting [MOS6522_VIA] best 8211 combination Uplifting [MOS6522_VIA] best 8211 combination
Uplifting [RADIX] best 8211 combination Uplifting [RADIX] best 8211 combination
Uplifting [VERA_SPRITE] best 8211 combination Uplifting [VERA_SPRITE] best 8211 combination
Uplifting [main] best 8211 combination Uplifting [main] best 8211 combination
Uplifting [__start] best 8211 combination Uplifting [__start] best 8211 combination
Attempting to uplift remaining variables inzp[1]:40 [ irq_line::l#2 irq_line::l#1 ] Attempting to uplift remaining variables inzp[1]:8 [ irq_line::l#2 irq_line::l#1 ]
Uplifting [irq_line] best 8091 combination reg byte x [ irq_line::l#2 irq_line::l#1 ] Uplifting [irq_line] best 8091 combination reg byte x [ irq_line::l#2 irq_line::l#1 ]
Attempting to uplift remaining variables inzp[1]:0 [ BRAM ] Attempting to uplift remaining variables inzp[1]:0 [ BRAM ]
Uplifting [] best 8091 combination zp[1]:0 [ BRAM ] Uplifting [] best 8091 combination zp[1]:0 [ BRAM ]
Attempting to uplift remaining variables inzp[1]:1 [ BROM ] Attempting to uplift remaining variables inzp[1]:1 [ BROM ]
Uplifting [] best 8091 combination zp[1]:1 [ BROM ] Uplifting [] best 8091 combination zp[1]:1 [ BROM ]
Attempting to uplift remaining variables inzp[1]:43 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] Attempting to uplift remaining variables inzp[1]:11 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
Uplifting [irq_line] best 8091 combination zp[1]:43 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] Uplifting [irq_line] best 8091 combination zp[1]:11 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
Attempting to uplift remaining variables inzp[1]:44 [ cnt ] Attempting to uplift remaining variables inzp[1]:12 [ cnt ]
Uplifting [] best 8091 combination zp[1]:44 [ cnt ] Uplifting [] best 8091 combination zp[1]:12 [ cnt ]
Attempting to uplift remaining variables inzp[1]:45 [ hstart ] Attempting to uplift remaining variables inzp[1]:13 [ hstart ]
Uplifting [] best 8091 combination zp[1]:45 [ hstart ] Uplifting [] best 8091 combination zp[1]:13 [ hstart ]
Attempting to uplift remaining variables inzp[1]:46 [ hstop ] Attempting to uplift remaining variables inzp[1]:14 [ hstop ]
Uplifting [] best 8091 combination zp[1]:46 [ hstop ] Uplifting [] best 8091 combination zp[1]:14 [ hstop ]
Attempting to uplift remaining variables inzp[1]:47 [ vstart ] Attempting to uplift remaining variables inzp[1]:15 [ vstart ]
Uplifting [] best 8091 combination zp[1]:47 [ vstart ] Uplifting [] best 8091 combination zp[1]:15 [ vstart ]
Attempting to uplift remaining variables inzp[1]:48 [ vstop ] Attempting to uplift remaining variables inzp[1]:16 [ vstop ]
Uplifting [] best 8091 combination zp[1]:48 [ vstop ] Uplifting [] best 8091 combination zp[1]:16 [ vstop ]
Attempting to uplift remaining variables inzp[1]:49 [ sin_idx ] Attempting to uplift remaining variables inzp[1]:17 [ sin_idx ]
Uplifting [] best 8091 combination zp[1]:49 [ sin_idx ] Uplifting [] best 8091 combination zp[1]:17 [ sin_idx ]
Coalescing zero page register [ zp[2]:41 [ irq_line::bar#0 ] ] with [ zp[2]:37 [ memset::dst#2 memset::dst#1 ] ] Coalescing zero page register [ zp[2]:9 [ irq_line::bar#0 ] ] with [ zp[2]:5 [ memset::dst#2 memset::dst#1 ] ]
Allocated (was zp[2]:41) zp[2]:34 [ irq_line::bar#0 memset::dst#2 memset::dst#1 ] Allocated (was zp[2]:9) zp[2]:2 [ irq_line::bar#0 memset::dst#2 memset::dst#1 ]
Allocated (was zp[1]:43) zp[1]:36 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] Allocated (was zp[1]:11) zp[1]:4 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
Allocated (was zp[1]:44) zp[1]:37 [ cnt ] Allocated (was zp[1]:12) zp[1]:5 [ cnt ]
Allocated (was zp[1]:45) zp[1]:38 [ hstart ] Allocated (was zp[1]:13) zp[1]:6 [ hstart ]
Allocated (was zp[1]:46) zp[1]:39 [ hstop ] Allocated (was zp[1]:14) zp[1]:7 [ hstop ]
Allocated (was zp[1]:47) zp[1]:40 [ vstart ] Allocated (was zp[1]:15) zp[1]:8 [ vstart ]
Allocated (was zp[1]:48) zp[1]:41 [ vstop ] Allocated (was zp[1]:16) zp[1]:9 [ vstop ]
Allocated (was zp[1]:49) zp[1]:42 [ sin_idx ] Allocated (was zp[1]:17) zp[1]:10 [ sin_idx ]
ASSEMBLER BEFORE OPTIMIZATION ASSEMBLER BEFORE OPTIMIZATION
// File Comments // File Comments
@ -1035,7 +1037,6 @@ ASSEMBLER BEFORE OPTIMIZATION
.segmentdef Data [startAfter="Code"] .segmentdef Data [startAfter="Code"]
.segment Basic .segment Basic
:BasicUpstart(__start) :BasicUpstart(__start)
// Global Constants & labels // Global Constants & labels
.const VERA_DCSEL = 2 .const VERA_DCSEL = 2
.const VERA_LINE = 2 .const VERA_LINE = 2
@ -1082,17 +1083,17 @@ ASSEMBLER BEFORE OPTIMIZATION
.label BRAM = 0 .label BRAM = 0
.label BROM = 1 .label BROM = 1
// The horizontal start // The horizontal start
.label hstart = $26 .label hstart = 6
// The horizontal stop // The horizontal stop
.label hstop = $27 .label hstop = 7
// The vertical start // The vertical start
.label vstart = $28 .label vstart = 8
// The vertical stop // The vertical stop
.label vstop = $29 .label vstop = 9
// The countdown // The countdown
.label cnt = $25 .label cnt = 5
// The sin idx // The sin idx
.label sin_idx = $2a .label sin_idx = $a
.segment Code .segment Code
// __start // __start
__start: { __start: {
@ -1141,8 +1142,8 @@ __start: {
// irq_line // irq_line
// LINE Interrupt Routine // LINE Interrupt Routine
irq_line: { irq_line: {
.label idx = $24 .label idx = 4
.label bar = $22 .label bar = 2
// interrupt(isr_rom_min_cx16_entry) -- isr_rom_min_cx16_entry // interrupt(isr_rom_min_cx16_entry) -- isr_rom_min_cx16_entry
// [12] *VERA_CTRL = *VERA_CTRL | VERA_DCSEL -- _deref_pbuc1=_deref_pbuc1_bor_vbuc2 // [12] *VERA_CTRL = *VERA_CTRL | VERA_DCSEL -- _deref_pbuc1=_deref_pbuc1_bor_vbuc2
// Update the border // Update the border
@ -1400,7 +1401,7 @@ memset: {
.const c = 0 .const c = 0
.label str = BARS .label str = BARS
.label end = str+num .label end = str+num
.label dst = $22 .label dst = 2
// [61] phi from memset to memset::@1 [phi:memset->memset::@1] // [61] phi from memset to memset::@1 [phi:memset->memset::@1]
__b1_from_memset: __b1_from_memset:
// [61] phi memset::dst#2 = (char *)memset::str#0 [phi:memset->memset::@1#0] -- pbuz1=pbuc1 // [61] phi memset::dst#2 = (char *)memset::str#0 [phi:memset->memset::@1#0] -- pbuz1=pbuc1
@ -1545,15 +1546,15 @@ __constant char * const VERA_IRQLINE_L = (char *) 40744
__constant char * const VERA_ISR = (char *) 40743 __constant char * const VERA_ISR = (char *) 40743
__constant const char VERA_LINE = 2 __constant const char VERA_LINE = 2
void __start() void __start()
__loadstore volatile char cnt // zp[1]:37 0.5263157894736842 __loadstore volatile char cnt // zp[1]:5 0.5263157894736842
__loadstore volatile char hstart // zp[1]:38 0.4545454545454546 __loadstore volatile char hstart // zp[1]:6 0.4545454545454546
__loadstore volatile char hstop // zp[1]:39 0.34782608695652173 __loadstore volatile char hstop // zp[1]:7 0.34782608695652173
__interrupt(rom_min_cx16) void irq_line() __interrupt(rom_min_cx16) void irq_line()
char irq_line::b char irq_line::b
char irq_line::b#1 // reg byte x 22.0 char irq_line::b#1 // reg byte x 22.0
char irq_line::b#2 // reg byte x 4.125 char irq_line::b#2 // reg byte x 4.125
char *irq_line::bar char *irq_line::bar
char *irq_line::bar#0 // bar zp[2]:34 22.4 char *irq_line::bar#0 // bar zp[2]:2 22.4
char irq_line::i char irq_line::i
char irq_line::i#1 // reg byte a 202.0 char irq_line::i#1 // reg byte a 202.0
char irq_line::i#2 // reg byte a 151.5 char irq_line::i#2 // reg byte a 151.5
@ -1564,9 +1565,9 @@ char irq_line::i2
char irq_line::i2#1 // reg byte y 202.0 char irq_line::i2#1 // reg byte y 202.0
char irq_line::i2#2 // reg byte y 168.33333333333331 char irq_line::i2#2 // reg byte y 168.33333333333331
char irq_line::idx char irq_line::idx
char irq_line::idx#0 // idx zp[1]:36 2.0 char irq_line::idx#0 // idx zp[1]:4 2.0
char irq_line::idx#1 // idx zp[1]:36 11.0 char irq_line::idx#1 // idx zp[1]:4 11.0
char irq_line::idx#2 // idx zp[1]:36 5.0 char irq_line::idx#2 // idx zp[1]:4 5.0
char irq_line::l char irq_line::l
char irq_line::l#1 // reg byte x 22.0 char irq_line::l#1 // reg byte x 22.0
char irq_line::l#2 // reg byte x 4.0 char irq_line::l#2 // reg byte x 4.0
@ -1577,8 +1578,8 @@ void * memset(void *str , char c , unsigned int num)
char memset::c char memset::c
__constant char memset::c#0 = 0 // c __constant char memset::c#0 = 0 // c
char *memset::dst char *memset::dst
char *memset::dst#1 // dst zp[2]:34 202.0 char *memset::dst#1 // dst zp[2]:2 202.0
char *memset::dst#2 // dst zp[2]:34 134.66666666666666 char *memset::dst#2 // dst zp[2]:2 134.66666666666666
char *memset::end char *memset::end
__constant char *memset::end#0 = (char *)memset::str#0+memset::num#0 // end __constant char *memset::end#0 = (char *)memset::str#0+memset::num#0 // end
unsigned int memset::num unsigned int memset::num
@ -1586,25 +1587,25 @@ __constant unsigned int memset::num#0 = $e6*SIZEOF_CHAR // num
void *memset::return void *memset::return
void *memset::str void *memset::str
__constant void *memset::str#0 = (void *)BARS // str __constant void *memset::str#0 = (void *)BARS // str
__loadstore volatile char sin_idx // zp[1]:42 0.27586206896551724 __loadstore volatile char sin_idx // zp[1]:10 0.27586206896551724
__loadstore volatile char vstart // zp[1]:40 0.3333333333333333 __loadstore volatile char vstart // zp[1]:8 0.3333333333333333
__loadstore volatile char vstop // zp[1]:41 0.32 __loadstore volatile char vstop // zp[1]:9 0.32
reg byte x [ irq_line::l#2 irq_line::l#1 ] reg byte x [ irq_line::l#2 irq_line::l#1 ]
reg byte x [ irq_line::b#2 irq_line::b#1 ] reg byte x [ irq_line::b#2 irq_line::b#1 ]
zp[1]:36 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] zp[1]:4 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
reg byte y [ irq_line::i2#2 irq_line::i2#1 ] reg byte y [ irq_line::i2#2 irq_line::i2#1 ]
reg byte a [ irq_line::i#2 irq_line::i#1 ] reg byte a [ irq_line::i#2 irq_line::i#1 ]
reg byte a [ irq_line::i1#2 irq_line::i1#1 ] reg byte a [ irq_line::i1#2 irq_line::i1#1 ]
zp[1]:0 [ BRAM ] zp[1]:0 [ BRAM ]
zp[1]:1 [ BROM ] zp[1]:1 [ BROM ]
zp[1]:38 [ hstart ] zp[1]:6 [ hstart ]
zp[1]:39 [ hstop ] zp[1]:7 [ hstop ]
zp[1]:40 [ vstart ] zp[1]:8 [ vstart ]
zp[1]:41 [ vstop ] zp[1]:9 [ vstop ]
zp[1]:37 [ cnt ] zp[1]:5 [ cnt ]
zp[1]:42 [ sin_idx ] zp[1]:10 [ sin_idx ]
zp[2]:34 [ irq_line::bar#0 memset::dst#2 memset::dst#1 ] zp[2]:2 [ irq_line::bar#0 memset::dst#2 memset::dst#1 ]
FINAL ASSEMBLER FINAL ASSEMBLER
@ -1623,7 +1624,6 @@ Score: 5794
.segmentdef Data [startAfter="Code"] .segmentdef Data [startAfter="Code"]
.segment Basic .segment Basic
:BasicUpstart(__start) :BasicUpstart(__start)
// Global Constants & labels // Global Constants & labels
.const VERA_DCSEL = 2 .const VERA_DCSEL = 2
.const VERA_LINE = 2 .const VERA_LINE = 2
@ -1670,17 +1670,17 @@ Score: 5794
.label BRAM = 0 .label BRAM = 0
.label BROM = 1 .label BROM = 1
// The horizontal start // The horizontal start
.label hstart = $26 .label hstart = 6
// The horizontal stop // The horizontal stop
.label hstop = $27 .label hstop = 7
// The vertical start // The vertical start
.label vstart = $28 .label vstart = 8
// The vertical stop // The vertical stop
.label vstop = $29 .label vstop = 9
// The countdown // The countdown
.label cnt = $25 .label cnt = 5
// The sin idx // The sin idx
.label sin_idx = $2a .label sin_idx = $a
.segment Code .segment Code
// __start // __start
__start: { __start: {
@ -1729,8 +1729,8 @@ __start: {
// irq_line // irq_line
// LINE Interrupt Routine // LINE Interrupt Routine
irq_line: { irq_line: {
.label idx = $24 .label idx = 4
.label bar = $22 .label bar = 2
// interrupt(isr_rom_min_cx16_entry) -- isr_rom_min_cx16_entry // interrupt(isr_rom_min_cx16_entry) -- isr_rom_min_cx16_entry
// *VERA_CTRL |= VERA_DCSEL // *VERA_CTRL |= VERA_DCSEL
// [12] *VERA_CTRL = *VERA_CTRL | VERA_DCSEL -- _deref_pbuc1=_deref_pbuc1_bor_vbuc2 // [12] *VERA_CTRL = *VERA_CTRL | VERA_DCSEL -- _deref_pbuc1=_deref_pbuc1_bor_vbuc2
@ -1978,7 +1978,7 @@ memset: {
.const c = 0 .const c = 0
.label str = BARS .label str = BARS
.label end = str+num .label end = str+num
.label dst = $22 .label dst = 2
// [61] phi from memset to memset::@1 [phi:memset->memset::@1] // [61] phi from memset to memset::@1 [phi:memset->memset::@1]
// [61] phi memset::dst#2 = (char *)memset::str#0 [phi:memset->memset::@1#0] -- pbuz1=pbuc1 // [61] phi memset::dst#2 = (char *)memset::str#0 [phi:memset->memset::@1#0] -- pbuz1=pbuc1
lda #<str lda #<str

40
src/test/ref/examples/cx16/cx16-rasterbars.sym
View File

@ -22,15 +22,15 @@ __constant char * const VERA_IRQLINE_L = (char *) 40744
__constant char * const VERA_ISR = (char *) 40743 __constant char * const VERA_ISR = (char *) 40743
__constant const char VERA_LINE = 2 __constant const char VERA_LINE = 2
void __start() void __start()
__loadstore volatile char cnt // zp[1]:37 0.5263157894736842 __loadstore volatile char cnt // zp[1]:5 0.5263157894736842
__loadstore volatile char hstart // zp[1]:38 0.4545454545454546 __loadstore volatile char hstart // zp[1]:6 0.4545454545454546
__loadstore volatile char hstop // zp[1]:39 0.34782608695652173 __loadstore volatile char hstop // zp[1]:7 0.34782608695652173
__interrupt(rom_min_cx16) void irq_line() __interrupt(rom_min_cx16) void irq_line()
char irq_line::b char irq_line::b
char irq_line::b#1 // reg byte x 22.0 char irq_line::b#1 // reg byte x 22.0
char irq_line::b#2 // reg byte x 4.125 char irq_line::b#2 // reg byte x 4.125
char *irq_line::bar char *irq_line::bar
char *irq_line::bar#0 // bar zp[2]:34 22.4 char *irq_line::bar#0 // bar zp[2]:2 22.4
char irq_line::i char irq_line::i
char irq_line::i#1 // reg byte a 202.0 char irq_line::i#1 // reg byte a 202.0
char irq_line::i#2 // reg byte a 151.5 char irq_line::i#2 // reg byte a 151.5
@ -41,9 +41,9 @@ char irq_line::i2
char irq_line::i2#1 // reg byte y 202.0 char irq_line::i2#1 // reg byte y 202.0
char irq_line::i2#2 // reg byte y 168.33333333333331 char irq_line::i2#2 // reg byte y 168.33333333333331
char irq_line::idx char irq_line::idx
char irq_line::idx#0 // idx zp[1]:36 2.0 char irq_line::idx#0 // idx zp[1]:4 2.0
char irq_line::idx#1 // idx zp[1]:36 11.0 char irq_line::idx#1 // idx zp[1]:4 11.0
char irq_line::idx#2 // idx zp[1]:36 5.0 char irq_line::idx#2 // idx zp[1]:4 5.0
char irq_line::l char irq_line::l
char irq_line::l#1 // reg byte x 22.0 char irq_line::l#1 // reg byte x 22.0
char irq_line::l#2 // reg byte x 4.0 char irq_line::l#2 // reg byte x 4.0
@ -54,8 +54,8 @@ void * memset(void *str , char c , unsigned int num)
char memset::c char memset::c
__constant char memset::c#0 = 0 // c __constant char memset::c#0 = 0 // c
char *memset::dst char *memset::dst
char *memset::dst#1 // dst zp[2]:34 202.0 char *memset::dst#1 // dst zp[2]:2 202.0
char *memset::dst#2 // dst zp[2]:34 134.66666666666666 char *memset::dst#2 // dst zp[2]:2 134.66666666666666
char *memset::end char *memset::end
__constant char *memset::end#0 = (char *)memset::str#0+memset::num#0 // end __constant char *memset::end#0 = (char *)memset::str#0+memset::num#0 // end
unsigned int memset::num unsigned int memset::num
@ -63,22 +63,22 @@ __constant unsigned int memset::num#0 = $e6*SIZEOF_CHAR // num
void *memset::return void *memset::return
void *memset::str void *memset::str
__constant void *memset::str#0 = (void *)BARS // str __constant void *memset::str#0 = (void *)BARS // str
__loadstore volatile char sin_idx // zp[1]:42 0.27586206896551724 __loadstore volatile char sin_idx // zp[1]:10 0.27586206896551724
__loadstore volatile char vstart // zp[1]:40 0.3333333333333333 __loadstore volatile char vstart // zp[1]:8 0.3333333333333333
__loadstore volatile char vstop // zp[1]:41 0.32 __loadstore volatile char vstop // zp[1]:9 0.32
reg byte x [ irq_line::l#2 irq_line::l#1 ] reg byte x [ irq_line::l#2 irq_line::l#1 ]
reg byte x [ irq_line::b#2 irq_line::b#1 ] reg byte x [ irq_line::b#2 irq_line::b#1 ]
zp[1]:36 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ] zp[1]:4 [ irq_line::idx#2 irq_line::idx#1 irq_line::idx#0 ]
reg byte y [ irq_line::i2#2 irq_line::i2#1 ] reg byte y [ irq_line::i2#2 irq_line::i2#1 ]
reg byte a [ irq_line::i#2 irq_line::i#1 ] reg byte a [ irq_line::i#2 irq_line::i#1 ]
reg byte a [ irq_line::i1#2 irq_line::i1#1 ] reg byte a [ irq_line::i1#2 irq_line::i1#1 ]
zp[1]:0 [ BRAM ] zp[1]:0 [ BRAM ]
zp[1]:1 [ BROM ] zp[1]:1 [ BROM ]
zp[1]:38 [ hstart ] zp[1]:6 [ hstart ]
zp[1]:39 [ hstop ] zp[1]:7 [ hstop ]
zp[1]:40 [ vstart ] zp[1]:8 [ vstart ]
zp[1]:41 [ vstop ] zp[1]:9 [ vstop ]
zp[1]:37 [ cnt ] zp[1]:5 [ cnt ]
zp[1]:42 [ sin_idx ] zp[1]:10 [ sin_idx ]
zp[2]:34 [ irq_line::bar#0 memset::dst#2 memset::dst#1 ] zp[2]:2 [ irq_line::bar#0 memset::dst#2 memset::dst#1 ]