Merge branch '766-add-huc6280-tst-instruction-addressing-modes' into 'master'

Finished implementing support for huc6280 transfer instructions with abs,abs,abs addressing mode. Closes #766 See merge request camelot/kickc!17
2024-06-03 07:29:37 +00:00 · 2022-02-13 11:05:44 +00:00 · 2022-02-13 11:05:44 +00:00 · 230776a2da
commit 230776a2da
parent 49abe6cdb7 dec47ab811
28 changed files with 286 additions and 53 deletions
--- a/pom.xml
+++ b/pom.xml
@ -79,7 +79,7 @@
        <dependency>
            <groupId>cml.kickass</groupId>
            <artifactId>kickassembler</artifactId>
-            <version>5.24-65ce02.c</version>
+            <version>5.24-65ce02.d</version>
        </dependency>
        <dependency>
            <groupId>dk.camelot64.kickass.xexplugin</groupId>
--- a/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.jar
+++ b/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.jar
--- a/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.jar.md5
+++ b/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.jar.md5
@ -0,0 +1 @@
+cb690b10bc82ebb353b1fa5da4666a19
--- a/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.jar.sha1
+++ b/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.jar.sha1
@ -0,0 +1 @@
+3fb23c3fe4301d638376ca2278944a742283c2a1
--- a/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.pom
+++ b/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.pom
@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project xsi:schemaLocation="http://maven.apache.org/POM/4.0.0 https://maven.apache.org/xsd/maven-4.0.0.xsd" xmlns="http://maven.apache.org/POM/4.0.0"
+    xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <modelVersion>4.0.0</modelVersion>
+  <groupId>cml.kickass</groupId>
+  <artifactId>kickassembler</artifactId>
+  <version>5.24-65ce02.d</version>
+  <description>POM was created from install:install-file</description>
+</project>
--- a/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.pom.md5
+++ b/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.pom.md5
@ -0,0 +1 @@
+f151e7a277d990765a349ec73f89d777
--- a/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.pom.sha1
+++ b/repo/cml/kickass/kickassembler/5.24-65ce02.d/kickassembler-5.24-65ce02.d.pom.sha1
@ -0,0 +1 @@
+b57b209be7e7daafb81ab23b99e18da764a390ac
--- a/repo/cml/kickass/kickassembler/maven-metadata.xml
+++ b/repo/cml/kickass/kickassembler/maven-metadata.xml
@ -3,7 +3,7 @@
  <groupId>cml.kickass</groupId>
  <artifactId>kickassembler</artifactId>
  <versioning>
-    <release>5.24-65ce02.c</release>
+    <release>5.24-65ce02.d</release>
    <versions>
      <version>4.19</version>
      <version>5.7</version>
@ -30,7 +30,8 @@
      <version>5.24-65ce02.a</version>
      <version>5.24-65ce02.b</version>
      <version>5.24-65ce02.c</version>
+      <version>5.24-65ce02.d</version>
    </versions>
-    <lastUpdated>20220212060216</lastUpdated>
+    <lastUpdated>20220213103243</lastUpdated>
  </versioning>
 </metadata>
--- a/repo/cml/kickass/kickassembler/maven-metadata.xml.md5
+++ b/repo/cml/kickass/kickassembler/maven-metadata.xml.md5
@ -1 +1 @@
-24290bfa1613ef56b57bc4c4e670423c
+566035322d1120a899902e225415aea4
--- a/repo/cml/kickass/kickassembler/maven-metadata.xml.sha1
+++ b/repo/cml/kickass/kickassembler/maven-metadata.xml.sha1
@ -1 +1 @@
-e3cf25389c4e30b070712f29c599f6e090746e7c
+9d02e7968040c29f57b25cc02f1ae3c143e7b773
--- a/src/main/antlr4/dk/camelot64/kickc/parser/KickCLexer.g4
+++ b/src/main/antlr4/dk/camelot64/kickc/parser/KickCLexer.g4
@ -165,7 +165,7 @@ ASM_MNEMONIC:
    'tsb' | 'wai' | 'cle' | 'see' | 'tsy' | 'lbpl'| 'inz' | 'tys' | 'lbmi'| 'dez' | 'neg' | 'asr' | 'taz' | 'lbvc'| 'tab' | 'map' | 'rtn' | 'lbsr'| 'tza' |
    'lbvs'| 'tba' | 'lbra'| 'lbcc'| 'ldz' | 'lbcs'| 'cpz' | 'dew' | 'asw' | 'lbne'| 'phz' | 'inw' | 'row' | 'lbeq'| 'phw' | 'plz' | 'eom' | 'adcq'| 'andq'|
    'aslq'| 'asrq'| 'bitq'| 'cpq' | 'deq' | 'eorq'| 'inq' | 'ldq' | 'lsrq'| 'orq' | 'rolq'| 'rorq'| 'sbcq'| 'stq' | 'sxy' | 'st0' | 'st1' | 'st2' | 'say' |
-    'tma' | 'bsr' | 'tam' | 'csl' | 'cla' | 'clx' | 'cly' | 'csh' | 'set' | 'tst'
+    'tma' | 'bsr' | 'tam' | 'csl' | 'cla' | 'clx' | 'cly' | 'csh' | 'set' | 'tst' | 'tia' | 'tdd' | 'tin' | 'tii'
    ;

 ASM_IMM : '#' ;
--- a/src/main/antlr4/dk/camelot64/kickc/parser/KickCParser.g4
+++ b/src/main/antlr4/dk/camelot64/kickc/parser/KickCParser.g4
@ -298,7 +298,8 @@ asmBytes
 asmParamMode
    : asmExpr #asmModeAbs
    | ASM_IMM asmExpr #asmModeImm
-    | asmExpr ASM_COMMA asmExpr #asmModeAbsXY
+    | asmExpr ASM_COMMA asmExpr #asmModeAbs2
+    | asmExpr ASM_COMMA asmExpr ASM_COMMA asmExpr #asmModeAbs3
    | ASM_PAR_BEGIN asmExpr ASM_PAR_END ASM_COMMA ASM_NAME #asmModeIndIdxXY
    | ASM_PAR_BEGIN ASM_PAR_BEGIN asmExpr ASM_PAR_END ASM_PAR_END ASM_COMMA ASM_NAME #asmModeIndLongIdxXY
    | ASM_PAR_BEGIN asmExpr ASM_COMMA ASM_NAME ASM_PAR_END ASM_COMMA ASM_NAME #asmModeSPIndIdx
--- a/src/main/java/dk/camelot64/cpufamily6502/CpuAddressingMode.java
+++ b/src/main/java/dk/camelot64/cpufamily6502/CpuAddressingMode.java
@ -216,7 +216,13 @@ public enum CpuAddressingMode {
    * #imm,abs,x Immediate, absolute,x <br>
    * IMMEDIATE ADDRESSING, ABSOLUTE — Two parameters, one immediate the other an absolute address. Only used by HUC6280 TST.
    */
-   IABX("#imm,abs,x", "%i #%p,%q,x", 3);
+   IABX("#imm,abs,x", "%i #%p,%q,x", 3),
+
+   /**
+    * abs,abs,abs Absolute, Absolute, Absolute <br>
+    * ABSOLUTE *3 — Three absolute address parameters. Used by HUC6280 transfer instructions `tia` `tdd`, `tin`, `tii`.
+    */
+   ABS3("abs,abs,abs", "%i %p,%q,%r", 6);

   /** The short name of the addressing mode. */
   private String name;
@ -255,10 +261,11 @@ public enum CpuAddressingMode {
    *
    * @param mnemnonic The opcode mnemonic
    * @param operand The operand value. Null if addressing mode is Implied/A/None
-    * @param operand2 The second operand value (only used for addressing mode Zeropage Test Relative)
+    * @param operand2 The second operand value (used for addressing modes with 2+ parameters)
+    * @param operand3 The second operand value (used for addressing modes with 3+ parameters)
    * @return The printed ASM code for the instruction
    */
-   public String getAsm(String mnemnonic, String operand, String operand2) {
+   public String getAsm(String mnemnonic, String operand, String operand2, String operand3) {
      String replaced = template.replace("%i", mnemnonic);
      if(operand != null) {
         replaced = replaced.replace("%p", operand);
@ -266,6 +273,9 @@ public enum CpuAddressingMode {
      if(operand2 != null) {
         replaced = replaced.replace("%q", operand2);
      }
+      if(operand3 != null) {
+         replaced = replaced.replace("%r", operand3);
+      }
      return replaced;
   }

--- a/src/main/java/dk/camelot64/cpufamily6502/CpuOpcode.java
+++ b/src/main/java/dk/camelot64/cpufamily6502/CpuOpcode.java
@ -94,8 +94,8 @@ public class CpuOpcode {
    * @param operand2 The second operand value (only used for addressing mode Zeropage Test Relative)
    * @return The printed ASM code for the instruction
    */
-   public String getAsm(String operand, String operand2) {
-      return addressingMode.getAsm(mnemonic, operand, operand2);
+   public String getAsm(String operand, String operand2, String operand3) {
+      return addressingMode.getAsm(mnemonic, operand, operand2, operand3);
   }

   /**
--- a/src/main/java/dk/camelot64/cpufamily6502/cpus/CpuHuc6280.java
+++ b/src/main/java/dk/camelot64/cpufamily6502/cpus/CpuHuc6280.java
@ -18,18 +18,6 @@ public class CpuHuc6280 extends Cpu65xx {

    public CpuHuc6280() {
        super(NAME, Cpu65C02.INSTANCE, false);
-
-        // The following instructions are not supported yet:
-        // TST #imm, zp
-        // TST #imm, zp,x
-        // TST #imm, abs
-        // TST #imm, abs,x
-        // TII SHSL,DHDL, LHLL
-        // TIN SHSL,DHDL, LHLL
-        // TDD SHSL,DHDL, LHLL
-        // TIA SHSL,DHDL, LHLL
-        // TAI SHSL,DHDL, LHLL
-
        addOpcode(0x02,"sxy", CpuAddressingMode.NON,3,"XY");
        addOpcode(0x03,"st0", CpuAddressingMode.IMM,4,"");
        addOpcode(0x13,"st1", CpuAddressingMode.IMM,4,"");
@ -49,6 +37,10 @@ public class CpuHuc6280 extends Cpu65xx {
        addOpcode(0x93,"tst", CpuAddressingMode.IAB,8,"vnz");
        addOpcode(0xA3,"tst", CpuAddressingMode.IZPX,7,"vnz");
        addOpcode(0xB3,"tst", CpuAddressingMode.IABX,8,"vnz");
+        addOpcode(0xE3,"tia", CpuAddressingMode.ABS3,71,"");
+        addOpcode(0xC3,"tdd", CpuAddressingMode.ABS3,71,"");
+        addOpcode(0xD3,"tin", CpuAddressingMode.ABS3,71,"");
+        addOpcode(0x73,"tii", CpuAddressingMode.ABS3,71,"");
    }

 }
--- a/src/main/java/dk/camelot64/kickc/asm/AsmInstruction.java
+++ b/src/main/java/dk/camelot64/kickc/asm/AsmInstruction.java
@ -13,13 +13,17 @@ public class AsmInstruction extends AsmLine {
   /** The ASM opcode parameter. Null if the opcode addressing mode is Implied/A/None {@link CpuAddressingMode#NON} - eg. DEX */
   private String operand1;

-   /** The second ASM opcode parameter. Null if not used. Only used for addressing mode Zeropage Test Relative  {@link CpuAddressingMode#REZ} - eg. BBR0 $12,label */
+   /** The second ASM opcode parameter. Null if not used. Used for addressing modes with 2+ parameters such as {@link CpuAddressingMode#REZ} - eg. `BBR0 $12,label` */
   private String operand2;

-   public AsmInstruction(CpuOpcode cpuOpcode, String operand1, String operand2) {
+   /** The third ASM opcode parameter. Null if not used. Used for addressing modes with 3+ parameters such as {@link CpuAddressingMode#ABS3} - eg. `tia src,dest,cnt` */
+   private String operand3;
+
+   public AsmInstruction(CpuOpcode cpuOpcode, String operand1, String operand2, String operand3) {
      this.cpuOpcode = cpuOpcode;
      this.operand1 = operand1;
      this.operand2 = operand2;
+      this.operand3 = operand3;
   }

   public String getOperand1() {
@ -38,6 +42,14 @@ public class AsmInstruction extends AsmLine {
      this.operand2 = operand2;
   }

+   public String getOperand3() {
+      return operand3;
+   }
+
+   public void setOperand3(String operand3) {
+      this.operand3 = operand3;
+   }
+
   public CpuOpcode getCpuOpcode() {
      return cpuOpcode;
   }
@ -58,7 +70,7 @@ public class AsmInstruction extends AsmLine {

   @Override
   public String getAsm() {
-      return cpuOpcode.getAsm(operand1, operand2);
+      return cpuOpcode.getAsm(operand1, operand2, operand3);
   }

   @Override
@ -103,6 +115,4 @@ public class AsmInstruction extends AsmLine {

   }

-
-
-   }
+}
--- a/src/main/java/dk/camelot64/kickc/asm/AsmProgram.java
+++ b/src/main/java/dk/camelot64/kickc/asm/AsmProgram.java
@ -148,7 +148,7 @@ public class AsmProgram {

   public AsmInstruction addInstruction(String mnemonic, CpuAddressingMode addressingMode, String operand1, boolean isOperandZp) {
      CpuOpcode cpuOpcode = targetCpu.getCpu65xx().getOpcode(mnemonic, addressingMode, isOperandZp);
-      AsmInstruction asmInstruction = new AsmInstruction(cpuOpcode, operand1, null);
+      AsmInstruction asmInstruction = new AsmInstruction(cpuOpcode, operand1, null, null);
      addLine(asmInstruction);
      return asmInstruction;
   }
--- a/src/main/java/dk/camelot64/kickc/fragment/AsmFragmentInstance.java
+++ b/src/main/java/dk/camelot64/kickc/fragment/AsmFragmentInstance.java
@ -264,7 +264,7 @@ public class AsmFragmentInstance {
         KickCParser.AsmParamModeContext paramModeCtx = ctx.asmParamMode();
         AsmInstruction instruction;
         if(paramModeCtx == null) {
-            instruction = createAsmInstruction(ctx, null, null, CpuAddressingMode.NON);
+            instruction = createAsmInstruction(ctx, null, null, null, CpuAddressingMode.NON);
         } else {
            instruction = (AsmInstruction) this.visit(paramModeCtx);
         }
@ -278,46 +278,52 @@ public class AsmFragmentInstance {

      @Override
      public Object visitAsmModeAbs(KickCParser.AsmModeAbsContext ctx) {
-         return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.ABS);
+         return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.ABS);
      }

      @Override
      public Object visitAsmModeImm(KickCParser.AsmModeImmContext ctx) {
-         return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.IMM);
+         return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.IMM);
      }

      @Override
      public Object visitAsmModeImmAndAbs(KickCParser.AsmModeImmAndAbsContext ctx) {
-         return createAsmInstruction(ctx, ctx.asmExpr(0), ctx.asmExpr(1), CpuAddressingMode.IAB);
+         return createAsmInstruction(ctx, ctx.asmExpr(0), ctx.asmExpr(1), null, CpuAddressingMode.IAB);
      }

      @Override
      public Object visitAsmModeImmAndAbsX(KickCParser.AsmModeImmAndAbsXContext ctx) {
-         return createAsmInstruction(ctx, ctx.asmExpr(0), ctx.asmExpr(1), CpuAddressingMode.IABX);
+         return createAsmInstruction(ctx, ctx.asmExpr(0), ctx.asmExpr(1), null, CpuAddressingMode.IABX);
      }

      @Override
-      public Object visitAsmModeAbsXY(KickCParser.AsmModeAbsXYContext ctx) {
+      public Object visitAsmModeAbs2(KickCParser.AsmModeAbs2Context ctx) {
         final KickCParser.AsmExprContext indexCtx = ctx.asmExpr(1);
         if(indexCtx instanceof KickCParser.AsmExprLabelContext) {
            final String xy = ((KickCParser.AsmExprLabelContext) indexCtx).ASM_NAME().getText();
            if(xy.equals("x")) {
-               return createAsmInstruction(ctx, ctx.asmExpr(0), null, CpuAddressingMode.ABX);
+               return createAsmInstruction(ctx, ctx.asmExpr(0), null, null, CpuAddressingMode.ABX);
            } else if(xy.equals("y")) {
-               return createAsmInstruction(ctx, ctx.asmExpr(0), null, CpuAddressingMode.ABY);
+               return createAsmInstruction(ctx, ctx.asmExpr(0), null, null, CpuAddressingMode.ABY);
            }
         }
         // Test Relative Addressing Mode (2 parameters)
-         return createAsmInstruction(ctx, ctx.asmExpr(0), ctx.asmExpr(1), CpuAddressingMode.REZ);
+         return createAsmInstruction(ctx, ctx.asmExpr(0), ctx.asmExpr(1), null, CpuAddressingMode.REZ);
+      }
+
+      @Override
+      public Object visitAsmModeAbs3(KickCParser.AsmModeAbs3Context ctx) {
+         // Abs*3 Addressing Mode (3 parameters)
+         return createAsmInstruction(ctx, ctx.asmExpr(0), ctx.asmExpr(1), ctx.asmExpr(2), CpuAddressingMode.ABS3);
      }

      @Override
      public Object visitAsmModeIndIdxXY(KickCParser.AsmModeIndIdxXYContext ctx) {
         String xy = ctx.ASM_NAME().getText();
         if(xy.equals("y")) {
-            return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.IZY);
+            return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.IZY);
         } else if(xy.equals("z")) {
-            return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.IZZ);
+            return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.IZZ);
         } else {
            throw new RuntimeException("Unknown addressing mode " + ctx.getText());
         }
@ -327,7 +333,7 @@ public class AsmFragmentInstance {
      public Object visitAsmModeIndLongIdxXY(KickCParser.AsmModeIndLongIdxXYContext ctx) {
         String xy = ctx.ASM_NAME().getText();
         if(xy.equals("z")) {
-            return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.LIZ);
+            return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.LIZ);
         } else {
            throw new RuntimeException("Unknown addressing mode " + ctx.getText());
         }
@ -337,7 +343,7 @@ public class AsmFragmentInstance {
      public Object visitAsmModeIdxIndXY(KickCParser.AsmModeIdxIndXYContext ctx) {
         String xy = ctx.ASM_NAME().getText();
         if(xy.equals("x")) {
-            return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.IAX);
+            return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.IAX);
         } else {
            throw new RuntimeException("Unknown addressing mode " + ctx.getText());
         }
@ -348,7 +354,7 @@ public class AsmFragmentInstance {
         String sp = ctx.ASM_NAME(0).getText();
         String y = ctx.ASM_NAME(1).getText();
         if(sp.equals("sp") && y.equals("y")) {
-            return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.ISY);
+            return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.ISY);
         } else {
            throw new RuntimeException("Unknown addressing mode " + ctx.getText());
         }
@ -356,30 +362,33 @@ public class AsmFragmentInstance {

      @Override
      public Object visitAsmModeInd(KickCParser.AsmModeIndContext ctx) {
-         return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.IND);
+         return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.IND);
      }

      @Override
      public Object visitAsmModeIndLong(KickCParser.AsmModeIndLongContext ctx) {
-         return createAsmInstruction(ctx, ctx.asmExpr(), null, CpuAddressingMode.LIN);
+         return createAsmInstruction(ctx, ctx.asmExpr(), null, null, CpuAddressingMode.LIN);
      }

      private AsmInstruction createAsmInstruction(
            KickCParser.AsmParamModeContext paramModeCtx,
            KickCParser.AsmExprContext operand1Ctx,
            KickCParser.AsmExprContext operand2Ctx,
+            KickCParser.AsmExprContext operand3Ctx,
            CpuAddressingMode addressingMode) {
-         return createAsmInstruction((KickCParser.AsmInstructionContext) paramModeCtx.getParent(), operand1Ctx, operand2Ctx, addressingMode);
+         return createAsmInstruction((KickCParser.AsmInstructionContext) paramModeCtx.getParent(), operand1Ctx, operand2Ctx, operand3Ctx, addressingMode);
      }

      private AsmInstruction createAsmInstruction(
            KickCParser.AsmInstructionContext instructionCtx,
            KickCParser.AsmExprContext operand1Ctx,
            KickCParser.AsmExprContext operand2Ctx,
+            KickCParser.AsmExprContext operand3Ctx,
            CpuAddressingMode addressingMode) {
         String mnemonic = instructionCtx.ASM_MNEMONIC().getSymbol().getText();
         AsmParameter param1 = operand1Ctx == null ? null : (AsmParameter) this.visit(operand1Ctx);
         AsmParameter param2 = operand2Ctx == null ? null : (AsmParameter) this.visit(operand2Ctx);
+         AsmParameter param3 = operand3Ctx == null ? null : (AsmParameter) this.visit(operand3Ctx);

         // Convert to ZP-addressing mode if possible

@ -398,10 +407,13 @@ public class AsmFragmentInstance {

         String operand1 = param1 == null ? null : param1.getParam();
         String operand2 = param2 == null ? null : param2.getParam();
+         String operand3 = param3 == null ? null : param3.getParam();
         if(cpuOpcode == null) {
-            throw new CompileError("Error in " + name + ".asm line " + instructionCtx.getStart().getLine() + " - Instruction type not supported  " + addressingMode.getAsm(mnemonic, operand1, operand2) + " by CPU " + this.fragmentInstance.fragmentTemplate.getTargetCpu().getName());
+            throw new CompileError("Error in " + name + ".asm line " + instructionCtx.getStart().getLine() + " - Instruction type not supported  " + addressingMode.getAsm(mnemonic, operand1, operand2, operand3) + " by CPU " + this.fragmentInstance.fragmentTemplate.getTargetCpu().getName());
         }
-         return new AsmInstruction(cpuOpcode, operand1, operand2);
+
+
+         return new AsmInstruction(cpuOpcode, operand1, operand2, operand3);
      }

      @Override
--- a/src/main/java/dk/camelot64/kickc/passes/Pass5AddMainRts.java
+++ b/src/main/java/dk/camelot64/kickc/passes/Pass5AddMainRts.java
@ -55,7 +55,7 @@ public class Pass5AddMainRts extends Pass5AsmOptimization {
   }

   private void addRts(ListIterator<AsmLine> lineIterator) {
-      lineIterator.add(new AsmInstruction(getAsmProgram().getTargetCpu().getCpu65xx().getOpcode("rts", CpuAddressingMode.NON, false), null, null));
+      lineIterator.add(new AsmInstruction(getAsmProgram().getTargetCpu().getCpu65xx().getOpcode("rts", CpuAddressingMode.NON, false), null, null, null));
      getLog().append("Adding RTS to root block ");
   }

--- a/src/main/java/dk/camelot64/kickc/passes/Pass5FixLongBranches.java
+++ b/src/main/java/dk/camelot64/kickc/passes/Pass5FixLongBranches.java
@ -147,7 +147,7 @@ public class Pass5FixLongBranches extends Pass5AsmOptimization {
               String newLabel = AsmFormat.asmFix("!" + branchDest);
               asmInstruction.setOperandJumpTarget(newLabel + "+");
               CpuOpcode jmpOpcode = getAsmProgram().getTargetCpu().getCpu65xx().getOpcode("jmp", CpuAddressingMode.ABS, false);
-               AsmInstruction jmpInstruction = new AsmInstruction(jmpOpcode, branchDest, null);
+               AsmInstruction jmpInstruction = new AsmInstruction(jmpOpcode, branchDest, null, null);
               asmChunk.addLineAfter(asmInstruction, jmpInstruction);
               asmChunk.addLineAfter(jmpInstruction, new AsmLabel(newLabel));
               return true;
--- a/src/main/repo/mvn-repo-install-kickass.sh
+++ b/src/main/repo/mvn-repo-install-kickass.sh
@ -4,7 +4,7 @@
 cp ./repo/cml/kickass/kickassembler/maven-metadata.xml ./repo/cml/kickass/kickassembler/maven-metadata-local.xml

 # mvn install:install-file -Dmaven.repo.local=./repo/ -Dfile=/Applications/KickAssembler/KickAss.jar -DgroupId=cml.kickass -DartifactId=kickassembler -Dpackaging=jar -DgeneratePom=true -DcreateChecksum=true -Dversion=5.16
-mvn install:install-file -Dmaven.repo.local=./repo/ -Dfile=/Users/jespergravgaard/c64/kickassembler65ce02/out/KickAss65CE02.jar -DgroupId=cml.kickass -DartifactId=kickassembler -Dpackaging=jar -DgeneratePom=true -DcreateChecksum=true -Dversion=5.24-65ce02.c
+mvn install:install-file -Dmaven.repo.local=./repo/ -Dfile=/Users/jespergravgaard/c64/kickassembler65ce02/out/KickAss65CE02.jar -DgroupId=cml.kickass -DartifactId=kickassembler -Dpackaging=jar -DgeneratePom=true -DcreateChecksum=true -Dversion=5.24-65ce02.d

 # Finalize by making the local metadata official
 pushd ./repo/cml/kickass/kickassembler
--- a/src/test/java/dk/camelot64/cpufamily6502/TestCpuFamilyKickAssCompatibility.java
+++ b/src/test/java/dk/camelot64/cpufamily6502/TestCpuFamilyKickAssCompatibility.java
@ -145,6 +145,7 @@ public class TestCpuFamilyKickAssCompatibility {
      map.put(CpuAddressingMode.IAB, Collections.singletonList(_65xxArgType.immediateAndAbsolute));
      map.put(CpuAddressingMode.IZPX, Collections.singletonList(_65xxArgType.immediateAndZeropageX));
      map.put(CpuAddressingMode.IABX, Collections.singletonList(_65xxArgType.immediateAndAbsoluteX));
+      map.put(CpuAddressingMode.ABS3, Collections.singletonList(_65xxArgType.absoluteAbsoluteAbsolute));
      return map;
   }

--- a/src/test/java/dk/camelot64/kickc/test/TestProgramsFast.java
+++ b/src/test/java/dk/camelot64/kickc/test/TestProgramsFast.java
@ -575,6 +575,11 @@ public class TestProgramsFast extends TestPrograms {
   //   compileAndCompare("library-constructor-0.c");
   //}

+   @Test
+   public void testCpuHuc6280Transfer() throws IOException {
+      compileAndCompare("cpu-huc6280-transfer.c");
+   }
+
   @Test
   public void testCpuHuc6280Tst() throws IOException {
      compileAndCompare("cpu-huc6280-tst.c");
--- a/src/test/kc/cpu-huc6280-transfer.c
+++ b/src/test/kc/cpu-huc6280-transfer.c
@ -0,0 +1,14 @@
+// Tests the HUC6280 instructions
+
+#pragma cpu(huc6280)
+
+void main() {
+    char * const SCREEN = (char*)0x0400;
+    asm {
+    tia 1, 2, 3
+    tdd $1000,$2000,$0800
+    tii $1000+4*8,$2000+4*8,$0800+4*8
+    tin SCREEN,$2000,40*24
+    rts
+    }
+}
--- a/src/test/ref/cpu-huc6280-transfer.asm
+++ b/src/test/ref/cpu-huc6280-transfer.asm
@ -0,0 +1,21 @@
+// Tests the HUC6280 instructions
+.cpu _huc6280
+  // Commodore 64 PRG executable file
+.file [name="cpu-huc6280-transfer.prg", type="prg", segments="Program"]
+.segmentdef Program [segments="Basic, Code, Data"]
+.segmentdef Basic [start=$0801]
+.segmentdef Code [start=$80d]
+.segmentdef Data [startAfter="Code"]
+.segment Basic
+:BasicUpstart(main)
+.segment Code
+main: {
+    .label SCREEN = $400
+    // asm
+    tia 1,2,3
+    tdd $1000,$2000,$800
+    tii $1000+4*8,$2000+4*8,$800+4*8
+    tin SCREEN,$2000,$28*$18
+    rts
+    // }
+}
--- a/src/test/ref/cpu-huc6280-transfer.cfg
+++ b/src/test/ref/cpu-huc6280-transfer.cfg
@ -0,0 +1,8 @@
+
+void main()
+main: scope:[main]  from
+  asm { tia1,2,3 tdd$1000,$2000,$0800 tii$1000+4*8,$2000+4*8,$0800+4*8 tinSCREEN,$2000,40*24 rts  }
+  to:main::@return
+main::@return: scope:[main]  from main
+  [1] return 
+  to:@return
--- a/src/test/ref/cpu-huc6280-transfer.log
+++ b/src/test/ref/cpu-huc6280-transfer.log
@ -0,0 +1,142 @@
+
+CONTROL FLOW GRAPH SSA
+
+void main()
+main: scope:[main]  from __start
+  asm { tia1,2,3 tdd$1000,$2000,$0800 tii$1000+4*8,$2000+4*8,$0800+4*8 tinSCREEN,$2000,40*24 rts  }
+  to:main::@return
+main::@return: scope:[main]  from main
+  return 
+  to:@return
+
+void __start()
+__start: scope:[__start]  from
+  call main
+  to:__start::@1
+__start::@1: scope:[__start]  from __start
+  to:__start::@return
+__start::@return: scope:[__start]  from __start::@1
+  return 
+  to:@return
+
+SYMBOL TABLE SSA
+void __start()
+void main()
+__constant char * const main::SCREEN = (char *)$400
+
+Simplifying constant pointer cast (char *) 1024
+Successful SSA optimization PassNCastSimplification
+Removing unused procedure __start
+Removing unused procedure block __start
+Removing unused procedure block __start::@1
+Removing unused procedure block __start::@return
+Successful SSA optimization PassNEliminateEmptyStart
+CALL GRAPH
+
+Created 0 initial phi equivalence classes
+Coalesced down to 0 phi equivalence classes
+
+FINAL CONTROL FLOW GRAPH
+
+void main()
+main: scope:[main]  from
+  asm { tia1,2,3 tdd$1000,$2000,$0800 tii$1000+4*8,$2000+4*8,$0800+4*8 tinSCREEN,$2000,40*24 rts  }
+  to:main::@return
+main::@return: scope:[main]  from main
+  [1] return 
+  to:@return
+
+
+VARIABLE REGISTER WEIGHTS
+void main()
+
+Initial phi equivalence classes
+Complete equivalence classes
+REGISTER UPLIFT POTENTIAL REGISTERS
+
+REGISTER UPLIFT SCOPES
+Uplift Scope [main] 
+Uplift Scope [] 
+
+Uplifting [main] best 299 combination 
+Uplifting [] best 299 combination 
+
+ASSEMBLER BEFORE OPTIMIZATION
+  // File Comments
+// Tests the HUC6280 instructions
+  // Upstart
+.cpu _huc6280
+  // Commodore 64 PRG executable file
+.file [name="cpu-huc6280-transfer.prg", type="prg", segments="Program"]
+.segmentdef Program [segments="Basic, Code, Data"]
+.segmentdef Basic [start=$0801]
+.segmentdef Code [start=$80d]
+.segmentdef Data [startAfter="Code"]
+.segment Basic
+:BasicUpstart(main)
+  // Global Constants & labels
+.segment Code
+  // main
+main: {
+    .label SCREEN = $400
+    // asm { tia1,2,3 tdd$1000,$2000,$0800 tii$1000+4*8,$2000+4*8,$0800+4*8 tinSCREEN,$2000,40*24 rts  }
+    tia 1,2,3
+    tdd $1000,$2000,$800
+    tii $1000+4*8,$2000+4*8,$800+4*8
+    tin SCREEN,$2000,$28*$18
+    rts
+    jmp __breturn
+    // main::@return
+  __breturn:
+    // [1] return 
+    rts
+}
+  // File Data
+
+ASSEMBLER OPTIMIZATIONS
+Removing instruction jmp __breturn
+Succesful ASM optimization Pass5NextJumpElimination
+Removing instruction __breturn:
+Succesful ASM optimization Pass5UnusedLabelElimination
+Removing unreachable instruction rts
+Succesful ASM optimization Pass5UnreachableCodeElimination
+
+FINAL SYMBOL TABLE
+void main()
+__constant char * const main::SCREEN = (char *) 1024
+
+
+
+FINAL ASSEMBLER
+Score: 290
+
+  // File Comments
+// Tests the HUC6280 instructions
+  // Upstart
+.cpu _huc6280
+  // Commodore 64 PRG executable file
+.file [name="cpu-huc6280-transfer.prg", type="prg", segments="Program"]
+.segmentdef Program [segments="Basic, Code, Data"]
+.segmentdef Basic [start=$0801]
+.segmentdef Code [start=$80d]
+.segmentdef Data [startAfter="Code"]
+.segment Basic
+:BasicUpstart(main)
+  // Global Constants & labels
+.segment Code
+  // main
+main: {
+    .label SCREEN = $400
+    // asm
+    // asm { tia1,2,3 tdd$1000,$2000,$0800 tii$1000+4*8,$2000+4*8,$0800+4*8 tinSCREEN,$2000,40*24 rts  }
+    tia 1,2,3
+    tdd $1000,$2000,$800
+    tii $1000+4*8,$2000+4*8,$800+4*8
+    tin SCREEN,$2000,$28*$18
+    rts
+    // main::@return
+    // }
+    // [1] return 
+}
+  // File Data
+
--- a/src/test/ref/cpu-huc6280-transfer.sym
+++ b/src/test/ref/cpu-huc6280-transfer.sym
@ -0,0 +1,3 @@
+void main()
+__constant char * const main::SCREEN = (char *) 1024
+