|
|
|
@ -90,7 +90,7 @@ sin16s_gen2::@5: scope:[sin16s_gen2] from sin16s_gen2::@4
|
|
|
|
|
sin16s_gen2::offs#1 = phi( sin16s_gen2::@4/sin16s_gen2::offs#2 )
|
|
|
|
|
mul16s::return#5 = phi( sin16s_gen2::@4/mul16s::return#0 )
|
|
|
|
|
sin16s_gen2::$6 = mul16s::return#5
|
|
|
|
|
sin16s_gen2::$7 = > sin16s_gen2::$6
|
|
|
|
|
sin16s_gen2::$7 = _word1_ sin16s_gen2::$6
|
|
|
|
|
sin16s_gen2::$10 = (signed word)sin16s_gen2::$7
|
|
|
|
|
sin16s_gen2::$8 = sin16s_gen2::offs#1 + sin16s_gen2::$10
|
|
|
|
|
*sin16s_gen2::sintab#2 = sin16s_gen2::$8
|
|
|
|
@ -130,7 +130,7 @@ sin16s::@2: scope:[sin16s] from sin16s::@1 sin16s::@5
|
|
|
|
|
sin16s::isUpper#7 = phi( sin16s::@1/sin16s::isUpper#8, sin16s::@5/sin16s::isUpper#9 )
|
|
|
|
|
sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
|
|
|
|
|
sin16s::$4 = sin16s::x#6 << 3
|
|
|
|
|
sin16s::$5 = > sin16s::$4
|
|
|
|
|
sin16s::$5 = _word1_ sin16s::$4
|
|
|
|
|
sin16s::x1#0 = sin16s::$5
|
|
|
|
|
mulu16_sel::v1#0 = sin16s::x1#0
|
|
|
|
|
mulu16_sel::v2#0 = sin16s::x1#0
|
|
|
|
@ -241,7 +241,7 @@ mulu16_sel::@1: scope:[mulu16_sel] from mulu16_sel
|
|
|
|
|
mul16u::return#4 = phi( mulu16_sel/mul16u::return#0 )
|
|
|
|
|
mulu16_sel::$0 = mul16u::return#4
|
|
|
|
|
mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
|
|
|
|
|
mulu16_sel::$2 = > mulu16_sel::$1
|
|
|
|
|
mulu16_sel::$2 = _word1_ mulu16_sel::$1
|
|
|
|
|
mulu16_sel::return#5 = mulu16_sel::$2
|
|
|
|
|
to:mulu16_sel::@return
|
|
|
|
|
mulu16_sel::@return: scope:[mulu16_sel] from mulu16_sel::@1
|
|
|
|
@ -334,7 +334,7 @@ div32u16u: scope:[div32u16u] from sin16s_gen2
|
|
|
|
|
rem16u#24 = phi( sin16s_gen2/rem16u#22 )
|
|
|
|
|
div32u16u::divisor#1 = phi( sin16s_gen2/div32u16u::divisor#0 )
|
|
|
|
|
div32u16u::dividend#1 = phi( sin16s_gen2/div32u16u::dividend#0 )
|
|
|
|
|
div32u16u::$0 = > div32u16u::dividend#1
|
|
|
|
|
div32u16u::$0 = _word1_ div32u16u::dividend#1
|
|
|
|
|
divr16u::dividend#1 = div32u16u::$0
|
|
|
|
|
divr16u::divisor#0 = div32u16u::divisor#1
|
|
|
|
|
divr16u::rem#3 = 0
|
|
|
|
@ -349,7 +349,7 @@ div32u16u::@1: scope:[div32u16u] from div32u16u
|
|
|
|
|
div32u16u::$1 = divr16u::return#5
|
|
|
|
|
rem16u#4 = rem16u#15
|
|
|
|
|
div32u16u::quotient_hi#0 = div32u16u::$1
|
|
|
|
|
div32u16u::$2 = < div32u16u::dividend#2
|
|
|
|
|
div32u16u::$2 = _word0_ div32u16u::dividend#2
|
|
|
|
|
divr16u::dividend#2 = div32u16u::$2
|
|
|
|
|
divr16u::divisor#1 = div32u16u::divisor#2
|
|
|
|
|
divr16u::rem#4 = rem16u#4
|
|
|
|
@ -454,11 +454,11 @@ mul16s::@3: scope:[mul16s] from mul16s::@5
|
|
|
|
|
mul16s::a#7 = phi( mul16s::@5/mul16s::a#4 )
|
|
|
|
|
mul16s::b#5 = phi( mul16s::@5/mul16s::b#6 )
|
|
|
|
|
mul16s::m#3 = phi( mul16s::@5/mul16s::m#0 )
|
|
|
|
|
mul16s::$6 = > mul16s::m#3
|
|
|
|
|
mul16s::$6 = _word1_ mul16s::m#3
|
|
|
|
|
mul16s::$13 = (word)mul16s::b#5
|
|
|
|
|
mul16s::$7 = mul16s::$6 - mul16s::$13
|
|
|
|
|
mul16s::$11 = mul16s::$7
|
|
|
|
|
mul16s::m#1 = mul16s::m#3 hi= mul16s::$11
|
|
|
|
|
mul16s::m#1 = mul16s::m#3 word1= mul16s::$11
|
|
|
|
|
to:mul16s::@1
|
|
|
|
|
mul16s::@2: scope:[mul16s] from mul16s::@1 mul16s::@4
|
|
|
|
|
mul16s::m#4 = phi( mul16s::@1/mul16s::m#6, mul16s::@4/mul16s::m#2 )
|
|
|
|
@ -467,11 +467,11 @@ mul16s::@2: scope:[mul16s] from mul16s::@1 mul16s::@4
|
|
|
|
|
mul16s::@4: scope:[mul16s] from mul16s::@1
|
|
|
|
|
mul16s::a#5 = phi( mul16s::@1/mul16s::a#6 )
|
|
|
|
|
mul16s::m#5 = phi( mul16s::@1/mul16s::m#6 )
|
|
|
|
|
mul16s::$9 = > mul16s::m#5
|
|
|
|
|
mul16s::$9 = _word1_ mul16s::m#5
|
|
|
|
|
mul16s::$14 = (word)mul16s::a#5
|
|
|
|
|
mul16s::$10 = mul16s::$9 - mul16s::$14
|
|
|
|
|
mul16s::$12 = mul16s::$10
|
|
|
|
|
mul16s::m#2 = mul16s::m#5 hi= mul16s::$12
|
|
|
|
|
mul16s::m#2 = mul16s::m#5 word1= mul16s::$12
|
|
|
|
|
to:mul16s::@2
|
|
|
|
|
mul16s::@return: scope:[mul16s] from mul16s::@2
|
|
|
|
|
mul16s::return#6 = phi( mul16s::@2/mul16s::return#1 )
|
|
|
|
@ -760,7 +760,7 @@ main::@12: scope:[main] from main::@2
|
|
|
|
|
main::$5 = mul16s::return#7
|
|
|
|
|
main::xpos#0 = main::$5
|
|
|
|
|
main::$6 = main::xpos#0 << 4
|
|
|
|
|
main::$7 = > main::$6
|
|
|
|
|
main::$7 = _word1_ main::$6
|
|
|
|
|
main::$8 = $a0 + main::$7
|
|
|
|
|
main::x#0 = (word)main::$8
|
|
|
|
|
main::$20 = main::idx_y#3 * SIZEOF_SIGNED_WORD
|
|
|
|
@ -781,7 +781,7 @@ main::@13: scope:[main] from main::@12
|
|
|
|
|
main::$9 = mul16s::return#8
|
|
|
|
|
main::ypos#0 = main::$9
|
|
|
|
|
main::$10 = main::ypos#0 << 4
|
|
|
|
|
main::$11 = > main::$10
|
|
|
|
|
main::$11 = _word1_ main::$10
|
|
|
|
|
main::$12 = $64 + main::$11
|
|
|
|
|
main::y#0 = (word)main::$12
|
|
|
|
|
bitmap_plot::x#0 = main::x#1
|
|
|
|
@ -1237,7 +1237,7 @@ signed word main::sin_y
|
|
|
|
|
signed word main::sin_y#0
|
|
|
|
|
number~ main::toD0181_$0
|
|
|
|
|
number~ main::toD0181_$1
|
|
|
|
|
number~ main::toD0181_$2
|
|
|
|
|
byte~ main::toD0181_$2
|
|
|
|
|
byte~ main::toD0181_$3
|
|
|
|
|
number~ main::toD0181_$4
|
|
|
|
|
number~ main::toD0181_$5
|
|
|
|
@ -1686,7 +1686,6 @@ Adding number conversion cast (unumber) $3fff in main::toD0181_$0 = main::toD018
|
|
|
|
|
Adding number conversion cast (unumber) main::toD0181_$0 in main::toD0181_$0 = main::toD0181_$7 & (unumber)$3fff
|
|
|
|
|
Adding number conversion cast (unumber) 4 in main::toD0181_$1 = main::toD0181_$0 * 4
|
|
|
|
|
Adding number conversion cast (unumber) main::toD0181_$1 in main::toD0181_$1 = main::toD0181_$0 * (unumber)4
|
|
|
|
|
Adding number conversion cast (unumber) main::toD0181_$2 in main::toD0181_$2 = > main::toD0181_$1
|
|
|
|
|
Adding number conversion cast (unumber) 4 in main::toD0181_$4 = main::toD0181_$3 / 4
|
|
|
|
|
Adding number conversion cast (unumber) main::toD0181_$4 in main::toD0181_$4 = main::toD0181_$3 / (unumber)4
|
|
|
|
|
Adding number conversion cast (unumber) $f in main::toD0181_$5 = main::toD0181_$4 & $f
|
|
|
|
@ -1870,7 +1869,6 @@ Inferred type updated to byte in bitmap_clear::$1 = bitmap_clear::$0 + bitmap_cl
|
|
|
|
|
Inferred type updated to word in bitmap_plot::$0 = bitmap_plot::x#1 & $fff8
|
|
|
|
|
Inferred type updated to word in main::toD0181_$0 = main::toD0181_$7 & $3fff
|
|
|
|
|
Inferred type updated to word in main::toD0181_$1 = main::toD0181_$0 * 4
|
|
|
|
|
Inferred type updated to byte in main::toD0181_$2 = > main::toD0181_$1
|
|
|
|
|
Inferred type updated to byte in main::toD0181_$4 = main::toD0181_$3 / 4
|
|
|
|
|
Inferred type updated to byte in main::toD0181_$5 = main::toD0181_$4 & $f
|
|
|
|
|
Inferred type updated to byte in main::toD0181_$6 = main::toD0181_$2 | main::toD0181_$5
|
|
|
|
@ -2223,15 +2221,15 @@ Alias main::x#0 = main::$8
|
|
|
|
|
Alias main::y#0 = main::$12
|
|
|
|
|
Successful SSA optimization Pass2AliasElimination
|
|
|
|
|
Constant right-side identified [0] sin16s_gen2::ampl#0 = sin16s_gen2::max#0 - sin16s_gen2::min#0
|
|
|
|
|
Constant right-side identified [91] divr16u::dividend#1 = > div32u16u::dividend#0
|
|
|
|
|
Constant right-side identified [95] divr16u::dividend#2 = < div32u16u::dividend#0
|
|
|
|
|
Constant right-side identified [91] divr16u::dividend#1 = _word1_ div32u16u::dividend#0
|
|
|
|
|
Constant right-side identified [95] divr16u::dividend#2 = _word0_ div32u16u::dividend#0
|
|
|
|
|
Constant right-side identified [153] bitmap_clear::col#0 = bitmap_clear::fgcol#0 * $10
|
|
|
|
|
Constant right-side identified [179] main::toD0181_$0 = main::toD0181_$7 & $3fff
|
|
|
|
|
Constant right-side identified [182] main::toD0181_$3 = > (word)main::toD0181_gfx#0
|
|
|
|
|
Successful SSA optimization Pass2ConstantRValueConsolidation
|
|
|
|
|
Constant sin16s_gen2::ampl#0 = sin16s_gen2::max#0-sin16s_gen2::min#0
|
|
|
|
|
Constant divr16u::dividend#1 = >div32u16u::dividend#0
|
|
|
|
|
Constant divr16u::dividend#2 = <div32u16u::dividend#0
|
|
|
|
|
Constant divr16u::dividend#1 = _word1_div32u16u::dividend#0
|
|
|
|
|
Constant divr16u::dividend#2 = _word0_div32u16u::dividend#0
|
|
|
|
|
Constant bitmap_clear::col#0 = bitmap_clear::fgcol#0*$10
|
|
|
|
|
Constant main::toD0181_$0 = main::toD0181_$7&$3fff
|
|
|
|
|
Constant main::toD0181_$3 = >(word)main::toD0181_gfx#0
|
|
|
|
@ -2362,8 +2360,8 @@ Constant inlined memset::str#1 = (void*)BITMAP
|
|
|
|
|
Constant inlined mul16s::a#2 = $64
|
|
|
|
|
Constant inlined memset::str#0 = (void*)SCREEN
|
|
|
|
|
Constant inlined bitmap_clear::fgcol#0 = WHITE
|
|
|
|
|
Constant inlined divr16u::dividend#1 = >PI2_u4f28
|
|
|
|
|
Constant inlined divr16u::dividend#2 = <PI2_u4f28
|
|
|
|
|
Constant inlined divr16u::dividend#1 = _word1_PI2_u4f28
|
|
|
|
|
Constant inlined divr16u::dividend#2 = _word0_PI2_u4f28
|
|
|
|
|
Constant inlined bitmap_screen#0 = SCREEN
|
|
|
|
|
Constant inlined mulu16_sel::v2#2 = (word)$10000/6
|
|
|
|
|
Constant inlined bitmap_init::y#0 = 0
|
|
|
|
@ -2621,7 +2619,7 @@ main::@2: scope:[main] from main::@1
|
|
|
|
|
main::@9: scope:[main] from main::@2
|
|
|
|
|
[28] main::xpos#0 = mul16s::return#3
|
|
|
|
|
[29] main::$6 = main::xpos#0 << 4
|
|
|
|
|
[30] main::$7 = > main::$6
|
|
|
|
|
[30] main::$7 = _word1_ main::$6
|
|
|
|
|
[31] main::x#0 = $a0 + main::$7
|
|
|
|
|
[32] main::$20 = main::idx_y#3 << 1
|
|
|
|
|
[33] main::$22 = SINE + main::$20
|
|
|
|
@ -2633,7 +2631,7 @@ main::@9: scope:[main] from main::@2
|
|
|
|
|
main::@10: scope:[main] from main::@9
|
|
|
|
|
[38] main::ypos#0 = mul16s::return#4
|
|
|
|
|
[39] main::$10 = main::ypos#0 << 4
|
|
|
|
|
[40] main::$11 = > main::$10
|
|
|
|
|
[40] main::$11 = _word1_ main::$10
|
|
|
|
|
[41] main::y#0 = $64 + main::$11
|
|
|
|
|
[42] bitmap_plot::x#0 = main::x#0
|
|
|
|
|
[43] bitmap_plot::y#0 = (byte)main::y#0
|
|
|
|
@ -2689,7 +2687,7 @@ sin16s_gen2::@4: scope:[sin16s_gen2] from sin16s_gen2::@2
|
|
|
|
|
to:sin16s_gen2::@5
|
|
|
|
|
sin16s_gen2::@5: scope:[sin16s_gen2] from sin16s_gen2::@4
|
|
|
|
|
[67] sin16s_gen2::$6 = mul16s::return#0
|
|
|
|
|
[68] sin16s_gen2::$8 = > sin16s_gen2::$6
|
|
|
|
|
[68] sin16s_gen2::$8 = _word1_ sin16s_gen2::$6
|
|
|
|
|
[69] *sin16s_gen2::sintab#2 = (signed word)sin16s_gen2::$8
|
|
|
|
|
[70] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_SIGNED_WORD
|
|
|
|
|
[71] sin16s_gen2::x#1 = sin16s_gen2::x#2 + sin16s_gen2::step#0
|
|
|
|
@ -2781,18 +2779,18 @@ mul16s::@5: scope:[mul16s] from mul16s
|
|
|
|
|
[116] if(mul16s::a#3>=0) goto mul16s::@1
|
|
|
|
|
to:mul16s::@3
|
|
|
|
|
mul16s::@3: scope:[mul16s] from mul16s::@5
|
|
|
|
|
[117] mul16s::$6 = > mul16s::m#0
|
|
|
|
|
[117] mul16s::$6 = _word1_ mul16s::m#0
|
|
|
|
|
[118] mul16s::$11 = mul16s::$6 - (word)mul16s::b#3
|
|
|
|
|
[119] mul16s::m#1 = mul16s::m#0 hi= mul16s::$11
|
|
|
|
|
[119] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11
|
|
|
|
|
to:mul16s::@1
|
|
|
|
|
mul16s::@1: scope:[mul16s] from mul16s::@3 mul16s::@5
|
|
|
|
|
[120] mul16s::m#5 = phi( mul16s::@3/mul16s::m#1, mul16s::@5/mul16s::m#0 )
|
|
|
|
|
[121] if(mul16s::b#3>=0) goto mul16s::@2
|
|
|
|
|
to:mul16s::@4
|
|
|
|
|
mul16s::@4: scope:[mul16s] from mul16s::@1
|
|
|
|
|
[122] mul16s::$9 = > mul16s::m#5
|
|
|
|
|
[122] mul16s::$9 = _word1_ mul16s::m#5
|
|
|
|
|
[123] mul16s::$12 = mul16s::$9 - (word)mul16s::a#3
|
|
|
|
|
[124] mul16s::m#2 = mul16s::m#5 hi= mul16s::$12
|
|
|
|
|
[124] mul16s::m#2 = mul16s::m#5 word1= mul16s::$12
|
|
|
|
|
to:mul16s::@2
|
|
|
|
|
mul16s::@2: scope:[mul16s] from mul16s::@1 mul16s::@4
|
|
|
|
|
[125] mul16s::m#4 = phi( mul16s::@1/mul16s::m#5, mul16s::@4/mul16s::m#2 )
|
|
|
|
@ -2852,7 +2850,7 @@ sin16s::@5: scope:[sin16s] from sin16s::@1
|
|
|
|
|
sin16s::@2: scope:[sin16s] from sin16s::@1 sin16s::@5
|
|
|
|
|
[149] sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
|
|
|
|
|
[150] sin16s::$4 = sin16s::x#6 << 3
|
|
|
|
|
[151] sin16s::x1#0 = > sin16s::$4
|
|
|
|
|
[151] sin16s::x1#0 = _word1_ sin16s::$4
|
|
|
|
|
[152] mulu16_sel::v1#0 = sin16s::x1#0
|
|
|
|
|
[153] mulu16_sel::v2#0 = sin16s::x1#0
|
|
|
|
|
[154] call mulu16_sel
|
|
|
|
@ -2958,7 +2956,7 @@ mul16u::@3: scope:[mul16u] from mul16u::@2 mul16u::@4
|
|
|
|
|
|
|
|
|
|
word divr16u(word divr16u::dividend , word divr16u::divisor , word divr16u::rem)
|
|
|
|
|
divr16u: scope:[divr16u] from div32u16u div32u16u::@1
|
|
|
|
|
[204] divr16u::dividend#5 = phi( div32u16u/>PI2_u4f28, div32u16u::@1/<PI2_u4f28 )
|
|
|
|
|
[204] divr16u::dividend#5 = phi( div32u16u/_word1_PI2_u4f28, div32u16u::@1/_word0_PI2_u4f28 )
|
|
|
|
|
[204] divr16u::rem#10 = phi( div32u16u/0, div32u16u::@1/divr16u::rem#4 )
|
|
|
|
|
to:divr16u::@1
|
|
|
|
|
divr16u::@1: scope:[divr16u] from divr16u divr16u::@3
|
|
|
|
@ -3010,7 +3008,7 @@ mulu16_sel: scope:[mulu16_sel] from sin16s::@10 sin16s::@2 sin16s::@7 sin16s::@
|
|
|
|
|
mulu16_sel::@1: scope:[mulu16_sel] from mulu16_sel
|
|
|
|
|
[227] mulu16_sel::$0 = mul16u::return#0
|
|
|
|
|
[228] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
|
|
|
|
|
[229] mulu16_sel::return#12 = > mulu16_sel::$1
|
|
|
|
|
[229] mulu16_sel::return#12 = _word1_ mulu16_sel::$1
|
|
|
|
|
to:mulu16_sel::@return
|
|
|
|
|
mulu16_sel::@return: scope:[mulu16_sel] from mulu16_sel::@1
|
|
|
|
|
[230] return
|
|
|
|
@ -3595,7 +3593,6 @@ Statement [38] main::ypos#0 = mul16s::return#4 [ frame_cnt main::idx_x#3 main::i
|
|
|
|
|
Statement [39] main::$10 = main::ypos#0 << 4 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 main::$10 ] ( main:3 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 main::$10 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [41] main::y#0 = $64 + main::$11 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 main::y#0 ] ( main:3 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 main::y#0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [42] bitmap_plot::x#0 = main::x#0 [ frame_cnt main::idx_x#3 main::idx_y#3 main::y#0 bitmap_plot::x#0 ] ( main:3 [ frame_cnt main::idx_x#3 main::idx_y#3 main::y#0 bitmap_plot::x#0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [43] bitmap_plot::y#0 = (byte)main::y#0 [ frame_cnt main::idx_x#3 main::idx_y#3 bitmap_plot::x#0 bitmap_plot::y#0 ] ( main:3 [ frame_cnt main::idx_x#3 main::idx_y#3 bitmap_plot::x#0 bitmap_plot::y#0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [46] if(main::idx_x#1!=$200) goto main::@12 [ frame_cnt main::idx_y#3 main::idx_x#1 ] ( main:3 [ frame_cnt main::idx_y#3 main::idx_x#1 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [50] if(main::idx_y#1!=$200) goto main::@13 [ frame_cnt main::idx_x#10 main::idx_y#1 ] ( main:3 [ frame_cnt main::idx_x#10 main::idx_y#1 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [53] plots_per_frame[frame_cnt] = ++ plots_per_frame[frame_cnt] [ frame_cnt main::idx_x#10 main::idx_y#10 ] ( main:3 [ frame_cnt main::idx_x#10 main::idx_y#10 ] { } ) always clobbers reg byte x
|
|
|
|
@ -3607,7 +3604,7 @@ Statement [63] sin16s::return#0 = sin16s::return#1 [ sin16s_gen2::step#0 sin16s_
|
|
|
|
|
Statement [64] mul16s::a#0 = sin16s::return#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [66] mul16s::return#0 = mul16s::return#1 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#0 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#0 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [67] sin16s_gen2::$6 = mul16s::return#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$6 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$6 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [68] sin16s_gen2::$8 = > sin16s_gen2::$6 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [68] sin16s_gen2::$8 = _word1_ sin16s_gen2::$6 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [69] *sin16s_gen2::sintab#2 = (signed word)sin16s_gen2::$8 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] { } ) always clobbers reg byte a reg byte y
|
|
|
|
|
Statement [70] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_SIGNED_WORD [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#0 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#0 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [71] sin16s_gen2::x#1 = sin16s_gen2::x#2 + sin16s_gen2::step#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#1 sin16s_gen2::sintab#0 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#1 sin16s_gen2::sintab#0 ] { } ) always clobbers reg byte a
|
|
|
|
@ -3625,13 +3622,13 @@ Statement [112] mul16u::b#1 = (word)mul16s::b#3 [ mul16s::a#3 mul16s::b#3 mul16u
|
|
|
|
|
Statement [114] mul16u::return#3 = mul16u::res#2 [ mul16s::a#3 mul16s::b#3 mul16u::return#3 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16u::return#3 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } { mul16u::b#1 = mul16u::b#2 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16u::return#3 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } { mul16u::b#1 = mul16u::b#2 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16u::return#3 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::b#1 = mul16u::b#2 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [115] mul16s::m#0 = mul16u::return#3 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [116] if(mul16s::a#3>=0) goto mul16s::@1 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [117] mul16s::$6 = > mul16s::m#0 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [117] mul16s::$6 = _word1_ mul16s::m#0 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [118] mul16s::$11 = mul16s::$6 - (word)mul16s::b#3 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$11 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$11 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$11 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$11 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [119] mul16s::m#1 = mul16s::m#0 hi= mul16s::$11 [ mul16s::a#3 mul16s::b#3 mul16s::m#1 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [119] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11 [ mul16s::a#3 mul16s::b#3 mul16s::m#1 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [121] if(mul16s::b#3>=0) goto mul16s::@2 [ mul16s::a#3 mul16s::m#5 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::m#5 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::m#5 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::m#5 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [122] mul16s::$9 = > mul16s::m#5 [ mul16s::a#3 mul16s::m#5 mul16s::$9 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [122] mul16s::$9 = _word1_ mul16s::m#5 [ mul16s::a#3 mul16s::m#5 mul16s::$9 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [123] mul16s::$12 = mul16s::$9 - (word)mul16s::a#3 [ mul16s::m#5 mul16s::$12 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::m#5 mul16s::$12 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::m#5 mul16s::$12 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#5 mul16s::$12 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [124] mul16s::m#2 = mul16s::m#5 hi= mul16s::$12 [ mul16s::m#2 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::m#2 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::m#2 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#2 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [124] mul16s::m#2 = mul16s::m#5 word1= mul16s::$12 [ mul16s::m#2 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::m#2 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::m#2 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#2 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [126] mul16s::return#1 = (signed dword)mul16s::m#4 [ mul16s::return#1 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::return#1 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::return#1 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#1 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [128] bitmap_plot::plotter#0 = bitmap_plot_yhi[bitmap_plot::y#0] w= bitmap_plot_ylo[bitmap_plot::y#0] [ bitmap_plot::x#0 bitmap_plot::plotter#0 ] ( main:3::bitmap_plot:44 [ frame_cnt main::idx_x#3 main::idx_y#3 bitmap_plot::x#0 bitmap_plot::plotter#0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [129] bitmap_plot::$0 = bitmap_plot::x#0 & $fff8 [ bitmap_plot::x#0 bitmap_plot::plotter#0 bitmap_plot::$0 ] ( main:3::bitmap_plot:44 [ frame_cnt main::idx_x#3 main::idx_y#3 bitmap_plot::x#0 bitmap_plot::plotter#0 bitmap_plot::$0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
@ -3649,7 +3646,7 @@ Statement [147] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 [ sin16s::x#4 sin1
|
|
|
|
|
Removing always clobbered register reg byte a as potential for zp[1]:27 [ sin16s::isUpper#2 ]
|
|
|
|
|
Statement [148] sin16s::x#2 = PI_u4f28 - sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [150] sin16s::$4 = sin16s::x#6 << 3 [ sin16s::isUpper#2 sin16s::$4 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::$4 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [151] sin16s::x1#0 = > sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [151] sin16s::x1#0 = _word1_ sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [152] mulu16_sel::v1#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [153] mulu16_sel::v2#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [155] mulu16_sel::return#0 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
@ -3696,7 +3693,7 @@ Statement [224] mul16u::b#0 = mulu16_sel::v2#5 [ mul16u::b#0 mul16u::a#0 mulu16_
|
|
|
|
|
Statement [226] mul16u::return#0 = mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#0 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [227] mulu16_sel::$0 = mul16u::return#0 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [228] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [229] mulu16_sel::return#12 = > mulu16_sel::$1 [ mulu16_sel::return#12 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [229] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 [ mulu16_sel::return#12 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [1] frame_cnt = 1 [ frame_cnt ] ( [ frame_cnt ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [5] *BG_COLOR = WHITE [ frame_cnt ] ( [ frame_cnt ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [6] if(0==frame_cnt) goto irq::@1 [ frame_cnt ] ( [ frame_cnt ] { } ) always clobbers reg byte a
|
|
|
|
@ -3722,7 +3719,6 @@ Statement [38] main::ypos#0 = mul16s::return#4 [ frame_cnt main::idx_x#3 main::i
|
|
|
|
|
Statement [39] main::$10 = main::ypos#0 << 4 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 main::$10 ] ( main:3 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 main::$10 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [41] main::y#0 = $64 + main::$11 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 main::y#0 ] ( main:3 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 main::y#0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [42] bitmap_plot::x#0 = main::x#0 [ frame_cnt main::idx_x#3 main::idx_y#3 main::y#0 bitmap_plot::x#0 ] ( main:3 [ frame_cnt main::idx_x#3 main::idx_y#3 main::y#0 bitmap_plot::x#0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [43] bitmap_plot::y#0 = (byte)main::y#0 [ frame_cnt main::idx_x#3 main::idx_y#3 bitmap_plot::x#0 bitmap_plot::y#0 ] ( main:3 [ frame_cnt main::idx_x#3 main::idx_y#3 bitmap_plot::x#0 bitmap_plot::y#0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [46] if(main::idx_x#1!=$200) goto main::@12 [ frame_cnt main::idx_y#3 main::idx_x#1 ] ( main:3 [ frame_cnt main::idx_y#3 main::idx_x#1 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [50] if(main::idx_y#1!=$200) goto main::@13 [ frame_cnt main::idx_x#10 main::idx_y#1 ] ( main:3 [ frame_cnt main::idx_x#10 main::idx_y#1 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [53] plots_per_frame[frame_cnt] = ++ plots_per_frame[frame_cnt] [ frame_cnt main::idx_x#10 main::idx_y#10 ] ( main:3 [ frame_cnt main::idx_x#10 main::idx_y#10 ] { } ) always clobbers reg byte x
|
|
|
|
@ -3734,7 +3730,7 @@ Statement [63] sin16s::return#0 = sin16s::return#1 [ sin16s_gen2::step#0 sin16s_
|
|
|
|
|
Statement [64] mul16s::a#0 = sin16s::return#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#0 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [66] mul16s::return#0 = mul16s::return#1 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#0 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#0 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [67] sin16s_gen2::$6 = mul16s::return#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$6 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$6 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [68] sin16s_gen2::$8 = > sin16s_gen2::$6 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [68] sin16s_gen2::$8 = _word1_ sin16s_gen2::$6 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s_gen2::$8 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [69] *sin16s_gen2::sintab#2 = (signed word)sin16s_gen2::$8 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 ] { } ) always clobbers reg byte a reg byte y
|
|
|
|
|
Statement [70] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_SIGNED_WORD [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#0 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#0 ] { } ) always clobbers reg byte a
|
|
|
|
|
Statement [71] sin16s_gen2::x#1 = sin16s_gen2::x#2 + sin16s_gen2::step#0 [ sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#1 sin16s_gen2::sintab#0 ] ( main:3::sin16s_gen2:12 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#1 sin16s_gen2::sintab#0 ] { } ) always clobbers reg byte a
|
|
|
|
@ -3752,13 +3748,13 @@ Statement [112] mul16u::b#1 = (word)mul16s::b#3 [ mul16s::a#3 mul16s::b#3 mul16u
|
|
|
|
|
Statement [114] mul16u::return#3 = mul16u::res#2 [ mul16s::a#3 mul16s::b#3 mul16u::return#3 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16u::return#3 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } { mul16u::b#1 = mul16u::b#2 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16u::return#3 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } { mul16u::b#1 = mul16u::b#2 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16u::return#3 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } { mul16u::b#1 = mul16u::b#2 } { mul16u::a#2 = mul16u::a#6 } { mul16u::return#3 = mul16u::res#2 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [115] mul16s::m#0 = mul16u::return#3 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [116] if(mul16s::a#3>=0) goto mul16s::@1 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [117] mul16s::$6 = > mul16s::m#0 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [117] mul16s::$6 = _word1_ mul16s::m#0 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$6 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [118] mul16s::$11 = mul16s::$6 - (word)mul16s::b#3 [ mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$11 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$11 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$11 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#0 mul16s::$11 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [119] mul16s::m#1 = mul16s::m#0 hi= mul16s::$11 [ mul16s::a#3 mul16s::b#3 mul16s::m#1 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [119] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11 [ mul16s::a#3 mul16s::b#3 mul16s::m#1 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::b#3 mul16s::m#1 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [121] if(mul16s::b#3>=0) goto mul16s::@2 [ mul16s::a#3 mul16s::m#5 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::m#5 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::m#5 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::m#5 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [122] mul16s::$9 = > mul16s::m#5 [ mul16s::a#3 mul16s::m#5 mul16s::$9 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [122] mul16s::$9 = _word1_ mul16s::m#5 [ mul16s::a#3 mul16s::m#5 mul16s::$9 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::a#3 mul16s::m#5 mul16s::$9 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [123] mul16s::$12 = mul16s::$9 - (word)mul16s::a#3 [ mul16s::m#5 mul16s::$12 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::m#5 mul16s::$12 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::m#5 mul16s::$12 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#5 mul16s::$12 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [124] mul16s::m#2 = mul16s::m#5 hi= mul16s::$12 [ mul16s::m#2 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::m#2 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::m#2 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#2 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [124] mul16s::m#2 = mul16s::m#5 word1= mul16s::$12 [ mul16s::m#2 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::m#2 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::m#2 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::m#2 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [126] mul16s::return#1 = (signed dword)mul16s::m#4 [ mul16s::return#1 ] ( main:3::mul16s:26 [ frame_cnt main::idx_x#3 main::idx_y#3 mul16s::return#1 ] { { mul16s::b#1 = mul16s::b#3 main::cos_x#0 } { mul16s::return#1 = mul16s::return#3 } } main:3::mul16s:36 [ frame_cnt main::idx_x#3 main::idx_y#3 main::x#0 mul16s::return#1 ] { { mul16s::b#2 = mul16s::b#3 main::sin_y#0 } { mul16s::return#1 = mul16s::return#4 } } main:3::sin16s_gen2:12::mul16s:65 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 mul16s::return#1 ] { { mul16s::a#0 = mul16s::a#3 sin16s::return#0 } { mul16s::return#0 = mul16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [128] bitmap_plot::plotter#0 = bitmap_plot_yhi[bitmap_plot::y#0] w= bitmap_plot_ylo[bitmap_plot::y#0] [ bitmap_plot::x#0 bitmap_plot::plotter#0 ] ( main:3::bitmap_plot:44 [ frame_cnt main::idx_x#3 main::idx_y#3 bitmap_plot::x#0 bitmap_plot::plotter#0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [129] bitmap_plot::$0 = bitmap_plot::x#0 & $fff8 [ bitmap_plot::x#0 bitmap_plot::plotter#0 bitmap_plot::$0 ] ( main:3::bitmap_plot:44 [ frame_cnt main::idx_x#3 main::idx_y#3 bitmap_plot::x#0 bitmap_plot::plotter#0 bitmap_plot::$0 ] { { bitmap_plot::x#0 = main::x#0 } } ) always clobbers reg byte a
|
|
|
|
@ -3775,7 +3771,7 @@ Statement [145] sin16s::x#1 = sin16s::x#0 - PI_u4f28 [ sin16s::x#1 ] ( main:3::s
|
|
|
|
|
Statement [147] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::x#4 sin16s::isUpper#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [148] sin16s::x#2 = PI_u4f28 - sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x#2 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [150] sin16s::$4 = sin16s::x#6 << 3 [ sin16s::isUpper#2 sin16s::$4 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::$4 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [151] sin16s::x1#0 = > sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [151] sin16s::x1#0 = _word1_ sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [152] mulu16_sel::v1#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [153] mulu16_sel::v2#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [155] mulu16_sel::return#0 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] ( main:3::sin16s_gen2:12::sin16s:62 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
@ -3818,7 +3814,7 @@ Statement [224] mul16u::b#0 = mulu16_sel::v2#5 [ mul16u::b#0 mul16u::a#0 mulu16_
|
|
|
|
|
Statement [226] mul16u::return#0 = mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#0 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::a#0 = mul16u::a#6 mul16u::b#2 mul16u::b#0 mulu16_sel::v2#5 mulu16_sel::v2#0 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mul16u::return#0 = mul16u::res#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#1 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#1 sin16s::x2#0 } { mul16u::return#0 = mul16u::res#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#2 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#3 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#3 sin16s::x3#0 } { mul16u::return#0 = mul16u::res#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::b#0 = mul16u::b#2 mulu16_sel::v2#5 mulu16_sel::v2#4 sin16s::x1#0 } { mul16u::a#0 = mul16u::a#6 mulu16_sel::v1#5 mulu16_sel::v1#4 sin16s::x4#0 } { mul16u::return#0 = mul16u::res#2 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [227] mulu16_sel::$0 = mul16u::return#0 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [228] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [229] mulu16_sel::return#12 = > mulu16_sel::$1 [ mulu16_sel::return#12 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Statement [229] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 [ mulu16_sel::return#12 ] ( main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:154 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:159 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:163 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:169 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } } main:3::sin16s_gen2:12::sin16s:62::mulu16_sel:174 [ frame_cnt sin16s_gen2::step#0 sin16s_gen2::i#2 sin16s_gen2::x#2 sin16s_gen2::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen2::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } } ) always clobbers reg byte a
|
|
|
|
|
Potential registers zp[2]:2 [ main::idx_x#3 main::idx_x#10 main::idx_x#1 ] : zp[2]:2 ,
|
|
|
|
|
Potential registers zp[2]:4 [ main::idx_y#3 main::idx_y#10 main::idx_y#1 ] : zp[2]:4 ,
|
|
|
|
|
Potential registers zp[2]:6 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] : zp[2]:6 ,
|
|
|
|
@ -3947,26 +3943,26 @@ Uplifting [mul16s] best 27208 combination zp[4]:23 [ mul16s::m#4 mul16s::m#5 mul
|
|
|
|
|
Uplifting [memset] best 27192 combination zp[2]:39 [ memset::dst#2 memset::dst#4 memset::dst#1 ] zp[2]:204 [ memset::end#0 ] reg byte x [ memset::c#4 ] zp[2]:34 [ memset::num#2 ] zp[2]:36 [ memset::str#3 ]
|
|
|
|
|
Uplifting [bitmap_init] best 26742 combination zp[2]:17 [ bitmap_init::yoffs#2 bitmap_init::yoffs#4 bitmap_init::yoffs#1 ] reg byte a [ bitmap_init::bits#3 bitmap_init::bits#4 bitmap_init::bits#1 ] reg byte x [ bitmap_init::x#2 bitmap_init::x#1 ] reg byte x [ bitmap_init::y#2 bitmap_init::y#1 ] reg byte a [ bitmap_init::$4 ] zp[1]:135 [ bitmap_init::$5 ] zp[1]:136 [ bitmap_init::$6 ] zp[1]:133 [ bitmap_init::$7 ]
|
|
|
|
|
Limited combination testing to 100 combinations of 15360 possible.
|
|
|
|
|
Uplifting [bitmap_plot] best 26705 combination reg byte a [ bitmap_plot::y#0 ] zp[2]:155 [ bitmap_plot::$0 ] reg byte x [ bitmap_plot::$1 ] zp[2]:157 [ bitmap_plot::plotter#1 ] zp[2]:153 [ bitmap_plot::plotter#0 ] zp[2]:110 [ bitmap_plot::x#0 ]
|
|
|
|
|
Uplifting [sin16s_gen2] best 26705 combination zp[2]:6 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] zp[4]:127 [ sin16s_gen2::$6 ] zp[4]:8 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ] zp[2]:131 [ sin16s_gen2::$8 ] zp[2]:12 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ] zp[4]:117 [ sin16s_gen2::step#0 ]
|
|
|
|
|
Uplifting [div32u16u] best 26705 combination zp[2]:166 [ div32u16u::quotient_lo#0 ] zp[2]:162 [ div32u16u::quotient_hi#0 ] zp[4]:168 [ div32u16u::return#1 ] zp[4]:113 [ div32u16u::return#0 ]
|
|
|
|
|
Uplifting [main] best 26465 combination zp[2]:4 [ main::idx_y#3 main::idx_y#10 main::idx_y#1 ] zp[2]:66 [ main::$19 ] zp[2]:68 [ main::$21 ] zp[2]:70 [ main::cos_x#0 ] zp[4]:76 [ main::xpos#0 ] zp[4]:80 [ main::$6 ] reg byte alu [ main::$7 ] zp[2]:88 [ main::$20 ] zp[2]:90 [ main::$22 ] zp[2]:92 [ main::sin_y#0 ] zp[4]:98 [ main::ypos#0 ] zp[4]:102 [ main::$10 ] reg byte alu [ main::$11 ] zp[2]:2 [ main::idx_x#3 main::idx_x#10 main::idx_x#1 ] zp[2]:108 [ main::y#0 ] zp[2]:86 [ main::x#0 ]
|
|
|
|
|
Uplifting [] best 26465 combination zp[2]:209 [ rem16u#14 ] zp[1]:65 [ frame_cnt ]
|
|
|
|
|
Uplifting [MOS6526_CIA] best 26465 combination
|
|
|
|
|
Uplifting [MOS6569_VICII] best 26465 combination
|
|
|
|
|
Uplifting [MOS6581_SID] best 26465 combination
|
|
|
|
|
Uplifting [bitmap_clear] best 26465 combination
|
|
|
|
|
Uplifting [init_irq] best 26465 combination
|
|
|
|
|
Uplifting [irq] best 26465 combination
|
|
|
|
|
Uplifting [__start] best 26465 combination
|
|
|
|
|
Uplifting [bitmap_plot] best 26703 combination reg byte x [ bitmap_plot::y#0 ] zp[2]:155 [ bitmap_plot::$0 ] reg byte x [ bitmap_plot::$1 ] zp[2]:157 [ bitmap_plot::plotter#1 ] zp[2]:153 [ bitmap_plot::plotter#0 ] zp[2]:110 [ bitmap_plot::x#0 ]
|
|
|
|
|
Uplifting [sin16s_gen2] best 26703 combination zp[2]:6 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] zp[4]:127 [ sin16s_gen2::$6 ] zp[4]:8 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ] zp[2]:131 [ sin16s_gen2::$8 ] zp[2]:12 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ] zp[4]:117 [ sin16s_gen2::step#0 ]
|
|
|
|
|
Uplifting [div32u16u] best 26703 combination zp[2]:166 [ div32u16u::quotient_lo#0 ] zp[2]:162 [ div32u16u::quotient_hi#0 ] zp[4]:168 [ div32u16u::return#1 ] zp[4]:113 [ div32u16u::return#0 ]
|
|
|
|
|
Uplifting [main] best 26463 combination zp[2]:4 [ main::idx_y#3 main::idx_y#10 main::idx_y#1 ] zp[2]:66 [ main::$19 ] zp[2]:68 [ main::$21 ] zp[2]:70 [ main::cos_x#0 ] zp[4]:76 [ main::xpos#0 ] zp[4]:80 [ main::$6 ] reg byte alu [ main::$7 ] zp[2]:88 [ main::$20 ] zp[2]:90 [ main::$22 ] zp[2]:92 [ main::sin_y#0 ] zp[4]:98 [ main::ypos#0 ] zp[4]:102 [ main::$10 ] reg byte alu [ main::$11 ] zp[2]:2 [ main::idx_x#3 main::idx_x#10 main::idx_x#1 ] zp[2]:108 [ main::y#0 ] zp[2]:86 [ main::x#0 ]
|
|
|
|
|
Uplifting [] best 26463 combination zp[2]:209 [ rem16u#14 ] zp[1]:65 [ frame_cnt ]
|
|
|
|
|
Uplifting [MOS6526_CIA] best 26463 combination
|
|
|
|
|
Uplifting [MOS6569_VICII] best 26463 combination
|
|
|
|
|
Uplifting [MOS6581_SID] best 26463 combination
|
|
|
|
|
Uplifting [bitmap_clear] best 26463 combination
|
|
|
|
|
Uplifting [init_irq] best 26463 combination
|
|
|
|
|
Uplifting [irq] best 26463 combination
|
|
|
|
|
Uplifting [__start] best 26463 combination
|
|
|
|
|
Attempting to uplift remaining variables inzp[1]:135 [ bitmap_init::$5 ]
|
|
|
|
|
Uplifting [bitmap_init] best 26405 combination reg byte a [ bitmap_init::$5 ]
|
|
|
|
|
Uplifting [bitmap_init] best 26403 combination reg byte a [ bitmap_init::$5 ]
|
|
|
|
|
Attempting to uplift remaining variables inzp[1]:136 [ bitmap_init::$6 ]
|
|
|
|
|
Uplifting [bitmap_init] best 26345 combination reg byte a [ bitmap_init::$6 ]
|
|
|
|
|
Uplifting [bitmap_init] best 26343 combination reg byte a [ bitmap_init::$6 ]
|
|
|
|
|
Attempting to uplift remaining variables inzp[1]:133 [ bitmap_init::$7 ]
|
|
|
|
|
Uplifting [bitmap_init] best 26345 combination zp[1]:133 [ bitmap_init::$7 ]
|
|
|
|
|
Uplifting [bitmap_init] best 26343 combination zp[1]:133 [ bitmap_init::$7 ]
|
|
|
|
|
Attempting to uplift remaining variables inzp[1]:65 [ frame_cnt ]
|
|
|
|
|
Uplifting [] best 26345 combination zp[1]:65 [ frame_cnt ]
|
|
|
|
|
Uplifting [] best 26343 combination zp[1]:65 [ frame_cnt ]
|
|
|
|
|
Coalescing zero page register [ zp[2]:32 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] ] with [ zp[2]:202 [ sin16s::usinx#1 ] ] - score: 2
|
|
|
|
|
Coalescing zero page register [ zp[2]:60 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ] ] with [ zp[2]:184 [ sin16s::x3#0 ] ] - score: 2
|
|
|
|
|
Coalescing zero page register [ zp[2]:19 [ mul16s::a#3 mul16s::a#0 ] ] with [ zp[2]:121 [ sin16s::return#0 ] ] - score: 1
|
|
|
|
@ -4302,8 +4298,8 @@ main: {
|
|
|
|
|
rol.z __6+1
|
|
|
|
|
rol.z __6+2
|
|
|
|
|
rol.z __6+3
|
|
|
|
|
// [30] main::$7 = > main::$6
|
|
|
|
|
// [31] main::x#0 = $a0 + main::$7 -- vwuz1=vwuc1_plus__hi_vdsz2
|
|
|
|
|
// [30] main::$7 = _word1_ main::$6
|
|
|
|
|
// [31] main::x#0 = $a0 + main::$7 -- vwuz1=vwuc1_plus__word1_vdsz2
|
|
|
|
|
clc
|
|
|
|
|
lda #<$a0
|
|
|
|
|
adc.z __6+2
|
|
|
|
@ -4368,8 +4364,8 @@ main: {
|
|
|
|
|
rol.z __10+1
|
|
|
|
|
rol.z __10+2
|
|
|
|
|
rol.z __10+3
|
|
|
|
|
// [40] main::$11 = > main::$10
|
|
|
|
|
// [41] main::y#0 = $64 + main::$11 -- vwuz1=vwuc1_plus__hi_vdsz2
|
|
|
|
|
// [40] main::$11 = _word1_ main::$10
|
|
|
|
|
// [41] main::y#0 = $64 + main::$11 -- vwuz1=vwuc1_plus__word1_vdsz2
|
|
|
|
|
clc
|
|
|
|
|
lda #<$64
|
|
|
|
|
adc.z __10+2
|
|
|
|
@ -4378,8 +4374,8 @@ main: {
|
|
|
|
|
adc.z __10+3
|
|
|
|
|
sta.z y+1
|
|
|
|
|
// [42] bitmap_plot::x#0 = main::x#0
|
|
|
|
|
// [43] bitmap_plot::y#0 = (byte)main::y#0 -- vbuaa=_byte_vwuz1
|
|
|
|
|
lda.z y
|
|
|
|
|
// [43] bitmap_plot::y#0 = (byte)main::y#0 -- vbuxx=_byte_vwuz1
|
|
|
|
|
ldx.z y
|
|
|
|
|
// [44] call bitmap_plot
|
|
|
|
|
jsr bitmap_plot
|
|
|
|
|
jmp __b11
|
|
|
|
@ -4555,7 +4551,7 @@ sin16s_gen2: {
|
|
|
|
|
// sin16s_gen2::@5
|
|
|
|
|
__b5:
|
|
|
|
|
// [67] sin16s_gen2::$6 = mul16s::return#0
|
|
|
|
|
// [68] sin16s_gen2::$8 = > sin16s_gen2::$6 -- vwuz1=_hi_vdsz2
|
|
|
|
|
// [68] sin16s_gen2::$8 = _word1_ sin16s_gen2::$6 -- vwuz1=_word1_vdsz2
|
|
|
|
|
lda.z __6+2
|
|
|
|
|
sta.z __8
|
|
|
|
|
lda.z __6+3
|
|
|
|
@ -4668,13 +4664,13 @@ bitmap_init: {
|
|
|
|
|
// [83] bitmap_init::$7 = bitmap_init::y#2 & 7 -- vbuz1=vbuxx_band_vbuc1
|
|
|
|
|
lda #7
|
|
|
|
|
sax.z __7
|
|
|
|
|
// [84] bitmap_init::$4 = < bitmap_init::yoffs#2 -- vbuaa=_lo_pbuz1
|
|
|
|
|
// [84] bitmap_init::$4 = < bitmap_init::yoffs#2 -- vbuaa=_byte0_pbuz1
|
|
|
|
|
lda.z yoffs
|
|
|
|
|
// [85] bitmap_init::$5 = bitmap_init::$7 | bitmap_init::$4 -- vbuaa=vbuz1_bor_vbuaa
|
|
|
|
|
ora.z __7
|
|
|
|
|
// [86] bitmap_plot_ylo[bitmap_init::y#2] = bitmap_init::$5 -- pbuc1_derefidx_vbuxx=vbuaa
|
|
|
|
|
sta bitmap_plot_ylo,x
|
|
|
|
|
// [87] bitmap_init::$6 = > bitmap_init::yoffs#2 -- vbuaa=_hi_pbuz1
|
|
|
|
|
// [87] bitmap_init::$6 = > bitmap_init::yoffs#2 -- vbuaa=_byte1_pbuz1
|
|
|
|
|
lda.z yoffs+1
|
|
|
|
|
// [88] bitmap_plot_yhi[bitmap_init::y#2] = bitmap_init::$6 -- pbuc1_derefidx_vbuxx=vbuaa
|
|
|
|
|
sta bitmap_plot_yhi,x
|
|
|
|
@ -4842,7 +4838,7 @@ mul16s: {
|
|
|
|
|
jmp __b3
|
|
|
|
|
// mul16s::@3
|
|
|
|
|
__b3:
|
|
|
|
|
// [117] mul16s::$6 = > mul16s::m#0 -- vwuz1=_hi_vduz2
|
|
|
|
|
// [117] mul16s::$6 = _word1_ mul16s::m#0 -- vwuz1=_word1_vduz2
|
|
|
|
|
lda.z m+2
|
|
|
|
|
sta.z __6
|
|
|
|
|
lda.z m+3
|
|
|
|
@ -4855,7 +4851,7 @@ mul16s: {
|
|
|
|
|
lda.z __11+1
|
|
|
|
|
sbc.z b+1
|
|
|
|
|
sta.z __11+1
|
|
|
|
|
// [119] mul16s::m#1 = mul16s::m#0 hi= mul16s::$11 -- vduz1=vduz1_sethi_vwuz2
|
|
|
|
|
// [119] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11 -- vduz1=vduz1_setword1_vwuz2
|
|
|
|
|
lda.z __11
|
|
|
|
|
sta.z m+2
|
|
|
|
|
lda.z __11+1
|
|
|
|
@ -4873,7 +4869,7 @@ mul16s: {
|
|
|
|
|
jmp __b4
|
|
|
|
|
// mul16s::@4
|
|
|
|
|
__b4:
|
|
|
|
|
// [122] mul16s::$9 = > mul16s::m#5 -- vwuz1=_hi_vduz2
|
|
|
|
|
// [122] mul16s::$9 = _word1_ mul16s::m#5 -- vwuz1=_word1_vduz2
|
|
|
|
|
lda.z m+2
|
|
|
|
|
sta.z __9
|
|
|
|
|
lda.z m+3
|
|
|
|
@ -4886,7 +4882,7 @@ mul16s: {
|
|
|
|
|
lda.z __9+1
|
|
|
|
|
sbc.z __12+1
|
|
|
|
|
sta.z __12+1
|
|
|
|
|
// [124] mul16s::m#2 = mul16s::m#5 hi= mul16s::$12 -- vduz1=vduz1_sethi_vwuz2
|
|
|
|
|
// [124] mul16s::m#2 = mul16s::m#5 word1= mul16s::$12 -- vduz1=vduz1_setword1_vwuz2
|
|
|
|
|
lda.z __12
|
|
|
|
|
sta.z m+2
|
|
|
|
|
lda.z __12+1
|
|
|
|
@ -4907,16 +4903,15 @@ mul16s: {
|
|
|
|
|
}
|
|
|
|
|
// bitmap_plot
|
|
|
|
|
// Plot a single dot in the bitmap
|
|
|
|
|
// bitmap_plot(word zp($17) x, byte register(A) y)
|
|
|
|
|
// bitmap_plot(word zp($17) x, byte register(X) y)
|
|
|
|
|
bitmap_plot: {
|
|
|
|
|
.label __0 = $22
|
|
|
|
|
.label plotter = $20
|
|
|
|
|
.label x = $17
|
|
|
|
|
// [128] bitmap_plot::plotter#0 = bitmap_plot_yhi[bitmap_plot::y#0] w= bitmap_plot_ylo[bitmap_plot::y#0] -- vwuz1=pbuc1_derefidx_vbuaa_word_pbuc2_derefidx_vbuaa
|
|
|
|
|
tay
|
|
|
|
|
lda bitmap_plot_yhi,y
|
|
|
|
|
// [128] bitmap_plot::plotter#0 = bitmap_plot_yhi[bitmap_plot::y#0] w= bitmap_plot_ylo[bitmap_plot::y#0] -- vwuz1=pbuc1_derefidx_vbuxx_word_pbuc2_derefidx_vbuxx
|
|
|
|
|
lda bitmap_plot_yhi,x
|
|
|
|
|
sta.z plotter+1
|
|
|
|
|
lda bitmap_plot_ylo,y
|
|
|
|
|
lda bitmap_plot_ylo,x
|
|
|
|
|
sta.z plotter
|
|
|
|
|
// [129] bitmap_plot::$0 = bitmap_plot::x#0 & $fff8 -- vwuz1=vwuz2_band_vwuc1
|
|
|
|
|
lda.z x
|
|
|
|
@ -4933,7 +4928,7 @@ bitmap_plot: {
|
|
|
|
|
lda.z plotter+1
|
|
|
|
|
adc.z __0+1
|
|
|
|
|
sta.z plotter+1
|
|
|
|
|
// [131] bitmap_plot::$1 = < bitmap_plot::x#0 -- vbuxx=_lo_vwuz1
|
|
|
|
|
// [131] bitmap_plot::$1 = < bitmap_plot::x#0 -- vbuxx=_byte0_vwuz1
|
|
|
|
|
ldx.z x
|
|
|
|
|
// [132] *bitmap_plot::plotter#1 = *bitmap_plot::plotter#1 | bitmap_plot_bit[bitmap_plot::$1] -- _deref_pbuz1=_deref_pbuz1_bor_pbuc1_derefidx_vbuxx
|
|
|
|
|
lda bitmap_plot_bit,x
|
|
|
|
@ -4957,7 +4952,7 @@ div32u16u: {
|
|
|
|
|
// [135] call divr16u
|
|
|
|
|
// [204] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
|
|
|
|
|
divr16u_from_div32u16u:
|
|
|
|
|
// [204] phi divr16u::dividend#5 = >PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1
|
|
|
|
|
// [204] phi divr16u::dividend#5 = _word1_PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1
|
|
|
|
|
lda #<PI2_u4f28>>$10
|
|
|
|
|
sta.z divr16u.dividend
|
|
|
|
|
lda #>PI2_u4f28>>$10
|
|
|
|
@ -4985,7 +4980,7 @@ div32u16u: {
|
|
|
|
|
// [139] call divr16u
|
|
|
|
|
// [204] phi from div32u16u::@1 to divr16u [phi:div32u16u::@1->divr16u]
|
|
|
|
|
divr16u_from___b1:
|
|
|
|
|
// [204] phi divr16u::dividend#5 = <PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1
|
|
|
|
|
// [204] phi divr16u::dividend#5 = _word0_PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1
|
|
|
|
|
lda #<PI2_u4f28&$ffff
|
|
|
|
|
sta.z divr16u.dividend
|
|
|
|
|
lda #>PI2_u4f28&$ffff
|
|
|
|
@ -5140,7 +5135,7 @@ sin16s: {
|
|
|
|
|
rol.z __4+1
|
|
|
|
|
rol.z __4+2
|
|
|
|
|
rol.z __4+3
|
|
|
|
|
// [151] sin16s::x1#0 = > sin16s::$4 -- vwuz1=_hi_vduz2
|
|
|
|
|
// [151] sin16s::x1#0 = _word1_ sin16s::$4 -- vwuz1=_word1_vduz2
|
|
|
|
|
lda.z __4+2
|
|
|
|
|
sta.z x1
|
|
|
|
|
lda.z __4+3
|
|
|
|
@ -5493,7 +5488,7 @@ divr16u: {
|
|
|
|
|
// [206] divr16u::rem#0 = divr16u::rem#5 << 1 -- vwuz1=vwuz1_rol_1
|
|
|
|
|
asl.z rem
|
|
|
|
|
rol.z rem+1
|
|
|
|
|
// [207] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_hi_vwuz1
|
|
|
|
|
// [207] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_byte1_vwuz1
|
|
|
|
|
lda.z dividend+1
|
|
|
|
|
// [208] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1
|
|
|
|
|
and #$80
|
|
|
|
@ -5611,7 +5606,7 @@ mulu16_sel: {
|
|
|
|
|
dex
|
|
|
|
|
bne !-
|
|
|
|
|
!e:
|
|
|
|
|
// [229] mulu16_sel::return#12 = > mulu16_sel::$1 -- vwuz1=_hi_vduz2
|
|
|
|
|
// [229] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 -- vwuz1=_word1_vduz2
|
|
|
|
|
lda.z __1+2
|
|
|
|
|
sta.z return
|
|
|
|
|
lda.z __1+3
|
|
|
|
@ -5943,7 +5938,7 @@ byte* bitmap_plot::plotter#1 plotter zp[2]:32 1501.5
|
|
|
|
|
word bitmap_plot::x
|
|
|
|
|
word bitmap_plot::x#0 x zp[2]:23 420.59999999999997
|
|
|
|
|
byte bitmap_plot::y
|
|
|
|
|
byte bitmap_plot::y#0 reg byte a 2103.0
|
|
|
|
|
byte bitmap_plot::y#0 reg byte x 2103.0
|
|
|
|
|
constant const byte* bitmap_plot_bit[$100] = { fill( $100, 0) }
|
|
|
|
|
constant const byte* bitmap_plot_yhi[$100] = { fill( $100, 0) }
|
|
|
|
|
constant const byte* bitmap_plot_ylo[$100] = { fill( $100, 0) }
|
|
|
|
@ -6187,7 +6182,7 @@ reg byte alu [ main::$7 ]
|
|
|
|
|
zp[2]:23 [ main::x#0 bitmap_plot::x#0 bitmap_init::yoffs#2 bitmap_init::yoffs#4 bitmap_init::yoffs#1 sin16s_gen2::i#2 sin16s_gen2::i#1 ]
|
|
|
|
|
reg byte alu [ main::$11 ]
|
|
|
|
|
zp[2]:25 [ main::y#0 memset::num#2 memset::end#0 sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ]
|
|
|
|
|
reg byte a [ bitmap_plot::y#0 ]
|
|
|
|
|
reg byte x [ bitmap_plot::y#0 ]
|
|
|
|
|
zp[4]:27 [ div32u16u::return#0 sin16s_gen2::step#0 div32u16u::return#1 ]
|
|
|
|
|
zp[1]:31 [ bitmap_init::$7 ]
|
|
|
|
|
reg byte a [ bitmap_init::$4 ]
|
|
|
|
@ -6206,7 +6201,7 @@ zp[2]:44 [ rem16u#14 ]
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
FINAL ASSEMBLER
|
|
|
|
|
Score: 20492
|
|
|
|
|
Score: 20490
|
|
|
|
|
|
|
|
|
|
// File Comments
|
|
|
|
|
// Tests the simple bitmap plotter - and counts plots per frame in an IRQ
|
|
|
|
@ -6442,10 +6437,10 @@ main: {
|
|
|
|
|
rol.z __6+1
|
|
|
|
|
rol.z __6+2
|
|
|
|
|
rol.z __6+3
|
|
|
|
|
// >(xpos<<4)
|
|
|
|
|
// [30] main::$7 = > main::$6
|
|
|
|
|
// word x = (word)(160 + >(xpos<<4))
|
|
|
|
|
// [31] main::x#0 = $a0 + main::$7 -- vwuz1=vwuc1_plus__hi_vdsz2
|
|
|
|
|
// WORD1(xpos<<4)
|
|
|
|
|
// [30] main::$7 = _word1_ main::$6
|
|
|
|
|
// word x = (word)(160 + WORD1(xpos<<4))
|
|
|
|
|
// [31] main::x#0 = $a0 + main::$7 -- vwuz1=vwuc1_plus__word1_vdsz2
|
|
|
|
|
clc
|
|
|
|
|
lda #<$a0
|
|
|
|
|
adc.z __6+2
|
|
|
|
@ -6512,10 +6507,10 @@ main: {
|
|
|
|
|
rol.z __10+1
|
|
|
|
|
rol.z __10+2
|
|
|
|
|
rol.z __10+3
|
|
|
|
|
// >(ypos<<4)
|
|
|
|
|
// [40] main::$11 = > main::$10
|
|
|
|
|
// word y = (word)(100 + >(ypos<<4))
|
|
|
|
|
// [41] main::y#0 = $64 + main::$11 -- vwuz1=vwuc1_plus__hi_vdsz2
|
|
|
|
|
// WORD1(ypos<<4)
|
|
|
|
|
// [40] main::$11 = _word1_ main::$10
|
|
|
|
|
// word y = (word)(100 + WORD1(ypos<<4))
|
|
|
|
|
// [41] main::y#0 = $64 + main::$11 -- vwuz1=vwuc1_plus__word1_vdsz2
|
|
|
|
|
clc
|
|
|
|
|
lda #<$64
|
|
|
|
|
adc.z __10+2
|
|
|
|
@ -6525,8 +6520,8 @@ main: {
|
|
|
|
|
sta.z y+1
|
|
|
|
|
// bitmap_plot(x, (byte)y)
|
|
|
|
|
// [42] bitmap_plot::x#0 = main::x#0
|
|
|
|
|
// [43] bitmap_plot::y#0 = (byte)main::y#0 -- vbuaa=_byte_vwuz1
|
|
|
|
|
lda.z y
|
|
|
|
|
// [43] bitmap_plot::y#0 = (byte)main::y#0 -- vbuxx=_byte_vwuz1
|
|
|
|
|
ldx.z y
|
|
|
|
|
// [44] call bitmap_plot
|
|
|
|
|
jsr bitmap_plot
|
|
|
|
|
// main::@11
|
|
|
|
@ -6680,13 +6675,13 @@ sin16s_gen2: {
|
|
|
|
|
// [66] mul16s::return#0 = mul16s::return#1
|
|
|
|
|
// sin16s_gen2::@5
|
|
|
|
|
// [67] sin16s_gen2::$6 = mul16s::return#0
|
|
|
|
|
// >mul16s(sin16s(x), ampl)
|
|
|
|
|
// [68] sin16s_gen2::$8 = > sin16s_gen2::$6 -- vwuz1=_hi_vdsz2
|
|
|
|
|
// WORD1(mul16s(sin16s(x), ampl))
|
|
|
|
|
// [68] sin16s_gen2::$8 = _word1_ sin16s_gen2::$6 -- vwuz1=_word1_vdsz2
|
|
|
|
|
lda.z __6+2
|
|
|
|
|
sta.z __8
|
|
|
|
|
lda.z __6+3
|
|
|
|
|
sta.z __8+1
|
|
|
|
|
// *sintab++ = offs + (signed int)>mul16s(sin16s(x), ampl)
|
|
|
|
|
// *sintab++ = offs + (signed int)WORD1(mul16s(sin16s(x), ampl))
|
|
|
|
|
// [69] *sin16s_gen2::sintab#2 = (signed word)sin16s_gen2::$8 -- _deref_pwsz1=vwsz2
|
|
|
|
|
ldy #0
|
|
|
|
|
lda.z __8
|
|
|
|
@ -6694,7 +6689,7 @@ sin16s_gen2: {
|
|
|
|
|
iny
|
|
|
|
|
lda.z __8+1
|
|
|
|
|
sta (sintab),y
|
|
|
|
|
// *sintab++ = offs + (signed int)>mul16s(sin16s(x), ampl);
|
|
|
|
|
// *sintab++ = offs + (signed int)WORD1(mul16s(sin16s(x), ampl));
|
|
|
|
|
// [70] sin16s_gen2::sintab#0 = sin16s_gen2::sintab#2 + SIZEOF_SIGNED_WORD -- pwsz1=pwsz1_plus_vbuc1
|
|
|
|
|
lda #SIZEOF_SIGNED_WORD
|
|
|
|
|
clc
|
|
|
|
@ -6787,19 +6782,19 @@ bitmap_init: {
|
|
|
|
|
// [83] bitmap_init::$7 = bitmap_init::y#2 & 7 -- vbuz1=vbuxx_band_vbuc1
|
|
|
|
|
lda #7
|
|
|
|
|
sax.z __7
|
|
|
|
|
// <yoffs
|
|
|
|
|
// [84] bitmap_init::$4 = < bitmap_init::yoffs#2 -- vbuaa=_lo_pbuz1
|
|
|
|
|
// BYTE0(yoffs)
|
|
|
|
|
// [84] bitmap_init::$4 = < bitmap_init::yoffs#2 -- vbuaa=_byte0_pbuz1
|
|
|
|
|
lda.z yoffs
|
|
|
|
|
// y&$7 | <yoffs
|
|
|
|
|
// y&$7 | BYTE0(yoffs)
|
|
|
|
|
// [85] bitmap_init::$5 = bitmap_init::$7 | bitmap_init::$4 -- vbuaa=vbuz1_bor_vbuaa
|
|
|
|
|
ora.z __7
|
|
|
|
|
// bitmap_plot_ylo[y] = y&$7 | <yoffs
|
|
|
|
|
// bitmap_plot_ylo[y] = y&$7 | BYTE0(yoffs)
|
|
|
|
|
// [86] bitmap_plot_ylo[bitmap_init::y#2] = bitmap_init::$5 -- pbuc1_derefidx_vbuxx=vbuaa
|
|
|
|
|
sta bitmap_plot_ylo,x
|
|
|
|
|
// >yoffs
|
|
|
|
|
// [87] bitmap_init::$6 = > bitmap_init::yoffs#2 -- vbuaa=_hi_pbuz1
|
|
|
|
|
// BYTE1(yoffs)
|
|
|
|
|
// [87] bitmap_init::$6 = > bitmap_init::yoffs#2 -- vbuaa=_byte1_pbuz1
|
|
|
|
|
lda.z yoffs+1
|
|
|
|
|
// bitmap_plot_yhi[y] = >yoffs
|
|
|
|
|
// bitmap_plot_yhi[y] = BYTE1(yoffs)
|
|
|
|
|
// [88] bitmap_plot_yhi[bitmap_init::y#2] = bitmap_init::$6 -- pbuc1_derefidx_vbuxx=vbuaa
|
|
|
|
|
sta bitmap_plot_yhi,x
|
|
|
|
|
// if((y&$7)==7)
|
|
|
|
@ -6966,13 +6961,13 @@ mul16s: {
|
|
|
|
|
lda.z a+1
|
|
|
|
|
bpl __b1
|
|
|
|
|
// mul16s::@3
|
|
|
|
|
// >m
|
|
|
|
|
// [117] mul16s::$6 = > mul16s::m#0 -- vwuz1=_hi_vduz2
|
|
|
|
|
// WORD1(m)
|
|
|
|
|
// [117] mul16s::$6 = _word1_ mul16s::m#0 -- vwuz1=_word1_vduz2
|
|
|
|
|
lda.z m+2
|
|
|
|
|
sta.z __6
|
|
|
|
|
lda.z m+3
|
|
|
|
|
sta.z __6+1
|
|
|
|
|
// >m = (>m)-(unsigned int)b
|
|
|
|
|
// WORD1(m) = WORD1(m)-(unsigned int)b
|
|
|
|
|
// [118] mul16s::$11 = mul16s::$6 - (word)mul16s::b#3 -- vwuz1=vwuz1_minus_vwuz2
|
|
|
|
|
lda.z __11
|
|
|
|
|
sec
|
|
|
|
@ -6981,7 +6976,7 @@ mul16s: {
|
|
|
|
|
lda.z __11+1
|
|
|
|
|
sbc.z b+1
|
|
|
|
|
sta.z __11+1
|
|
|
|
|
// [119] mul16s::m#1 = mul16s::m#0 hi= mul16s::$11 -- vduz1=vduz1_sethi_vwuz2
|
|
|
|
|
// [119] mul16s::m#1 = mul16s::m#0 word1= mul16s::$11 -- vduz1=vduz1_setword1_vwuz2
|
|
|
|
|
lda.z __11
|
|
|
|
|
sta.z m+2
|
|
|
|
|
lda.z __11+1
|
|
|
|
@ -6995,13 +6990,13 @@ mul16s: {
|
|
|
|
|
lda.z b+1
|
|
|
|
|
bpl __b2
|
|
|
|
|
// mul16s::@4
|
|
|
|
|
// >m
|
|
|
|
|
// [122] mul16s::$9 = > mul16s::m#5 -- vwuz1=_hi_vduz2
|
|
|
|
|
// WORD1(m)
|
|
|
|
|
// [122] mul16s::$9 = _word1_ mul16s::m#5 -- vwuz1=_word1_vduz2
|
|
|
|
|
lda.z m+2
|
|
|
|
|
sta.z __9
|
|
|
|
|
lda.z m+3
|
|
|
|
|
sta.z __9+1
|
|
|
|
|
// >m = (>m)-(unsigned int)a
|
|
|
|
|
// WORD1(m) = WORD1(m)-(unsigned int)a
|
|
|
|
|
// [123] mul16s::$12 = mul16s::$9 - (word)mul16s::a#3 -- vwuz1=vwuz2_minus_vwuz1
|
|
|
|
|
lda.z __9
|
|
|
|
|
sec
|
|
|
|
@ -7010,7 +7005,7 @@ mul16s: {
|
|
|
|
|
lda.z __9+1
|
|
|
|
|
sbc.z __12+1
|
|
|
|
|
sta.z __12+1
|
|
|
|
|
// [124] mul16s::m#2 = mul16s::m#5 hi= mul16s::$12 -- vduz1=vduz1_sethi_vwuz2
|
|
|
|
|
// [124] mul16s::m#2 = mul16s::m#5 word1= mul16s::$12 -- vduz1=vduz1_setword1_vwuz2
|
|
|
|
|
lda.z __12
|
|
|
|
|
sta.z m+2
|
|
|
|
|
lda.z __12+1
|
|
|
|
@ -7028,17 +7023,16 @@ mul16s: {
|
|
|
|
|
}
|
|
|
|
|
// bitmap_plot
|
|
|
|
|
// Plot a single dot in the bitmap
|
|
|
|
|
// bitmap_plot(word zp($17) x, byte register(A) y)
|
|
|
|
|
// bitmap_plot(word zp($17) x, byte register(X) y)
|
|
|
|
|
bitmap_plot: {
|
|
|
|
|
.label __0 = $22
|
|
|
|
|
.label plotter = $20
|
|
|
|
|
.label x = $17
|
|
|
|
|
// char* plotter = (char*) { bitmap_plot_yhi[y], bitmap_plot_ylo[y] }
|
|
|
|
|
// [128] bitmap_plot::plotter#0 = bitmap_plot_yhi[bitmap_plot::y#0] w= bitmap_plot_ylo[bitmap_plot::y#0] -- vwuz1=pbuc1_derefidx_vbuaa_word_pbuc2_derefidx_vbuaa
|
|
|
|
|
tay
|
|
|
|
|
lda bitmap_plot_yhi,y
|
|
|
|
|
// [128] bitmap_plot::plotter#0 = bitmap_plot_yhi[bitmap_plot::y#0] w= bitmap_plot_ylo[bitmap_plot::y#0] -- vwuz1=pbuc1_derefidx_vbuxx_word_pbuc2_derefidx_vbuxx
|
|
|
|
|
lda bitmap_plot_yhi,x
|
|
|
|
|
sta.z plotter+1
|
|
|
|
|
lda bitmap_plot_ylo,y
|
|
|
|
|
lda bitmap_plot_ylo,x
|
|
|
|
|
sta.z plotter
|
|
|
|
|
// x & $fff8
|
|
|
|
|
// [129] bitmap_plot::$0 = bitmap_plot::x#0 & $fff8 -- vwuz1=vwuz2_band_vwuc1
|
|
|
|
@ -7057,10 +7051,10 @@ bitmap_plot: {
|
|
|
|
|
lda.z plotter+1
|
|
|
|
|
adc.z __0+1
|
|
|
|
|
sta.z plotter+1
|
|
|
|
|
// <x
|
|
|
|
|
// [131] bitmap_plot::$1 = < bitmap_plot::x#0 -- vbuxx=_lo_vwuz1
|
|
|
|
|
// BYTE0(x)
|
|
|
|
|
// [131] bitmap_plot::$1 = < bitmap_plot::x#0 -- vbuxx=_byte0_vwuz1
|
|
|
|
|
ldx.z x
|
|
|
|
|
// *plotter |= bitmap_plot_bit[<x]
|
|
|
|
|
// *plotter |= bitmap_plot_bit[BYTE0(x)]
|
|
|
|
|
// [132] *bitmap_plot::plotter#1 = *bitmap_plot::plotter#1 | bitmap_plot_bit[bitmap_plot::$1] -- _deref_pbuz1=_deref_pbuz1_bor_pbuc1_derefidx_vbuxx
|
|
|
|
|
lda bitmap_plot_bit,x
|
|
|
|
|
ldy #0
|
|
|
|
@ -7078,10 +7072,10 @@ div32u16u: {
|
|
|
|
|
.label return = $1b
|
|
|
|
|
.label quotient_hi = $28
|
|
|
|
|
.label quotient_lo = $14
|
|
|
|
|
// divr16u(>dividend, divisor, 0)
|
|
|
|
|
// divr16u(WORD1(dividend), divisor, 0)
|
|
|
|
|
// [135] call divr16u
|
|
|
|
|
// [204] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
|
|
|
|
|
// [204] phi divr16u::dividend#5 = >PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1
|
|
|
|
|
// [204] phi divr16u::dividend#5 = _word1_PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1
|
|
|
|
|
lda #<PI2_u4f28>>$10
|
|
|
|
|
sta.z divr16u.dividend
|
|
|
|
|
lda #>PI2_u4f28>>$10
|
|
|
|
@ -7091,16 +7085,16 @@ div32u16u: {
|
|
|
|
|
sta.z divr16u.rem
|
|
|
|
|
sta.z divr16u.rem+1
|
|
|
|
|
jsr divr16u
|
|
|
|
|
// divr16u(>dividend, divisor, 0)
|
|
|
|
|
// divr16u(WORD1(dividend), divisor, 0)
|
|
|
|
|
// [136] divr16u::return#2 = divr16u::return#0
|
|
|
|
|
// div32u16u::@1
|
|
|
|
|
// unsigned int quotient_hi = divr16u(>dividend, divisor, 0)
|
|
|
|
|
// unsigned int quotient_hi = divr16u(WORD1(dividend), divisor, 0)
|
|
|
|
|
// [137] div32u16u::quotient_hi#0 = divr16u::return#2 -- vwuz1=vwuz2
|
|
|
|
|
lda.z divr16u.return
|
|
|
|
|
sta.z quotient_hi
|
|
|
|
|
lda.z divr16u.return+1
|
|
|
|
|
sta.z quotient_hi+1
|
|
|
|
|
// divr16u(<dividend, divisor, rem16u)
|
|
|
|
|
// divr16u(WORD0(dividend), divisor, rem16u)
|
|
|
|
|
// [138] divr16u::rem#4 = rem16u#14 -- vwuz1=vwuz2
|
|
|
|
|
lda.z rem16u
|
|
|
|
|
sta.z divr16u.rem
|
|
|
|
@ -7108,17 +7102,17 @@ div32u16u: {
|
|
|
|
|
sta.z divr16u.rem+1
|
|
|
|
|
// [139] call divr16u
|
|
|
|
|
// [204] phi from div32u16u::@1 to divr16u [phi:div32u16u::@1->divr16u]
|
|
|
|
|
// [204] phi divr16u::dividend#5 = <PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1
|
|
|
|
|
// [204] phi divr16u::dividend#5 = _word0_PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1
|
|
|
|
|
lda #<PI2_u4f28&$ffff
|
|
|
|
|
sta.z divr16u.dividend
|
|
|
|
|
lda #>PI2_u4f28&$ffff
|
|
|
|
|
sta.z divr16u.dividend+1
|
|
|
|
|
// [204] phi divr16u::rem#10 = divr16u::rem#4 [phi:div32u16u::@1->divr16u#1] -- register_copy
|
|
|
|
|
jsr divr16u
|
|
|
|
|
// divr16u(<dividend, divisor, rem16u)
|
|
|
|
|
// divr16u(WORD0(dividend), divisor, rem16u)
|
|
|
|
|
// [140] divr16u::return#3 = divr16u::return#0
|
|
|
|
|
// div32u16u::@2
|
|
|
|
|
// unsigned int quotient_lo = divr16u(<dividend, divisor, rem16u)
|
|
|
|
|
// unsigned int quotient_lo = divr16u(WORD0(dividend), divisor, rem16u)
|
|
|
|
|
// [141] div32u16u::quotient_lo#0 = divr16u::return#3
|
|
|
|
|
// unsigned long quotient = { quotient_hi, quotient_lo}
|
|
|
|
|
// [142] div32u16u::return#1 = div32u16u::quotient_hi#0 dw= div32u16u::quotient_lo#0 -- vduz1=vwuz2_dword_vwuz3
|
|
|
|
@ -7259,8 +7253,8 @@ sin16s: {
|
|
|
|
|
rol.z __4+1
|
|
|
|
|
rol.z __4+2
|
|
|
|
|
rol.z __4+3
|
|
|
|
|
// unsigned int x1 = >x<<3
|
|
|
|
|
// [151] sin16s::x1#0 = > sin16s::$4 -- vwuz1=_hi_vduz2
|
|
|
|
|
// unsigned int x1 = WORD1(x<<3)
|
|
|
|
|
// [151] sin16s::x1#0 = _word1_ sin16s::$4 -- vwuz1=_word1_vduz2
|
|
|
|
|
lda.z __4+2
|
|
|
|
|
sta.z x1
|
|
|
|
|
lda.z __4+3
|
|
|
|
@ -7602,13 +7596,13 @@ divr16u: {
|
|
|
|
|
// [206] divr16u::rem#0 = divr16u::rem#5 << 1 -- vwuz1=vwuz1_rol_1
|
|
|
|
|
asl.z rem
|
|
|
|
|
rol.z rem+1
|
|
|
|
|
// >dividend
|
|
|
|
|
// [207] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_hi_vwuz1
|
|
|
|
|
// BYTE1(dividend)
|
|
|
|
|
// [207] divr16u::$1 = > divr16u::dividend#3 -- vbuaa=_byte1_vwuz1
|
|
|
|
|
lda.z dividend+1
|
|
|
|
|
// >dividend & $80
|
|
|
|
|
// BYTE1(dividend) & $80
|
|
|
|
|
// [208] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1
|
|
|
|
|
and #$80
|
|
|
|
|
// if( (>dividend & $80) != 0 )
|
|
|
|
|
// if( (BYTE1(dividend) & $80) != 0 )
|
|
|
|
|
// [209] if(divr16u::$2==0) goto divr16u::@2 -- vbuaa_eq_0_then_la1
|
|
|
|
|
cmp #0
|
|
|
|
|
beq __b2
|
|
|
|
@ -7718,8 +7712,8 @@ mulu16_sel: {
|
|
|
|
|
dex
|
|
|
|
|
bne !-
|
|
|
|
|
!e:
|
|
|
|
|
// >mul16u(v1, v2)<<select
|
|
|
|
|
// [229] mulu16_sel::return#12 = > mulu16_sel::$1 -- vwuz1=_hi_vduz2
|
|
|
|
|
// WORD1(mul16u(v1, v2)<<select)
|
|
|
|
|
// [229] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 -- vwuz1=_word1_vduz2
|
|
|
|
|
lda.z __1+2
|
|
|
|
|
sta.z return
|
|
|
|
|
lda.z __1+3
|
|
|
|
|