From 73bdd4ff8df7e36486b2b9203c4307bec89e231f Mon Sep 17 00:00:00 2001
From: jespergravgaard <jesper@balmangravgaard.dk>
Date: Sun, 25 Feb 2018 00:08:11 +0100
Subject: [PATCH] Optimized sin /128 part.

---
 .../kickc/fragment/asm/vwuz1=vwuz1_ror_4.asm  |    6 +
 .../kickc/fragment/asm/vwuz1=vwuz2_ror_4.asm  |   10 +
 .../dk/camelot64/kickc/test/kc/division.kc    |    9 +
 .../dk/camelot64/kickc/test/kc/sinusgen.kc    |   11 +-
 .../dk/camelot64/kickc/test/ref/sinusgen.asm  |   27 +-
 .../dk/camelot64/kickc/test/ref/sinusgen.cfg  |  211 +-
 .../dk/camelot64/kickc/test/ref/sinusgen.log  | 3096 ++++++++---------
 .../dk/camelot64/kickc/test/ref/sinusgen.sym  |   39 +-
 8 files changed, 1633 insertions(+), 1776 deletions(-)
 create mode 100644 src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz1_ror_4.asm
 create mode 100644 src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz2_ror_4.asm

diff --git a/src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz1_ror_4.asm b/src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz1_ror_4.asm
new file mode 100644
index 000000000..e471f2659
--- /dev/null
+++ b/src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz1_ror_4.asm
@@ -0,0 +1,6 @@
+ldy #4
+!:
+lsr {z1}+1
+ror {z1}
+dey
+bne !-
\ No newline at end of file
diff --git a/src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz2_ror_4.asm b/src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz2_ror_4.asm
new file mode 100644
index 000000000..7bda81a62
--- /dev/null
+++ b/src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz2_ror_4.asm
@@ -0,0 +1,10 @@
+lda {z2}+1
+sta {z1}+1
+lda {z2}
+sta {z1}
+ldy #4
+!:
+lsr {z1}+1
+ror {z1}
+dey
+bne !-
\ No newline at end of file
diff --git a/src/test/java/dk/camelot64/kickc/test/kc/division.kc b/src/test/java/dk/camelot64/kickc/test/kc/division.kc
index 11a0b0725..40f35fde5 100644
--- a/src/test/java/dk/camelot64/kickc/test/kc/division.kc
+++ b/src/test/java/dk/camelot64/kickc/test/kc/division.kc
@@ -68,6 +68,15 @@ word divr16u(word dividend, word divisor, word rem) {
     return quotient;
 }
 
+// Divide unsigned 32-bit dword dividend with a 16-bit word divisor
+// The 16-bit word remainder can be found in rem16u after the division
+dword div32u16u(dword dividend, word divisor) {
+  word quotient_hi = divr16u(>dividend, divisor, 0);
+  word quotient_lo = divr16u(<dividend, divisor, rem16u);
+  dword quotient = { quotient_hi, quotient_lo};
+  return quotient;
+}
+
 // Remainder after signed 8 bit division
 signed byte rem8s = 0;
 
diff --git a/src/test/java/dk/camelot64/kickc/test/kc/sinusgen.kc b/src/test/java/dk/camelot64/kickc/test/kc/sinusgen.kc
index 97cf18465..dece32e89 100644
--- a/src/test/java/dk/camelot64/kickc/test/kc/sinusgen.kc
+++ b/src/test/java/dk/camelot64/kickc/test/kc/sinusgen.kc
@@ -73,7 +73,8 @@ signed word sin16s(dword x) {
     word usinx = x1 - x3_6; // u[1.15] x - x^3/6
     word x4 = mul_u16_sel(x3, x1, 0); // u[3.13] x^4
     word x5 = mul_u16_sel(x4, x1, 0); // u[4.12] x^5
-    word x5_128 = mul_u16_sel(x5, $10000/128, 3); // u[1.15] x^5/128;
+    //word x5_128 = mul_u16_sel(x5, $10000/128, 3); // u[1.15] x^5/128;
+    word x5_128 = x5>>4;
     usinx = usinx + x5_128; // u[1.15] (always an initial zero)
     signed word sinx = (signed word)usinx; // s[0.15]
     if(isUpper!=0) {
@@ -128,11 +129,3 @@ word mul_u16_sel(word v1, word v2, byte select) {
     return >mul16u(v1, v2)<<select;
 }
 
-// Divide unsigned 32-bit dword dividend with a 16-bit word divisor
-// The 16-bit word remainder can be found in rem16u after the division
-dword div32u16u(dword dividend, word divisor) {
-  word quotient_hi = divr16u(>dividend, divisor, 0);
-  word quotient_lo = divr16u(<dividend, divisor, rem16u);
-  dword quotient = { quotient_hi, quotient_lo};
-  return quotient;
-}
\ No newline at end of file
diff --git a/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.asm b/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.asm
index 5dd07a3b2..1eac44c9a 100644
--- a/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.asm
+++ b/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.asm
@@ -238,7 +238,7 @@ sin16s: {
     .label x3_6 = $13
     .label usinx = 6
     .label x4 = 8
-    .label x5 = 8
+    .label x5 = $13
     .label x5_128 = $13
     .label sinx = 6
     .label isUpper = $e
@@ -364,25 +364,21 @@ sin16s: {
     ldx #0
     jsr mul_u16_sel
     lda mul_u16_sel.return
-    sta mul_u16_sel.return_11
+    sta mul_u16_sel.return_10
     lda mul_u16_sel.return+1
-    sta mul_u16_sel.return_11+1
+    sta mul_u16_sel.return_10+1
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
     ldx #0
     jsr mul_u16_sel
-    lda mul_u16_sel.return
-    sta mul_u16_sel.return_12
-    lda mul_u16_sel.return+1
-    sta mul_u16_sel.return_12+1
-    ldx #3
-    lda #<$10000/$80
-    sta mul_u16_sel.v2
-    lda #>$10000/$80
-    sta mul_u16_sel.v2+1
-    jsr mul_u16_sel
+    ldy #4
+  !:
+    lsr x5_128+1
+    ror x5_128
+    dey
+    bne !-
     lda usinx
     clc
     adc x5_128
@@ -411,8 +407,7 @@ mul_u16_sel: {
     .label v2 = $13
     .label return = $13
     .label return_1 = 8
-    .label return_11 = 8
-    .label return_12 = 8
+    .label return_10 = 8
     lda v1
     sta mul16u.a
     lda v1+1
@@ -486,9 +481,9 @@ mul16u: {
     jmp b1
 }
 div32u16u: {
-    .label return = $1b
     .label quotient_hi = $13
     .label quotient_lo = 8
+    .label return = $1b
     lda #<main.wavelength
     sta divr16u.divisor
     lda #>main.wavelength
diff --git a/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.cfg b/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.cfg
index c0be33d02..4dd3c26b5 100644
--- a/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.cfg
+++ b/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.cfg
@@ -125,11 +125,11 @@ print_cls::@return: scope:[print_cls]  from print_cls::@1
   to:@return
 sin16s_gen: scope:[sin16s_gen]  from main
   [58] phi() [ ] ( main:2::sin16s_gen:5 [ ] )
-  [59] call div32u16u param-assignment [ div32u16u::return#1 ] ( main:2::sin16s_gen:5 [ div32u16u::return#1 ] )
-  [60] (dword) div32u16u::return#0 ← (dword) div32u16u::return#1 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
+  [59] call div32u16u param-assignment [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
+  [60] (dword) div32u16u::return#2 ← (dword) div32u16u::return#0 [ div32u16u::return#2 ] ( main:2::sin16s_gen:5 [ div32u16u::return#2 ] )
   to:sin16s_gen::@3
 sin16s_gen::@3: scope:[sin16s_gen]  from sin16s_gen
-  [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#0 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] )
+  [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#2 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] )
   to:sin16s_gen::@1
 sin16s_gen::@1: scope:[sin16s_gen]  from sin16s_gen::@3 sin16s_gen::@4
   [62] (word) sin16s_gen::i#2 ← phi( sin16s_gen::@3/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s_gen::@4/(word) sin16s_gen::i#1 ) [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 ] )
@@ -157,169 +157,164 @@ sin16s::@4: scope:[sin16s]  from sin16s
   [74] (dword) sin16s::x#1 ← (dword) sin16s::x#0 - (const dword) PI_u4f28#0 [ sin16s::x#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#1 ] )
   to:sin16s::@1
 sin16s::@1: scope:[sin16s]  from sin16s sin16s::@4
-  [75] (byte) sin16s::isUpper#10 ← phi( sin16s/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@4/(byte/signed byte/word/signed word/dword/signed dword) 1 ) [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] )
-  [75] (dword) sin16s::x#4 ← phi( sin16s/(dword) sin16s::x#0 sin16s::@4/(dword) sin16s::x#1 ) [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] )
-  [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] )
+  [75] (byte) sin16s::isUpper#2 ← phi( sin16s/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@4/(byte/signed byte/word/signed word/dword/signed dword) 1 ) [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] )
+  [75] (dword) sin16s::x#4 ← phi( sin16s/(dword) sin16s::x#0 sin16s::@4/(dword) sin16s::x#1 ) [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] )
+  [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] )
   to:sin16s::@5
 sin16s::@5: scope:[sin16s]  from sin16s::@1
-  [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#10 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#2 ] )
+  [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#2 ] )
   to:sin16s::@2
 sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
-  [78] (dword) sin16s::x#6 ← phi( sin16s::@1/(dword) sin16s::x#4 sin16s::@5/(dword) sin16s::x#2 ) [ sin16s::isUpper#10 sin16s::x#6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#6 ] )
-  [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#10 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::$6 ] )
-  [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#10 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 ] )
-  [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] )
-  [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] )
-  [83] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] )
+  [78] (dword) sin16s::x#6 ← phi( sin16s::@1/(dword) sin16s::x#4 sin16s::@5/(dword) sin16s::x#2 ) [ sin16s::isUpper#2 sin16s::x#6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#6 ] )
+  [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#2 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::$6 ] )
+  [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 ] )
+  [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] )
+  [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] )
+  [83] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] )
   to:sin16s::@8
 sin16s::@8: scope:[sin16s]  from sin16s::@2
-  [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] )
-  [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] )
-  [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] )
-  [88] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] )
+  [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] )
+  [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] )
+  [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] )
+  [88] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] )
   to:sin16s::@9
 sin16s::@9: scope:[sin16s]  from sin16s::@8
-  [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] )
-  [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] )
-  [92] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] )
-  [93] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] )
+  [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] )
+  [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] )
+  [92] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] )
+  [93] (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] )
   to:sin16s::@10
 sin16s::@10: scope:[sin16s]  from sin16s::@9
-  [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] )
-  [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] )
-  [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] )
-  [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] )
-  [98] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  [99] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] )
+  [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] )
+  [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] )
+  [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] )
+  [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] )
+  [98] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  [99] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] )
   to:sin16s::@11
 sin16s::@11: scope:[sin16s]  from sin16s::@10
-  [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] )
-  [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] )
-  [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] )
-  [103] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  [104] (word) mul_u16_sel::return#12 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] )
+  [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] )
+  [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] )
+  [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] )
+  [103] call mul_u16_sel param-assignment [ sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  [104] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] )
   to:sin16s::@12
 sin16s::@12: scope:[sin16s]  from sin16s::@11
-  [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] )
-  [106] (word) mul_u16_sel::v1#5 ← (word) sin16s::x5#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] )
-  [107] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  [108] (word) mul_u16_sel::return#13 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] )
-  to:sin16s::@13
-sin16s::@13: scope:[sin16s]  from sin16s::@12
-  [109] (word) sin16s::x5_128#0 ← (word) mul_u16_sel::return#13 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] )
-  [110] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#10 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#1 ] )
-  [111] if((byte) sin16s::isUpper#10==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@16 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] )
+  [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] )
+  [106] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] )
+  [107] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] )
+  [108] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] )
   to:sin16s::@6
-sin16s::@6: scope:[sin16s]  from sin16s::@13
-  [112] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] )
+sin16s::@6: scope:[sin16s]  from sin16s::@12
+  [109] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] )
   to:sin16s::@3
-sin16s::@3: scope:[sin16s]  from sin16s::@16 sin16s::@6
-  [113] (signed word) sin16s::return#1 ← phi( sin16s::@16/(signed word~) sin16s::return#5 sin16s::@6/(signed word) sin16s::sinx#1 ) [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
+sin16s::@3: scope:[sin16s]  from sin16s::@15 sin16s::@6
+  [110] (signed word) sin16s::return#1 ← phi( sin16s::@15/(signed word~) sin16s::return#5 sin16s::@6/(signed word) sin16s::sinx#1 ) [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
   to:sin16s::@return
 sin16s::@return: scope:[sin16s]  from sin16s::@3
-  [114] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
+  [111] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
   to:@return
-sin16s::@16: scope:[sin16s]  from sin16s::@13
-  [115] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] )
+sin16s::@15: scope:[sin16s]  from sin16s::@12
+  [112] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] )
   to:sin16s::@3
-mul_u16_sel: scope:[mul_u16_sel]  from sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@2 sin16s::@8 sin16s::@9
-  [116] (byte) mul_u16_sel::select#6 ← phi( sin16s::@10/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@11/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@12/(byte/signed byte/word/signed word/dword/signed dword) 3 sin16s::@2/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@8/(byte/signed byte/word/signed word/dword/signed dword) 1 sin16s::@9/(byte/signed byte/word/signed word/dword/signed dword) 1 ) [ mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] )
-  [116] (word) mul_u16_sel::v2#6 ← phi( sin16s::@10/(word) mul_u16_sel::v2#3 sin16s::@11/(word) mul_u16_sel::v2#4 sin16s::@12/(dword/signed dword) 65536/(byte/word/signed word/dword/signed dword) 128 sin16s::@2/(word) mul_u16_sel::v2#0 sin16s::@8/(word) mul_u16_sel::v2#1 sin16s::@9/(dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 ) [ mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] )
-  [116] (word) mul_u16_sel::v1#6 ← phi( sin16s::@10/(word) mul_u16_sel::v1#3 sin16s::@11/(word) mul_u16_sel::v1#4 sin16s::@12/(word) mul_u16_sel::v1#5 sin16s::@2/(word) mul_u16_sel::v1#0 sin16s::@8/(word) mul_u16_sel::v1#1 sin16s::@9/(word) mul_u16_sel::v1#2 ) [ mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] )
-  [117] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#6 [ mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] )
-  [118] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#6 [ mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] )
-  [119] call mul16u param-assignment [ mul_u16_sel::select#6 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
-  [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#6 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] )
+mul_u16_sel: scope:[mul_u16_sel]  from sin16s::@10 sin16s::@11 sin16s::@2 sin16s::@8 sin16s::@9
+  [113] (byte) mul_u16_sel::select#5 ← phi( sin16s::@10/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@11/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@2/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@8/(byte/signed byte/word/signed word/dword/signed dword) 1 sin16s::@9/(byte/signed byte/word/signed word/dword/signed dword) 1 ) [ mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] )
+  [113] (word) mul_u16_sel::v2#5 ← phi( sin16s::@10/(word) mul_u16_sel::v2#3 sin16s::@11/(word) mul_u16_sel::v2#4 sin16s::@2/(word) mul_u16_sel::v2#0 sin16s::@8/(word) mul_u16_sel::v2#1 sin16s::@9/(dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 ) [ mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] )
+  [113] (word) mul_u16_sel::v1#5 ← phi( sin16s::@10/(word) mul_u16_sel::v1#3 sin16s::@11/(word) mul_u16_sel::v1#4 sin16s::@2/(word) mul_u16_sel::v1#0 sin16s::@8/(word) mul_u16_sel::v1#1 sin16s::@9/(word) mul_u16_sel::v1#2 ) [ mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] )
+  [114] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#5 [ mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] )
+  [115] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#5 [ mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] )
+  [116] call mul16u param-assignment [ mul_u16_sel::select#5 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
+  [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] )
   to:mul_u16_sel::@2
 mul_u16_sel::@2: scope:[mul_u16_sel]  from mul_u16_sel
-  [121] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#6 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] )
-  [122] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#6 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] )
-  [123] (word) mul_u16_sel::return#14 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] )
+  [118] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#5 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] )
+  [119] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#5 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::$1 ] )
+  [120] (word) mul_u16_sel::return#12 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] )
   to:mul_u16_sel::@return
 mul_u16_sel::@return: scope:[mul_u16_sel]  from mul_u16_sel::@2
-  [124] return  [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] )
+  [121] return  [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] )
   to:@return
 mul16u: scope:[mul16u]  from mul_u16_sel
-  [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] )
+  [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] )
   to:mul16u::@1
 mul16u::@1: scope:[mul16u]  from mul16u mul16u::@4
-  [126] (dword) mul16u::mb#2 ← phi( mul16u/(dword) mul16u::mb#0 mul16u::@4/(dword) mul16u::mb#1 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
-  [126] (dword) mul16u::res#2 ← phi( mul16u/(byte/signed byte/word/signed word/dword/signed dword) 0 mul16u::@4/(dword) mul16u::res#6 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
-  [126] (word) mul16u::a#2 ← phi( mul16u/(word) mul16u::a#1 mul16u::@4/(word) mul16u::a#0 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
-  [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [123] (dword) mul16u::mb#2 ← phi( mul16u/(dword) mul16u::mb#0 mul16u::@4/(dword) mul16u::mb#1 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [123] (dword) mul16u::res#2 ← phi( mul16u/(byte/signed byte/word/signed word/dword/signed dword) 0 mul16u::@4/(dword) mul16u::res#6 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [123] (word) mul16u::a#2 ← phi( mul16u/(word) mul16u::a#1 mul16u::@4/(word) mul16u::a#0 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
   to:mul16u::@return
 mul16u::@return: scope:[mul16u]  from mul16u::@1
-  [128] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
+  [125] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
   to:@return
 mul16u::@2: scope:[mul16u]  from mul16u::@1
-  [129] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] )
-  [130] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [126] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] )
+  [127] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
   to:mul16u::@7
 mul16u::@7: scope:[mul16u]  from mul16u::@2
-  [131] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] )
+  [128] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] )
   to:mul16u::@4
 mul16u::@4: scope:[mul16u]  from mul16u::@2 mul16u::@7
-  [132] (dword) mul16u::res#6 ← phi( mul16u::@2/(dword) mul16u::res#2 mul16u::@7/(dword) mul16u::res#1 ) [ mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] )
-  [133] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] )
-  [134] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] )
+  [129] (dword) mul16u::res#6 ← phi( mul16u::@2/(dword) mul16u::res#2 mul16u::@7/(dword) mul16u::res#1 ) [ mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] )
+  [130] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] )
+  [131] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] )
   to:mul16u::@1
 div32u16u: scope:[div32u16u]  from sin16s_gen
-  [135] phi() [ ] ( main:2::sin16s_gen:5::div32u16u:59 [ ] )
-  [136] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
-  [137] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] )
+  [132] phi() [ ] ( main:2::sin16s_gen:5::div32u16u:59 [ ] )
+  [133] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
+  [134] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] )
   to:div32u16u::@2
 div32u16u::@2: scope:[div32u16u]  from div32u16u
-  [138] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] )
-  [139] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] )
-  [140] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
-  [141] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] )
+  [135] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] )
+  [136] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] )
+  [137] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
+  [138] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] )
   to:div32u16u::@3
 div32u16u::@3: scope:[div32u16u]  from div32u16u::@2
-  [142] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] )
-  [143] (dword) div32u16u::return#1 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] )
+  [139] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] )
+  [140] (dword) div32u16u::return#0 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] )
   to:div32u16u::@return
 div32u16u::@return: scope:[div32u16u]  from div32u16u::@3
-  [144] return  [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] )
+  [141] return  [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] )
   to:@return
 divr16u: scope:[divr16u]  from div32u16u div32u16u::@2
-  [145] (word) divr16u::divisor#6 ← phi( div32u16u/(const word) main::wavelength#0 div32u16u::@2/(const word) main::wavelength#0 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
-  [145] (word) divr16u::dividend#5 ← phi( div32u16u/>(const dword) PI2_u4f28#0 div32u16u::@2/<(const dword) PI2_u4f28#0 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
-  [145] (word) divr16u::rem#10 ← phi( div32u16u/(byte/signed byte/word/signed word/dword/signed dword) 0 div32u16u::@2/(word) divr16u::rem#4 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
+  [142] (word) divr16u::divisor#6 ← phi( div32u16u/(const word) main::wavelength#0 div32u16u::@2/(const word) main::wavelength#0 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
+  [142] (word) divr16u::dividend#5 ← phi( div32u16u/>(const dword) PI2_u4f28#0 div32u16u::@2/<(const dword) PI2_u4f28#0 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
+  [142] (word) divr16u::rem#10 ← phi( div32u16u/(byte/signed byte/word/signed word/dword/signed dword) 0 div32u16u::@2/(word) divr16u::rem#4 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
   to:divr16u::@1
 divr16u::@1: scope:[divr16u]  from divr16u divr16u::@3
-  [146] (byte) divr16u::i#2 ← phi( divr16u/(byte/signed byte/word/signed word/dword/signed dword) 0 divr16u::@3/(byte) divr16u::i#1 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
-  [146] (word) divr16u::quotient#3 ← phi( divr16u/(byte/signed byte/word/signed word/dword/signed dword) 0 divr16u::@3/(word) divr16u::return#0 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
-  [146] (word) divr16u::dividend#3 ← phi( divr16u/(word) divr16u::dividend#5 divr16u::@3/(word) divr16u::dividend#0 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
-  [146] (word) divr16u::rem#5 ← phi( divr16u/(word) divr16u::rem#10 divr16u::@3/(word) divr16u::rem#11 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
-  [147] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] )
-  [148] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] )
-  [149] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] )
-  [150] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] )
+  [143] (byte) divr16u::i#2 ← phi( divr16u/(byte/signed byte/word/signed word/dword/signed dword) 0 divr16u::@3/(byte) divr16u::i#1 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
+  [143] (word) divr16u::quotient#3 ← phi( divr16u/(byte/signed byte/word/signed word/dword/signed dword) 0 divr16u::@3/(word) divr16u::return#0 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
+  [143] (word) divr16u::dividend#3 ← phi( divr16u/(word) divr16u::dividend#5 divr16u::@3/(word) divr16u::dividend#0 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
+  [143] (word) divr16u::rem#5 ← phi( divr16u/(word) divr16u::rem#10 divr16u::@3/(word) divr16u::rem#11 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
+  [144] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] )
+  [145] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] )
+  [146] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] )
+  [147] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] )
   to:divr16u::@4
 divr16u::@4: scope:[divr16u]  from divr16u::@1
-  [151] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] )
+  [148] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] )
   to:divr16u::@2
 divr16u::@2: scope:[divr16u]  from divr16u::@1 divr16u::@4
-  [152] (word) divr16u::rem#6 ← phi( divr16u::@1/(word) divr16u::rem#0 divr16u::@4/(word) divr16u::rem#1 ) [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] )
-  [153] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] )
-  [154] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] )
-  [155] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] )
+  [149] (word) divr16u::rem#6 ← phi( divr16u::@1/(word) divr16u::rem#0 divr16u::@4/(word) divr16u::rem#1 ) [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] )
+  [150] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] )
+  [151] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] )
+  [152] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] )
   to:divr16u::@5
 divr16u::@5: scope:[divr16u]  from divr16u::@2
-  [156] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] )
-  [157] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] )
+  [153] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] )
+  [154] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] )
   to:divr16u::@3
 divr16u::@3: scope:[divr16u]  from divr16u::@2 divr16u::@5
-  [158] (word) divr16u::return#0 ← phi( divr16u::@2/(word) divr16u::quotient#1 divr16u::@5/(word) divr16u::quotient#2 ) [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] )
-  [158] (word) divr16u::rem#11 ← phi( divr16u::@2/(word) divr16u::rem#6 divr16u::@5/(word) divr16u::rem#2 ) [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] )
-  [159] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] )
-  [160] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] )
+  [155] (word) divr16u::return#0 ← phi( divr16u::@2/(word) divr16u::quotient#1 divr16u::@5/(word) divr16u::quotient#2 ) [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] )
+  [155] (word) divr16u::rem#11 ← phi( divr16u::@2/(word) divr16u::rem#6 divr16u::@5/(word) divr16u::rem#2 ) [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] )
+  [156] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] )
+  [157] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] )
   to:divr16u::@6
 divr16u::@6: scope:[divr16u]  from divr16u::@3
-  [161] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  [158] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
   to:divr16u::@return
 divr16u::@return: scope:[divr16u]  from divr16u::@6
-  [162] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  [159] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
   to:@return
diff --git a/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.log b/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.log
index 75b275554..2d9cfeccb 100644
--- a/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.log
+++ b/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.log
@@ -74,7 +74,8 @@ signed word sin16s(dword x) {
     word usinx = x1 - x3_6; // u[1.15] x - x^3/6
     word x4 = mul_u16_sel(x3, x1, 0); // u[3.13] x^4
     word x5 = mul_u16_sel(x4, x1, 0); // u[4.12] x^5
-    word x5_128 = mul_u16_sel(x5, $10000/128, 3); // u[1.15] x^5/128;
+    //word x5_128 = mul_u16_sel(x5, $10000/128, 3); // u[1.15] x^5/128;
+    word x5_128 = x5>>4;
     usinx = usinx + x5_128; // u[1.15] (always an initial zero)
     signed word sinx = (signed word)usinx; // s[0.15]
     if(isUpper!=0) {
@@ -129,14 +130,7 @@ word mul_u16_sel(word v1, word v2, byte select) {
     return >mul16u(v1, v2)<<select;
 }
 
-// Divide unsigned 32-bit dword dividend with a 16-bit word divisor
-// The 16-bit word remainder can be found in rem16u after the division
-dword div32u16u(dword dividend, word divisor) {
-  word quotient_hi = divr16u(>dividend, divisor, 0);
-  word quotient_lo = divr16u(<dividend, divisor, rem16u);
-  dword quotient = { quotient_hi, quotient_lo};
-  return quotient;
-}
+
 Importing division.kc
 PARSING src/test/java/dk/camelot64/kickc/test/kc/division.kc
 // Simple binary division implementation
@@ -209,6 +203,15 @@ word divr16u(word dividend, word divisor, word rem) {
     return quotient;
 }
 
+// Divide unsigned 32-bit dword dividend with a 16-bit word divisor
+// The 16-bit word remainder can be found in rem16u after the division
+dword div32u16u(dword dividend, word divisor) {
+  word quotient_hi = divr16u(>dividend, divisor, 0);
+  word quotient_lo = divr16u(<dividend, divisor, rem16u);
+  dword quotient = { quotient_hi, quotient_lo};
+  return quotient;
+}
+
 // Remainder after signed 8 bit division
 signed byte rem8s = 0;
 
@@ -520,6 +523,20 @@ divr16u::@return:
   (word) divr16u::return ← (word) divr16u::return
   return (word) divr16u::return
 endproc // divr16u()
+proc (dword()) div32u16u((dword) div32u16u::dividend , (word) div32u16u::divisor)
+  (word~) div32u16u::$0 ← > (dword) div32u16u::dividend
+  (word~) div32u16u::$1 ← call divr16u (word~) div32u16u::$0 (word) div32u16u::divisor (byte/signed byte/word/signed word/dword/signed dword) 0 
+  (word) div32u16u::quotient_hi ← (word~) div32u16u::$1
+  (word~) div32u16u::$2 ← < (dword) div32u16u::dividend
+  (word~) div32u16u::$3 ← call divr16u (word~) div32u16u::$2 (word) div32u16u::divisor (word) rem16u 
+  (word) div32u16u::quotient_lo ← (word~) div32u16u::$3
+  (dword) div32u16u::quotient ← { (word) div32u16u::quotient_hi, (word) div32u16u::quotient_lo }
+  (dword) div32u16u::return ← (dword) div32u16u::quotient
+  goto div32u16u::@return
+div32u16u::@return:
+  (dword) div32u16u::return ← (dword) div32u16u::return
+  return (dword) div32u16u::return
+endproc // div32u16u()
   (signed byte) rem8s ← (byte/signed byte/word/signed word/dword/signed dword) 0
 proc (signed byte()) div8s((signed byte) div8s::dividend , (signed byte) div8s::divisor)
   (byte) div8s::neg ← (byte/signed byte/word/signed word/dword/signed dword) 0
@@ -931,19 +948,18 @@ sin16s::@2:
   (word) sin16s::x4 ← (word~) sin16s::$13
   (word~) sin16s::$14 ← call mul_u16_sel (word) sin16s::x4 (word) sin16s::x1 (byte/signed byte/word/signed word/dword/signed dword) 0 
   (word) sin16s::x5 ← (word~) sin16s::$14
-  (word/signed word/dword/signed dword~) sin16s::$15 ← (dword/signed dword) 65536 / (byte/word/signed word/dword/signed dword) 128
-  (word~) sin16s::$16 ← call mul_u16_sel (word) sin16s::x5 (word/signed word/dword/signed dword~) sin16s::$15 (byte/signed byte/word/signed word/dword/signed dword) 3 
-  (word) sin16s::x5_128 ← (word~) sin16s::$16
-  (word~) sin16s::$17 ← (word) sin16s::usinx + (word) sin16s::x5_128
-  (word) sin16s::usinx ← (word~) sin16s::$17
-  (signed word~) sin16s::$18 ← ((signed word)) (word) sin16s::usinx
-  (signed word) sin16s::sinx ← (signed word~) sin16s::$18
-  (boolean~) sin16s::$19 ← (byte) sin16s::isUpper != (byte/signed byte/word/signed word/dword/signed dword) 0
-  (boolean~) sin16s::$20 ← ! (boolean~) sin16s::$19
-  if((boolean~) sin16s::$20) goto sin16s::@3
-  (signed word~) sin16s::$21 ← ((signed word)) (word) sin16s::usinx
-  (signed word~) sin16s::$22 ← - (signed word~) sin16s::$21
-  (signed word) sin16s::sinx ← (signed word~) sin16s::$22
+  (word~) sin16s::$15 ← (word) sin16s::x5 >> (byte/signed byte/word/signed word/dword/signed dword) 4
+  (word) sin16s::x5_128 ← (word~) sin16s::$15
+  (word~) sin16s::$16 ← (word) sin16s::usinx + (word) sin16s::x5_128
+  (word) sin16s::usinx ← (word~) sin16s::$16
+  (signed word~) sin16s::$17 ← ((signed word)) (word) sin16s::usinx
+  (signed word) sin16s::sinx ← (signed word~) sin16s::$17
+  (boolean~) sin16s::$18 ← (byte) sin16s::isUpper != (byte/signed byte/word/signed word/dword/signed dword) 0
+  (boolean~) sin16s::$19 ← ! (boolean~) sin16s::$18
+  if((boolean~) sin16s::$19) goto sin16s::@3
+  (signed word~) sin16s::$20 ← ((signed word)) (word) sin16s::usinx
+  (signed word~) sin16s::$21 ← - (signed word~) sin16s::$20
+  (signed word) sin16s::sinx ← (signed word~) sin16s::$21
 sin16s::@3:
   (signed word) sin16s::return ← (signed word) sin16s::sinx
   goto sin16s::@return
@@ -1023,20 +1039,6 @@ mul_u16_sel::@return:
   (word) mul_u16_sel::return ← (word) mul_u16_sel::return
   return (word) mul_u16_sel::return
 endproc // mul_u16_sel()
-proc (dword()) div32u16u((dword) div32u16u::dividend , (word) div32u16u::divisor)
-  (word~) div32u16u::$0 ← > (dword) div32u16u::dividend
-  (word~) div32u16u::$1 ← call divr16u (word~) div32u16u::$0 (word) div32u16u::divisor (byte/signed byte/word/signed word/dword/signed dword) 0 
-  (word) div32u16u::quotient_hi ← (word~) div32u16u::$1
-  (word~) div32u16u::$2 ← < (dword) div32u16u::dividend
-  (word~) div32u16u::$3 ← call divr16u (word~) div32u16u::$2 (word) div32u16u::divisor (word) rem16u 
-  (word) div32u16u::quotient_lo ← (word~) div32u16u::$3
-  (dword) div32u16u::quotient ← { (word) div32u16u::quotient_hi, (word) div32u16u::quotient_lo }
-  (dword) div32u16u::return ← (dword) div32u16u::quotient
-  goto div32u16u::@return
-div32u16u::@return:
-  (dword) div32u16u::return ← (dword) div32u16u::return
-  return (dword) div32u16u::return
-endproc // div32u16u()
   call main 
 
 SYMBOLS
@@ -1385,15 +1387,14 @@ SYMBOLS
 (word~) sin16s::$12
 (word~) sin16s::$13
 (word~) sin16s::$14
-(word/signed word/dword/signed dword~) sin16s::$15
+(word~) sin16s::$15
 (word~) sin16s::$16
-(word~) sin16s::$17
-(signed word~) sin16s::$18
+(signed word~) sin16s::$17
+(boolean~) sin16s::$18
 (boolean~) sin16s::$19
 (dword~) sin16s::$2
-(boolean~) sin16s::$20
+(signed word~) sin16s::$20
 (signed word~) sin16s::$21
-(signed word~) sin16s::$22
 (boolean~) sin16s::$3
 (boolean~) sin16s::$4
 (dword~) sin16s::$5
@@ -1609,8 +1610,26 @@ divr16u::@return: scope:[divr16u]  from divr16u::@6 divr16u::@7
 divr16u::@7: scope:[divr16u]  from
   to:divr16u::@return
 @4: scope:[]  from @3
-  (signed byte) rem8s ← (byte/signed byte/word/signed word/dword/signed dword) 0
   to:@5
+div32u16u: scope:[div32u16u]  from
+  (word~) div32u16u::$0 ← > (dword) div32u16u::dividend
+  (word~) div32u16u::$1 ← call divr16u (word~) div32u16u::$0 (word) div32u16u::divisor (byte/signed byte/word/signed word/dword/signed dword) 0 
+  (word) div32u16u::quotient_hi ← (word~) div32u16u::$1
+  (word~) div32u16u::$2 ← < (dword) div32u16u::dividend
+  (word~) div32u16u::$3 ← call divr16u (word~) div32u16u::$2 (word) div32u16u::divisor (word) rem16u 
+  (word) div32u16u::quotient_lo ← (word~) div32u16u::$3
+  (dword) div32u16u::quotient ← { (word) div32u16u::quotient_hi, (word) div32u16u::quotient_lo }
+  (dword) div32u16u::return ← (dword) div32u16u::quotient
+  to:div32u16u::@return
+div32u16u::@return: scope:[div32u16u]  from div32u16u div32u16u::@1
+  (dword) div32u16u::return ← (dword) div32u16u::return
+  return (dword) div32u16u::return
+  to:@return
+div32u16u::@1: scope:[div32u16u]  from
+  to:div32u16u::@return
+@5: scope:[]  from @4
+  (signed byte) rem8s ← (byte/signed byte/word/signed word/dword/signed dword) 0
+  to:@6
 div8s: scope:[div8s]  from
   (byte) div8s::neg ← (byte/signed byte/word/signed word/dword/signed dword) 0
   (byte) div8s::dividendu ← (byte/signed byte/word/signed word/dword/signed dword) 0
@@ -1682,9 +1701,9 @@ div8s::@13: scope:[div8s]  from
   to:div8s::@5
 div8s::@14: scope:[div8s]  from
   to:div8s::@6
-@5: scope:[]  from @4
+@6: scope:[]  from @5
   (signed word) rem16s ← (byte/signed byte/word/signed word/dword/signed dword) 0
-  to:@6
+  to:@7
 div16s: scope:[div16s]  from
   (byte) div16s::neg ← (byte/signed byte/word/signed word/dword/signed dword) 0
   (word) div16s::dividendu ← (byte/signed byte/word/signed word/dword/signed dword) 0
@@ -1756,8 +1775,8 @@ div16s::@13: scope:[div16s]  from
   to:div16s::@5
 div16s::@14: scope:[div16s]  from
   to:div16s::@6
-@6: scope:[]  from @5
-  to:@7
+@7: scope:[]  from @6
+  to:@8
 mul8u: scope:[mul8u]  from
   (word) mul8u::res ← (byte/signed byte/word/signed word/dword/signed dword) 0
   (word) mul8u::mb ← ((word)) (byte) mul8u::b
@@ -1797,8 +1816,8 @@ mul8u::@return: scope:[mul8u]  from mul8u::@3 mul8u::@9
   to:@return
 mul8u::@9: scope:[mul8u]  from
   to:mul8u::@return
-@7: scope:[]  from @6
-  to:@8
+@8: scope:[]  from @7
+  to:@9
 mul8s: scope:[mul8s]  from
   (byte~) mul8s::$0 ← ((byte)) (signed byte) mul8s::a
   (byte~) mul8s::$1 ← ((byte)) (signed byte) mul8s::b
@@ -1839,8 +1858,8 @@ mul8s::@return: scope:[mul8s]  from mul8s::@2 mul8s::@5
   to:@return
 mul8s::@5: scope:[mul8s]  from
   to:mul8s::@return
-@8: scope:[]  from @7
-  to:@9
+@9: scope:[]  from @8
+  to:@10
 mul16u: scope:[mul16u]  from
   (dword) mul16u::res ← (byte/signed byte/word/signed word/dword/signed dword) 0
   (dword) mul16u::mb ← ((dword)) (word) mul16u::b
@@ -1880,8 +1899,8 @@ mul16u::@return: scope:[mul16u]  from mul16u::@3 mul16u::@9
   to:@return
 mul16u::@9: scope:[mul16u]  from
   to:mul16u::@return
-@9: scope:[]  from @8
-  to:@10
+@10: scope:[]  from @9
+  to:@11
 mul16s: scope:[mul16s]  from
   (word~) mul16s::$0 ← ((word)) (signed word) mul16s::a
   (word~) mul16s::$1 ← ((word)) (signed word) mul16s::b
@@ -1922,11 +1941,11 @@ mul16s::@return: scope:[mul16s]  from mul16s::@2 mul16s::@5
   to:@return
 mul16s::@5: scope:[mul16s]  from
   to:mul16s::@return
-@10: scope:[]  from @9
+@11: scope:[]  from @10
   (byte*) SCREEN ← ((byte*)) (word/signed word/dword/signed dword) 1024
   (byte*) line_cursor ← (byte*) SCREEN
   (byte*) char_cursor ← (byte*) line_cursor
-  to:@11
+  to:@12
 print_str: scope:[print_str]  from
   to:print_str::@1
 print_str::@1: scope:[print_str]  from print_str print_str::@2
@@ -1949,8 +1968,8 @@ print_str::@6: scope:[print_str]  from
 print_str::@return: scope:[print_str]  from print_str::@3
   return 
   to:@return
-@11: scope:[]  from @10
-  to:@12
+@12: scope:[]  from @11
+  to:@13
 print_ln: scope:[print_ln]  from
   to:print_ln::@1
 print_ln::@1: scope:[print_ln]  from print_ln print_ln::@1
@@ -1965,8 +1984,8 @@ print_ln::@2: scope:[print_ln]  from print_ln::@1
 print_ln::@return: scope:[print_ln]  from print_ln::@2
   return 
   to:@return
-@12: scope:[]  from @11
-  to:@13
+@13: scope:[]  from @12
+  to:@14
 print_sword: scope:[print_sword]  from
   (boolean~) print_sword::$0 ← (signed word) print_sword::w < (byte/signed byte/word/signed word/dword/signed dword) 0
   (boolean~) print_sword::$1 ← ! (boolean~) print_sword::$0
@@ -1984,8 +2003,8 @@ print_sword::@2: scope:[print_sword]  from print_sword
 print_sword::@return: scope:[print_sword]  from print_sword::@1
   return 
   to:@return
-@13: scope:[]  from @12
-  to:@14
+@14: scope:[]  from @13
+  to:@15
 print_sbyte: scope:[print_sbyte]  from
   (boolean~) print_sbyte::$0 ← (signed byte) print_sbyte::b < (byte/signed byte/word/signed word/dword/signed dword) 0
   (boolean~) print_sbyte::$1 ← ! (boolean~) print_sbyte::$0
@@ -2003,8 +2022,8 @@ print_sbyte::@2: scope:[print_sbyte]  from print_sbyte
 print_sbyte::@return: scope:[print_sbyte]  from print_sbyte::@1
   return 
   to:@return
-@14: scope:[]  from @13
-  to:@15
+@15: scope:[]  from @14
+  to:@16
 print_word: scope:[print_word]  from
   (byte~) print_word::$0 ← > (word) print_word::w
   (void~) print_word::$1 ← call print_byte (byte~) print_word::$0 
@@ -2014,8 +2033,8 @@ print_word: scope:[print_word]  from
 print_word::@return: scope:[print_word]  from print_word
   return 
   to:@return
-@15: scope:[]  from @14
-  to:@16
+@16: scope:[]  from @15
+  to:@17
 print_dword: scope:[print_dword]  from
   (word~) print_dword::$0 ← > (dword) print_dword::dw
   (void~) print_dword::$1 ← call print_word (word~) print_dword::$0 
@@ -2025,8 +2044,8 @@ print_dword: scope:[print_dword]  from
 print_dword::@return: scope:[print_dword]  from print_dword
   return 
   to:@return
-@16: scope:[]  from @15
-  to:@17
+@17: scope:[]  from @16
+  to:@18
 print_sdword: scope:[print_sdword]  from
   (boolean~) print_sdword::$0 ← (signed dword) print_sdword::dw < (byte/signed byte/word/signed word/dword/signed dword) 0
   (boolean~) print_sdword::$1 ← ! (boolean~) print_sdword::$0
@@ -2044,8 +2063,8 @@ print_sdword::@2: scope:[print_sdword]  from print_sdword
 print_sdword::@return: scope:[print_sdword]  from print_sdword::@1
   return 
   to:@return
-@17: scope:[]  from @16
-  to:@18
+@18: scope:[]  from @17
+  to:@19
 print_byte: scope:[print_byte]  from
   (byte[]) print_byte::hextab ← (string) "0123456789abcdef"
   (byte~) print_byte::$0 ← (byte) print_byte::b >> (byte/signed byte/word/signed word/dword/signed dword) 4
@@ -2056,8 +2075,8 @@ print_byte: scope:[print_byte]  from
 print_byte::@return: scope:[print_byte]  from print_byte
   return 
   to:@return
-@18: scope:[]  from @17
-  to:@19
+@19: scope:[]  from @18
+  to:@20
 print_char: scope:[print_char]  from
   *((byte*) char_cursor) ← (byte) print_char::ch
   (byte*) char_cursor ← ++ (byte*) char_cursor
@@ -2065,8 +2084,8 @@ print_char: scope:[print_char]  from
 print_char::@return: scope:[print_char]  from print_char
   return 
   to:@return
-@19: scope:[]  from @18
-  to:@20
+@20: scope:[]  from @19
+  to:@21
 print_cls: scope:[print_cls]  from
   (byte*) print_cls::sc ← (byte*) SCREEN
   to:print_cls::@1
@@ -2084,8 +2103,8 @@ print_cls::@2: scope:[print_cls]  from print_cls::@1
 print_cls::@return: scope:[print_cls]  from print_cls::@2
   return 
   to:@return
-@20: scope:[]  from @19
-  to:@21
+@21: scope:[]  from @20
+  to:@22
 main: scope:[main]  from
   (word) main::wavelength ← (byte/signed byte/word/signed word/dword/signed dword) 120
   (signed word[120]) main::sintab1 ← { fill( 120, 0) }
@@ -2117,14 +2136,14 @@ main::@4: scope:[main]  from main::@2
 main::@return: scope:[main]  from main::@4
   return 
   to:@return
-@21: scope:[]  from @20
+@22: scope:[]  from @21
   (dword) PI2_u4f28 ← (dword/signed dword) 1686629713
   (dword) PI_u4f28 ← (dword/signed dword) 843314857
   (dword) PI_HALF_u4f28 ← (dword/signed dword) 421657428
   (word) PI2_u4f12 ← (word/signed word/dword/signed dword) 25736
   (word) PI_u4f12 ← (word/signed word/dword/signed dword) 12868
   (word) PI_HALF_u4f12 ← (word/signed word/dword/signed dword) 6434
-  to:@22
+  to:@23
 sin16s_gen: scope:[sin16s_gen]  from
   (dword~) sin16s_gen::$0 ← call div32u16u (dword) PI2_u4f28 (word) sin16s_gen::wavelength 
   (dword) sin16s_gen::step ← (dword~) sin16s_gen::$0
@@ -2147,8 +2166,8 @@ sin16s_gen::@2: scope:[sin16s_gen]  from sin16s_gen::@1
 sin16s_gen::@return: scope:[sin16s_gen]  from sin16s_gen::@2
   return 
   to:@return
-@22: scope:[]  from @21
-  to:@23
+@23: scope:[]  from @22
+  to:@24
 sin16s: scope:[sin16s]  from
   (byte) sin16s::isUpper ← (byte/signed byte/word/signed word/dword/signed dword) 0
   (boolean~) sin16s::$0 ← (dword) sin16s::x >= (dword) PI_u4f28
@@ -2182,16 +2201,15 @@ sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
   (word) sin16s::x4 ← (word~) sin16s::$13
   (word~) sin16s::$14 ← call mul_u16_sel (word) sin16s::x4 (word) sin16s::x1 (byte/signed byte/word/signed word/dword/signed dword) 0 
   (word) sin16s::x5 ← (word~) sin16s::$14
-  (word/signed word/dword/signed dword~) sin16s::$15 ← (dword/signed dword) 65536 / (byte/word/signed word/dword/signed dword) 128
-  (word~) sin16s::$16 ← call mul_u16_sel (word) sin16s::x5 (word/signed word/dword/signed dword~) sin16s::$15 (byte/signed byte/word/signed word/dword/signed dword) 3 
-  (word) sin16s::x5_128 ← (word~) sin16s::$16
-  (word~) sin16s::$17 ← (word) sin16s::usinx + (word) sin16s::x5_128
-  (word) sin16s::usinx ← (word~) sin16s::$17
-  (signed word~) sin16s::$18 ← ((signed word)) (word) sin16s::usinx
-  (signed word) sin16s::sinx ← (signed word~) sin16s::$18
-  (boolean~) sin16s::$19 ← (byte) sin16s::isUpper != (byte/signed byte/word/signed word/dword/signed dword) 0
-  (boolean~) sin16s::$20 ← ! (boolean~) sin16s::$19
-  if((boolean~) sin16s::$20) goto sin16s::@3
+  (word~) sin16s::$15 ← (word) sin16s::x5 >> (byte/signed byte/word/signed word/dword/signed dword) 4
+  (word) sin16s::x5_128 ← (word~) sin16s::$15
+  (word~) sin16s::$16 ← (word) sin16s::usinx + (word) sin16s::x5_128
+  (word) sin16s::usinx ← (word~) sin16s::$16
+  (signed word~) sin16s::$17 ← ((signed word)) (word) sin16s::usinx
+  (signed word) sin16s::sinx ← (signed word~) sin16s::$17
+  (boolean~) sin16s::$18 ← (byte) sin16s::isUpper != (byte/signed byte/word/signed word/dword/signed dword) 0
+  (boolean~) sin16s::$19 ← ! (boolean~) sin16s::$18
+  if((boolean~) sin16s::$19) goto sin16s::@3
   to:sin16s::@6
 sin16s::@5: scope:[sin16s]  from sin16s::@1
   (dword~) sin16s::$5 ← (dword) PI_u4f28 - (dword) sin16s::x
@@ -2201,9 +2219,9 @@ sin16s::@3: scope:[sin16s]  from sin16s::@2 sin16s::@6
   (signed word) sin16s::return ← (signed word) sin16s::sinx
   to:sin16s::@return
 sin16s::@6: scope:[sin16s]  from sin16s::@2
-  (signed word~) sin16s::$21 ← ((signed word)) (word) sin16s::usinx
-  (signed word~) sin16s::$22 ← - (signed word~) sin16s::$21
-  (signed word) sin16s::sinx ← (signed word~) sin16s::$22
+  (signed word~) sin16s::$20 ← ((signed word)) (word) sin16s::usinx
+  (signed word~) sin16s::$21 ← - (signed word~) sin16s::$20
+  (signed word) sin16s::sinx ← (signed word~) sin16s::$21
   to:sin16s::@3
 sin16s::@return: scope:[sin16s]  from sin16s::@3 sin16s::@7
   (signed word) sin16s::return ← (signed word) sin16s::return
@@ -2211,8 +2229,8 @@ sin16s::@return: scope:[sin16s]  from sin16s::@3 sin16s::@7
   to:@return
 sin16s::@7: scope:[sin16s]  from
   to:sin16s::@return
-@23: scope:[]  from @22
-  to:@24
+@24: scope:[]  from @23
+  to:@25
 sin16ss_gen: scope:[sin16ss_gen]  from
   (dword~) sin16ss_gen::$0 ← call div32u16u (dword) PI2_u4f28 (word) sin16ss_gen::wavelength 
   (dword) sin16ss_gen::step ← (dword~) sin16ss_gen::$0
@@ -2290,8 +2308,8 @@ sin16ss_gen::@10: scope:[sin16ss_gen]  from sin16ss_gen::@5
 sin16ss_gen::@return: scope:[sin16ss_gen]  from sin16ss_gen::@10
   return 
   to:@return
-@24: scope:[]  from @23
-  to:@25
+@25: scope:[]  from @24
+  to:@26
 mul_u16_sel: scope:[mul_u16_sel]  from
   (dword~) mul_u16_sel::$0 ← call mul16u (word) mul_u16_sel::v1 (word) mul_u16_sel::v2 
   (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select
@@ -2304,24 +2322,6 @@ mul_u16_sel::@return: scope:[mul_u16_sel]  from mul_u16_sel mul_u16_sel::@1
   to:@return
 mul_u16_sel::@1: scope:[mul_u16_sel]  from
   to:mul_u16_sel::@return
-@25: scope:[]  from @24
-  to:@26
-div32u16u: scope:[div32u16u]  from
-  (word~) div32u16u::$0 ← > (dword) div32u16u::dividend
-  (word~) div32u16u::$1 ← call divr16u (word~) div32u16u::$0 (word) div32u16u::divisor (byte/signed byte/word/signed word/dword/signed dword) 0 
-  (word) div32u16u::quotient_hi ← (word~) div32u16u::$1
-  (word~) div32u16u::$2 ← < (dword) div32u16u::dividend
-  (word~) div32u16u::$3 ← call divr16u (word~) div32u16u::$2 (word) div32u16u::divisor (word) rem16u 
-  (word) div32u16u::quotient_lo ← (word~) div32u16u::$3
-  (dword) div32u16u::quotient ← { (word) div32u16u::quotient_hi, (word) div32u16u::quotient_lo }
-  (dword) div32u16u::return ← (dword) div32u16u::quotient
-  to:div32u16u::@return
-div32u16u::@return: scope:[div32u16u]  from div32u16u div32u16u::@1
-  (dword) div32u16u::return ← (dword) div32u16u::return
-  return (dword) div32u16u::return
-  to:@return
-div32u16u::@1: scope:[div32u16u]  from
-  to:div32u16u::@return
 @26: scope:[]  from @25
   call main 
   to:@end
@@ -2341,8 +2341,8 @@ Removing unused procedure mul8u
 Removing unused procedure print_dword
 Removing unused procedure divr8u
 Eliminating unused variable (byte) rem8u and assignment [0] (byte) rem8u ← (byte/signed byte/word/signed word/dword/signed dword) 0
-Eliminating unused variable (signed byte) rem8s and assignment [30] (signed byte) rem8s ← (byte/signed byte/word/signed word/dword/signed dword) 0
-Eliminating unused variable (signed word) rem16s and assignment [31] (signed word) rem16s ← (byte/signed byte/word/signed word/dword/signed dword) 0
+Eliminating unused variable (signed byte) rem8s and assignment [40] (signed byte) rem8s ← (byte/signed byte/word/signed word/dword/signed dword) 0
+Eliminating unused variable (signed word) rem16s and assignment [41] (signed word) rem16s ← (byte/signed byte/word/signed word/dword/signed dword) 0
 Eliminating unused variable - keeping the call (void~) print_sword::$5
 Eliminating unused variable - keeping the call (void~) print_sword::$2
 Eliminating unused variable - keeping the call (void~) print_word::$1
@@ -2354,9 +2354,9 @@ Eliminating unused variable - keeping the call (void~) main::$1
 Eliminating unused variable - keeping the call (void~) main::$5
 Eliminating unused variable - keeping the call (void~) main::$6
 Eliminating unused variable - keeping the call (void~) main::$4
-Eliminating unused variable (word) PI2_u4f12 and assignment [112] (word) PI2_u4f12 ← (word/signed word/dword/signed dword) 25736
-Eliminating unused variable (word) PI_u4f12 and assignment [113] (word) PI_u4f12 ← (word/signed word/dword/signed dword) 12868
-Eliminating unused variable (word) PI_HALF_u4f12 and assignment [114] (word) PI_HALF_u4f12 ← (word/signed word/dword/signed dword) 6434
+Eliminating unused variable (word) PI2_u4f12 and assignment [122] (word) PI2_u4f12 ← (word/signed word/dword/signed dword) 25736
+Eliminating unused variable (word) PI_u4f12 and assignment [123] (word) PI_u4f12 ← (word/signed word/dword/signed dword) 12868
+Eliminating unused variable (word) PI_HALF_u4f12 and assignment [124] (word) PI_HALF_u4f12 ← (word/signed word/dword/signed dword) 6434
 Creating constant string variable for inline (const string) print_byte::$4 "0123456789abcdef"
 Creating constant string variable for inline (const string) main::str "   @"
 Creating constant string variable for inline (const string) main::str1 " @"
@@ -2364,20 +2364,21 @@ Removing empty block @1
 Removing empty block @3
 Removing empty block divr16u::@7
 Removing empty block @4
+Removing empty block div32u16u::@1
 Removing empty block @5
 Removing empty block @6
 Removing empty block @7
 Removing empty block @8
+Removing empty block @9
 Removing empty block mul16u::@5
 Removing empty block mul16u::@6
 Removing empty block mul16u::@8
 Removing empty block mul16u::@9
-Removing empty block @9
+Removing empty block @10
 Removing empty block print_str::@4
 Removing empty block print_str::@3
 Removing empty block print_str::@5
 Removing empty block print_str::@6
-Removing empty block @11
 Removing empty block @12
 Removing empty block @13
 Removing empty block @14
@@ -2387,17 +2388,17 @@ Removing empty block @17
 Removing empty block @18
 Removing empty block @19
 Removing empty block @20
+Removing empty block @21
 Removing empty block main::@4
 Removing empty block sin16s_gen::@2
-Removing empty block @22
-Removing empty block sin16s::@7
 Removing empty block @23
+Removing empty block sin16s::@7
 Removing empty block @24
-Removing empty block mul_u16_sel::@1
 Removing empty block @25
-Removing empty block div32u16u::@1
+Removing empty block mul_u16_sel::@1
 PROCEDURE MODIFY VARIABLE ANALYSIS
 divr16u modifies rem16u
+div32u16u modifies rem16u
 print_str modifies char_cursor
 print_sword modifies char_cursor
 print_word modifies char_cursor
@@ -2409,7 +2410,6 @@ main modifies rem16u
 main modifies line_cursor
 main modifies char_cursor
 sin16s_gen modifies rem16u
-div32u16u modifies rem16u
 
 Completing Phi functions...
 Completing Phi functions...
@@ -2418,14 +2418,13 @@ Completing Phi functions...
 Completing Phi functions...
 Completing Phi functions...
 Completing Phi functions...
-Completing Phi functions...
 
 CONTROL FLOW GRAPH SSA WITH ASSIGNMENT CALL & RETURN
 @begin: scope:[]  from
   to:@2
 @2: scope:[]  from @begin
   (word) rem16u#0 ← (byte/signed byte/word/signed word/dword/signed dword) 0
-  to:@10
+  to:@11
 divr16u: scope:[divr16u]  from div32u16u div32u16u::@2
   (word) divr16u::divisor#6 ← phi( div32u16u/(word) divr16u::divisor#0 div32u16u::@2/(word) divr16u::divisor#1 )
   (word) divr16u::dividend#5 ← phi( div32u16u/(word) divr16u::dividend#1 div32u16u::@2/(word) divr16u::dividend#2 )
@@ -2503,6 +2502,49 @@ divr16u::@return: scope:[divr16u]  from divr16u::@6
   (word) rem16u#2 ← (word) rem16u#11
   return 
   to:@return
+div32u16u: scope:[div32u16u]  from sin16s_gen
+  (word) rem16u#20 ← phi( sin16s_gen/(word) rem16u#23 )
+  (word) div32u16u::divisor#1 ← phi( sin16s_gen/(word) div32u16u::divisor#0 )
+  (dword) div32u16u::dividend#1 ← phi( sin16s_gen/(dword) div32u16u::dividend#0 )
+  (word~) div32u16u::$0 ← > (dword) div32u16u::dividend#1
+  (word) divr16u::dividend#1 ← (word~) div32u16u::$0
+  (word) divr16u::divisor#0 ← (word) div32u16u::divisor#1
+  (word) divr16u::rem#3 ← (byte/signed byte/word/signed word/dword/signed dword) 0
+  call divr16u param-assignment
+  (word) divr16u::return#2 ← (word) divr16u::return#1
+  to:div32u16u::@2
+div32u16u::@2: scope:[div32u16u]  from div32u16u
+  (word) div32u16u::divisor#2 ← phi( div32u16u/(word) div32u16u::divisor#1 )
+  (dword) div32u16u::dividend#2 ← phi( div32u16u/(dword) div32u16u::dividend#1 )
+  (word) rem16u#12 ← phi( div32u16u/(word) rem16u#2 )
+  (word) divr16u::return#5 ← phi( div32u16u/(word) divr16u::return#2 )
+  (word~) div32u16u::$1 ← (word) divr16u::return#5
+  (word) rem16u#3 ← (word) rem16u#12
+  (word) div32u16u::quotient_hi#0 ← (word~) div32u16u::$1
+  (word~) div32u16u::$2 ← < (dword) div32u16u::dividend#2
+  (word) divr16u::dividend#2 ← (word~) div32u16u::$2
+  (word) divr16u::divisor#1 ← (word) div32u16u::divisor#2
+  (word) divr16u::rem#4 ← (word) rem16u#3
+  call divr16u param-assignment
+  (word) divr16u::return#3 ← (word) divr16u::return#1
+  to:div32u16u::@3
+div32u16u::@3: scope:[div32u16u]  from div32u16u::@2
+  (word) div32u16u::quotient_hi#1 ← phi( div32u16u::@2/(word) div32u16u::quotient_hi#0 )
+  (word) rem16u#13 ← phi( div32u16u::@2/(word) rem16u#2 )
+  (word) divr16u::return#6 ← phi( div32u16u::@2/(word) divr16u::return#3 )
+  (word~) div32u16u::$3 ← (word) divr16u::return#6
+  (word) rem16u#4 ← (word) rem16u#13
+  (word) div32u16u::quotient_lo#0 ← (word~) div32u16u::$3
+  (dword) div32u16u::quotient#0 ← { (word) div32u16u::quotient_hi#1, (word) div32u16u::quotient_lo#0 }
+  (dword) div32u16u::return#0 ← (dword) div32u16u::quotient#0
+  to:div32u16u::@return
+div32u16u::@return: scope:[div32u16u]  from div32u16u::@3
+  (word) rem16u#14 ← phi( div32u16u::@3/(word) rem16u#4 )
+  (dword) div32u16u::return#3 ← phi( div32u16u::@3/(dword) div32u16u::return#0 )
+  (dword) div32u16u::return#1 ← (dword) div32u16u::return#3
+  (word) rem16u#5 ← (word) rem16u#14
+  return 
+  to:@return
 mul16u: scope:[mul16u]  from mul_u16_sel
   (word) mul16u::a#5 ← phi( mul_u16_sel/(word) mul16u::a#1 )
   (word) mul16u::b#1 ← phi( mul_u16_sel/(word) mul16u::b#0 )
@@ -2550,12 +2592,12 @@ mul16u::@return: scope:[mul16u]  from mul16u::@3
   (dword) mul16u::return#1 ← (dword) mul16u::return#3
   return 
   to:@return
-@10: scope:[]  from @2
+@11: scope:[]  from @2
   (word) rem16u#30 ← phi( @2/(word) rem16u#0 )
   (byte*) SCREEN#0 ← ((byte*)) (word/signed word/dword/signed dword) 1024
   (byte*) line_cursor#0 ← (byte*) SCREEN#0
   (byte*) char_cursor#0 ← (byte*) line_cursor#0
-  to:@21
+  to:@22
 print_str: scope:[print_str]  from main::@3 main::@7
   (byte*) char_cursor#51 ← phi( main::@3/(byte*) char_cursor#49 main::@7/(byte*) char_cursor#17 )
   (byte*) print_str::str#5 ← phi( main::@3/(byte*) print_str::str#2 main::@7/(byte*) print_str::str#1 )
@@ -2699,7 +2741,7 @@ print_cls::@return: scope:[print_cls]  from print_cls::@2
 main: scope:[main]  from @26
   (byte*) char_cursor#53 ← phi( @26/(byte*) char_cursor#50 )
   (byte*) line_cursor#13 ← phi( @26/(byte*) line_cursor#12 )
-  (word) rem16u#20 ← phi( @26/(word) rem16u#25 )
+  (word) rem16u#21 ← phi( @26/(word) rem16u#25 )
   (word) main::wavelength#0 ← (byte/signed byte/word/signed word/dword/signed dword) 120
   (signed word[120]) main::sintab1#0 ← { fill( 120, 0) }
   (signed word*) sin16s_gen::sintab#0 ← (signed word[120]) main::sintab1#0
@@ -2710,12 +2752,12 @@ main::@5: scope:[main]  from main
   (word) main::wavelength#8 ← phi( main/(word) main::wavelength#0 )
   (byte*) char_cursor#47 ← phi( main/(byte*) char_cursor#53 )
   (byte*) line_cursor#10 ← phi( main/(byte*) line_cursor#13 )
-  (word) rem16u#12 ← phi( main/(word) rem16u#6 )
-  (word) rem16u#3 ← (word) rem16u#12
+  (word) rem16u#15 ← phi( main/(word) rem16u#9 )
+  (word) rem16u#6 ← (word) rem16u#15
   call print_cls param-assignment
   to:main::@6
 main::@6: scope:[main]  from main::@5
-  (word) rem16u#33 ← phi( main::@5/(word) rem16u#3 )
+  (word) rem16u#33 ← phi( main::@5/(word) rem16u#6 )
   (word) main::wavelength#6 ← phi( main::@5/(word) main::wavelength#8 )
   (byte*) char_cursor#36 ← phi( main::@5/(byte*) char_cursor#15 )
   (byte*) line_cursor#7 ← phi( main::@5/(byte*) line_cursor#2 )
@@ -2725,7 +2767,7 @@ main::@6: scope:[main]  from main::@5
   to:main::@1
 main::@1: scope:[main]  from main::@6 main::@8
   (byte*) line_cursor#17 ← phi( main::@6/(byte*) line_cursor#3 main::@8/(byte*) line_cursor#11 )
-  (word) rem16u#31 ← phi( main::@6/(word) rem16u#33 main::@8/(word) rem16u#21 )
+  (word) rem16u#31 ← phi( main::@6/(word) rem16u#33 main::@8/(word) rem16u#22 )
   (word) main::wavelength#4 ← phi( main::@6/(word) main::wavelength#6 main::@8/(word) main::wavelength#1 )
   (byte*) char_cursor#54 ← phi( main::@6/(byte*) char_cursor#16 main::@8/(byte*) char_cursor#18 )
   (signed word*) main::st1#2 ← phi( main::@6/(signed word*) main::st1#0 main::@8/(signed word*) main::st1#1 )
@@ -2756,7 +2798,7 @@ main::@7: scope:[main]  from main::@2
   to:main::@8
 main::@8: scope:[main]  from main::@7
   (byte*) line_cursor#11 ← phi( main::@7/(byte*) line_cursor#14 )
-  (word) rem16u#21 ← phi( main::@7/(word) rem16u#26 )
+  (word) rem16u#22 ← phi( main::@7/(word) rem16u#26 )
   (word) main::wavelength#1 ← phi( main::@7/(word) main::wavelength#2 )
   (signed word*) main::st1#3 ← phi( main::@7/(signed word*) main::st1#4 )
   (byte*) char_cursor#38 ← phi( main::@7/(byte*) char_cursor#2 )
@@ -2790,42 +2832,42 @@ main::@9: scope:[main]  from main::@3
 main::@return: scope:[main]  from main::@8
   (byte*) char_cursor#40 ← phi( main::@8/(byte*) char_cursor#18 )
   (byte*) line_cursor#8 ← phi( main::@8/(byte*) line_cursor#11 )
-  (word) rem16u#13 ← phi( main::@8/(word) rem16u#21 )
-  (word) rem16u#4 ← (word) rem16u#13
+  (word) rem16u#16 ← phi( main::@8/(word) rem16u#22 )
+  (word) rem16u#7 ← (word) rem16u#16
   (byte*) line_cursor#4 ← (byte*) line_cursor#8
   (byte*) char_cursor#20 ← (byte*) char_cursor#40
   return 
   to:@return
-@21: scope:[]  from @10
-  (byte*) char_cursor#55 ← phi( @10/(byte*) char_cursor#0 )
-  (byte*) line_cursor#15 ← phi( @10/(byte*) line_cursor#0 )
-  (word) rem16u#28 ← phi( @10/(word) rem16u#30 )
+@22: scope:[]  from @11
+  (byte*) char_cursor#55 ← phi( @11/(byte*) char_cursor#0 )
+  (byte*) line_cursor#15 ← phi( @11/(byte*) line_cursor#0 )
+  (word) rem16u#28 ← phi( @11/(word) rem16u#30 )
   (dword) PI2_u4f28#0 ← (dword/signed dword) 1686629713
   (dword) PI_u4f28#0 ← (dword/signed dword) 843314857
   (dword) PI_HALF_u4f28#0 ← (dword/signed dword) 421657428
   to:@26
 sin16s_gen: scope:[sin16s_gen]  from main
   (signed word*) sin16s_gen::sintab#5 ← phi( main/(signed word*) sin16s_gen::sintab#0 )
-  (word) rem16u#22 ← phi( main/(word) rem16u#20 )
+  (word) rem16u#23 ← phi( main/(word) rem16u#21 )
   (word) sin16s_gen::wavelength#1 ← phi( main/(word) sin16s_gen::wavelength#0 )
   (dword) div32u16u::dividend#0 ← (dword) PI2_u4f28#0
   (word) div32u16u::divisor#0 ← (word) sin16s_gen::wavelength#1
   call div32u16u param-assignment
-  (dword) div32u16u::return#0 ← (dword) div32u16u::return#2
+  (dword) div32u16u::return#2 ← (dword) div32u16u::return#1
   to:sin16s_gen::@3
 sin16s_gen::@3: scope:[sin16s_gen]  from sin16s_gen
   (word) sin16s_gen::wavelength#4 ← phi( sin16s_gen/(word) sin16s_gen::wavelength#1 )
   (signed word*) sin16s_gen::sintab#4 ← phi( sin16s_gen/(signed word*) sin16s_gen::sintab#5 )
-  (word) rem16u#14 ← phi( sin16s_gen/(word) rem16u#9 )
-  (dword) div32u16u::return#3 ← phi( sin16s_gen/(dword) div32u16u::return#0 )
-  (dword~) sin16s_gen::$0 ← (dword) div32u16u::return#3
-  (word) rem16u#5 ← (word) rem16u#14
+  (word) rem16u#17 ← phi( sin16s_gen/(word) rem16u#5 )
+  (dword) div32u16u::return#4 ← phi( sin16s_gen/(dword) div32u16u::return#2 )
+  (dword~) sin16s_gen::$0 ← (dword) div32u16u::return#4
+  (word) rem16u#8 ← (word) rem16u#17
   (dword) sin16s_gen::step#0 ← (dword~) sin16s_gen::$0
   (dword) sin16s_gen::x#0 ← (byte/signed byte/word/signed word/dword/signed dword) 0
   (word) sin16s_gen::i#0 ← (byte/signed byte/word/signed word/dword/signed dword) 0
   to:sin16s_gen::@1
 sin16s_gen::@1: scope:[sin16s_gen]  from sin16s_gen::@3 sin16s_gen::@4
-  (word) rem16u#27 ← phi( sin16s_gen::@3/(word) rem16u#5 sin16s_gen::@4/(word) rem16u#23 )
+  (word) rem16u#27 ← phi( sin16s_gen::@3/(word) rem16u#8 sin16s_gen::@4/(word) rem16u#24 )
   (word) sin16s_gen::wavelength#3 ← phi( sin16s_gen::@3/(word) sin16s_gen::wavelength#4 sin16s_gen::@4/(word) sin16s_gen::wavelength#2 )
   (word) sin16s_gen::i#3 ← phi( sin16s_gen::@3/(word) sin16s_gen::i#0 sin16s_gen::@4/(word) sin16s_gen::i#1 )
   (dword) sin16s_gen::step#2 ← phi( sin16s_gen::@3/(dword) sin16s_gen::step#0 sin16s_gen::@4/(dword) sin16s_gen::step#1 )
@@ -2836,7 +2878,7 @@ sin16s_gen::@1: scope:[sin16s_gen]  from sin16s_gen::@3 sin16s_gen::@4
   (signed word) sin16s::return#0 ← (signed word) sin16s::return#2
   to:sin16s_gen::@4
 sin16s_gen::@4: scope:[sin16s_gen]  from sin16s_gen::@1
-  (word) rem16u#23 ← phi( sin16s_gen::@1/(word) rem16u#27 )
+  (word) rem16u#24 ← phi( sin16s_gen::@1/(word) rem16u#27 )
   (word) sin16s_gen::wavelength#2 ← phi( sin16s_gen::@1/(word) sin16s_gen::wavelength#3 )
   (word) sin16s_gen::i#2 ← phi( sin16s_gen::@1/(word) sin16s_gen::i#3 )
   (dword) sin16s_gen::step#1 ← phi( sin16s_gen::@1/(dword) sin16s_gen::step#2 )
@@ -2854,8 +2896,8 @@ sin16s_gen::@4: scope:[sin16s_gen]  from sin16s_gen::@1
   if((boolean~) sin16s_gen::$4) goto sin16s_gen::@1
   to:sin16s_gen::@return
 sin16s_gen::@return: scope:[sin16s_gen]  from sin16s_gen::@4
-  (word) rem16u#15 ← phi( sin16s_gen::@4/(word) rem16u#23 )
-  (word) rem16u#6 ← (word) rem16u#15
+  (word) rem16u#18 ← phi( sin16s_gen::@4/(word) rem16u#24 )
+  (word) rem16u#9 ← (word) rem16u#18
   return 
   to:@return
 sin16s: scope:[sin16s]  from sin16s_gen::@1
@@ -2866,7 +2908,7 @@ sin16s: scope:[sin16s]  from sin16s_gen::@1
   if((boolean~) sin16s::$1) goto sin16s::@1
   to:sin16s::@4
 sin16s::@1: scope:[sin16s]  from sin16s sin16s::@4
-  (byte) sin16s::isUpper#9 ← phi( sin16s/(byte) sin16s::isUpper#0 sin16s::@4/(byte) sin16s::isUpper#1 )
+  (byte) sin16s::isUpper#8 ← phi( sin16s/(byte) sin16s::isUpper#0 sin16s::@4/(byte) sin16s::isUpper#1 )
   (dword) sin16s::x#4 ← phi( sin16s/(dword) sin16s::x#3 sin16s::@4/(dword) sin16s::x#1 )
   (boolean~) sin16s::$3 ← (dword) sin16s::x#4 >= (dword) PI_HALF_u4f28#0
   (boolean~) sin16s::$4 ← ! (boolean~) sin16s::$3
@@ -2879,7 +2921,7 @@ sin16s::@4: scope:[sin16s]  from sin16s
   (byte) sin16s::isUpper#1 ← (byte/signed byte/word/signed word/dword/signed dword) 1
   to:sin16s::@1
 sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
-  (byte) sin16s::isUpper#8 ← phi( sin16s::@1/(byte) sin16s::isUpper#9 sin16s::@5/(byte) sin16s::isUpper#10 )
+  (byte) sin16s::isUpper#7 ← phi( sin16s::@1/(byte) sin16s::isUpper#8 sin16s::@5/(byte) sin16s::isUpper#9 )
   (dword) sin16s::x#6 ← phi( sin16s::@1/(dword) sin16s::x#4 sin16s::@5/(dword) sin16s::x#2 )
   (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3
   (word~) sin16s::$7 ← > (dword~) sin16s::$6
@@ -2888,39 +2930,39 @@ sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
   (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0
   (byte) mul_u16_sel::select#0 ← (byte/signed byte/word/signed word/dword/signed dword) 0
   call mul_u16_sel param-assignment
-  (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#7
+  (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#6
   to:sin16s::@8
 sin16s::@8: scope:[sin16s]  from sin16s::@2
-  (byte) sin16s::isUpper#7 ← phi( sin16s::@2/(byte) sin16s::isUpper#8 )
+  (byte) sin16s::isUpper#6 ← phi( sin16s::@2/(byte) sin16s::isUpper#7 )
   (word) sin16s::x1#1 ← phi( sin16s::@2/(word) sin16s::x1#0 )
-  (word) mul_u16_sel::return#8 ← phi( sin16s::@2/(word) mul_u16_sel::return#0 )
-  (word~) sin16s::$8 ← (word) mul_u16_sel::return#8
+  (word) mul_u16_sel::return#7 ← phi( sin16s::@2/(word) mul_u16_sel::return#0 )
+  (word~) sin16s::$8 ← (word) mul_u16_sel::return#7
   (word) sin16s::x2#0 ← (word~) sin16s::$8
   (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0
   (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#1
   (byte) mul_u16_sel::select#1 ← (byte/signed byte/word/signed word/dword/signed dword) 1
   call mul_u16_sel param-assignment
-  (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#7
+  (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#6
   to:sin16s::@9
 sin16s::@9: scope:[sin16s]  from sin16s::@8
-  (byte) sin16s::isUpper#6 ← phi( sin16s::@8/(byte) sin16s::isUpper#7 )
+  (byte) sin16s::isUpper#5 ← phi( sin16s::@8/(byte) sin16s::isUpper#6 )
   (word) sin16s::x1#4 ← phi( sin16s::@8/(word) sin16s::x1#1 )
-  (word) mul_u16_sel::return#9 ← phi( sin16s::@8/(word) mul_u16_sel::return#1 )
-  (word~) sin16s::$9 ← (word) mul_u16_sel::return#9
+  (word) mul_u16_sel::return#8 ← phi( sin16s::@8/(word) mul_u16_sel::return#1 )
+  (word~) sin16s::$9 ← (word) mul_u16_sel::return#8
   (word) sin16s::x3#0 ← (word~) sin16s::$9
   (word/signed word/dword/signed dword~) sin16s::$10 ← (dword/signed dword) 65536 / (byte/signed byte/word/signed word/dword/signed dword) 6
   (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0
   (word) mul_u16_sel::v2#2 ← (word/signed word/dword/signed dword~) sin16s::$10
   (byte) mul_u16_sel::select#2 ← (byte/signed byte/word/signed word/dword/signed dword) 1
   call mul_u16_sel param-assignment
-  (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#7
+  (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#6
   to:sin16s::@10
 sin16s::@10: scope:[sin16s]  from sin16s::@9
-  (byte) sin16s::isUpper#5 ← phi( sin16s::@9/(byte) sin16s::isUpper#6 )
+  (byte) sin16s::isUpper#4 ← phi( sin16s::@9/(byte) sin16s::isUpper#5 )
   (word) sin16s::x3#1 ← phi( sin16s::@9/(word) sin16s::x3#0 )
   (word) sin16s::x1#2 ← phi( sin16s::@9/(word) sin16s::x1#4 )
-  (word) mul_u16_sel::return#10 ← phi( sin16s::@9/(word) mul_u16_sel::return#2 )
-  (word~) sin16s::$11 ← (word) mul_u16_sel::return#10
+  (word) mul_u16_sel::return#9 ← phi( sin16s::@9/(word) mul_u16_sel::return#2 )
+  (word~) sin16s::$11 ← (word) mul_u16_sel::return#9
   (word) sin16s::x3_6#0 ← (word~) sin16s::$11
   (word~) sin16s::$12 ← (word) sin16s::x1#2 - (word) sin16s::x3_6#0
   (word) sin16s::usinx#0 ← (word~) sin16s::$12
@@ -2928,144 +2970,90 @@ sin16s::@10: scope:[sin16s]  from sin16s::@9
   (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#2
   (byte) mul_u16_sel::select#3 ← (byte/signed byte/word/signed word/dword/signed dword) 0
   call mul_u16_sel param-assignment
-  (word) mul_u16_sel::return#3 ← (word) mul_u16_sel::return#7
+  (word) mul_u16_sel::return#3 ← (word) mul_u16_sel::return#6
   to:sin16s::@11
 sin16s::@11: scope:[sin16s]  from sin16s::@10
-  (byte) sin16s::isUpper#4 ← phi( sin16s::@10/(byte) sin16s::isUpper#5 )
-  (word) sin16s::usinx#5 ← phi( sin16s::@10/(word) sin16s::usinx#0 )
+  (byte) sin16s::isUpper#3 ← phi( sin16s::@10/(byte) sin16s::isUpper#4 )
+  (word) sin16s::usinx#4 ← phi( sin16s::@10/(word) sin16s::usinx#0 )
   (word) sin16s::x1#3 ← phi( sin16s::@10/(word) sin16s::x1#2 )
-  (word) mul_u16_sel::return#11 ← phi( sin16s::@10/(word) mul_u16_sel::return#3 )
-  (word~) sin16s::$13 ← (word) mul_u16_sel::return#11
+  (word) mul_u16_sel::return#10 ← phi( sin16s::@10/(word) mul_u16_sel::return#3 )
+  (word~) sin16s::$13 ← (word) mul_u16_sel::return#10
   (word) sin16s::x4#0 ← (word~) sin16s::$13
   (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0
   (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#3
   (byte) mul_u16_sel::select#4 ← (byte/signed byte/word/signed word/dword/signed dword) 0
   call mul_u16_sel param-assignment
-  (word) mul_u16_sel::return#4 ← (word) mul_u16_sel::return#7
+  (word) mul_u16_sel::return#4 ← (word) mul_u16_sel::return#6
   to:sin16s::@12
 sin16s::@12: scope:[sin16s]  from sin16s::@11
-  (byte) sin16s::isUpper#3 ← phi( sin16s::@11/(byte) sin16s::isUpper#4 )
-  (word) sin16s::usinx#4 ← phi( sin16s::@11/(word) sin16s::usinx#5 )
-  (word) mul_u16_sel::return#12 ← phi( sin16s::@11/(word) mul_u16_sel::return#4 )
-  (word~) sin16s::$14 ← (word) mul_u16_sel::return#12
+  (byte) sin16s::isUpper#2 ← phi( sin16s::@11/(byte) sin16s::isUpper#3 )
+  (word) sin16s::usinx#2 ← phi( sin16s::@11/(word) sin16s::usinx#4 )
+  (word) mul_u16_sel::return#11 ← phi( sin16s::@11/(word) mul_u16_sel::return#4 )
+  (word~) sin16s::$14 ← (word) mul_u16_sel::return#11
   (word) sin16s::x5#0 ← (word~) sin16s::$14
-  (word/signed word/dword/signed dword~) sin16s::$15 ← (dword/signed dword) 65536 / (byte/word/signed word/dword/signed dword) 128
-  (word) mul_u16_sel::v1#5 ← (word) sin16s::x5#0
-  (word) mul_u16_sel::v2#5 ← (word/signed word/dword/signed dword~) sin16s::$15
-  (byte) mul_u16_sel::select#5 ← (byte/signed byte/word/signed word/dword/signed dword) 3
-  call mul_u16_sel param-assignment
-  (word) mul_u16_sel::return#5 ← (word) mul_u16_sel::return#7
-  to:sin16s::@13
-sin16s::@13: scope:[sin16s]  from sin16s::@12
-  (byte) sin16s::isUpper#2 ← phi( sin16s::@12/(byte) sin16s::isUpper#3 )
-  (word) sin16s::usinx#2 ← phi( sin16s::@12/(word) sin16s::usinx#4 )
-  (word) mul_u16_sel::return#13 ← phi( sin16s::@12/(word) mul_u16_sel::return#5 )
-  (word~) sin16s::$16 ← (word) mul_u16_sel::return#13
-  (word) sin16s::x5_128#0 ← (word~) sin16s::$16
-  (word~) sin16s::$17 ← (word) sin16s::usinx#2 + (word) sin16s::x5_128#0
-  (word) sin16s::usinx#1 ← (word~) sin16s::$17
-  (signed word~) sin16s::$18 ← ((signed word)) (word) sin16s::usinx#1
-  (signed word) sin16s::sinx#0 ← (signed word~) sin16s::$18
-  (boolean~) sin16s::$19 ← (byte) sin16s::isUpper#2 != (byte/signed byte/word/signed word/dword/signed dword) 0
-  (boolean~) sin16s::$20 ← ! (boolean~) sin16s::$19
-  if((boolean~) sin16s::$20) goto sin16s::@3
+  (word~) sin16s::$15 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4
+  (word) sin16s::x5_128#0 ← (word~) sin16s::$15
+  (word~) sin16s::$16 ← (word) sin16s::usinx#2 + (word) sin16s::x5_128#0
+  (word) sin16s::usinx#1 ← (word~) sin16s::$16
+  (signed word~) sin16s::$17 ← ((signed word)) (word) sin16s::usinx#1
+  (signed word) sin16s::sinx#0 ← (signed word~) sin16s::$17
+  (boolean~) sin16s::$18 ← (byte) sin16s::isUpper#2 != (byte/signed byte/word/signed word/dword/signed dword) 0
+  (boolean~) sin16s::$19 ← ! (boolean~) sin16s::$18
+  if((boolean~) sin16s::$19) goto sin16s::@3
   to:sin16s::@6
 sin16s::@5: scope:[sin16s]  from sin16s::@1
-  (byte) sin16s::isUpper#10 ← phi( sin16s::@1/(byte) sin16s::isUpper#9 )
+  (byte) sin16s::isUpper#9 ← phi( sin16s::@1/(byte) sin16s::isUpper#8 )
   (dword) sin16s::x#7 ← phi( sin16s::@1/(dword) sin16s::x#4 )
   (dword~) sin16s::$5 ← (dword) PI_u4f28#0 - (dword) sin16s::x#7
   (dword) sin16s::x#2 ← (dword~) sin16s::$5
   to:sin16s::@2
-sin16s::@3: scope:[sin16s]  from sin16s::@13 sin16s::@6
-  (signed word) sin16s::sinx#2 ← phi( sin16s::@13/(signed word) sin16s::sinx#0 sin16s::@6/(signed word) sin16s::sinx#1 )
+sin16s::@3: scope:[sin16s]  from sin16s::@12 sin16s::@6
+  (signed word) sin16s::sinx#2 ← phi( sin16s::@12/(signed word) sin16s::sinx#0 sin16s::@6/(signed word) sin16s::sinx#1 )
   (signed word) sin16s::return#1 ← (signed word) sin16s::sinx#2
   to:sin16s::@return
-sin16s::@6: scope:[sin16s]  from sin16s::@13
-  (word) sin16s::usinx#3 ← phi( sin16s::@13/(word) sin16s::usinx#1 )
-  (signed word~) sin16s::$21 ← ((signed word)) (word) sin16s::usinx#3
-  (signed word~) sin16s::$22 ← - (signed word~) sin16s::$21
-  (signed word) sin16s::sinx#1 ← (signed word~) sin16s::$22
+sin16s::@6: scope:[sin16s]  from sin16s::@12
+  (word) sin16s::usinx#3 ← phi( sin16s::@12/(word) sin16s::usinx#1 )
+  (signed word~) sin16s::$20 ← ((signed word)) (word) sin16s::usinx#3
+  (signed word~) sin16s::$21 ← - (signed word~) sin16s::$20
+  (signed word) sin16s::sinx#1 ← (signed word~) sin16s::$21
   to:sin16s::@3
 sin16s::@return: scope:[sin16s]  from sin16s::@3
   (signed word) sin16s::return#4 ← phi( sin16s::@3/(signed word) sin16s::return#1 )
   (signed word) sin16s::return#2 ← (signed word) sin16s::return#4
   return 
   to:@return
-mul_u16_sel: scope:[mul_u16_sel]  from sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@2 sin16s::@8 sin16s::@9
-  (byte) mul_u16_sel::select#7 ← phi( sin16s::@10/(byte) mul_u16_sel::select#3 sin16s::@11/(byte) mul_u16_sel::select#4 sin16s::@12/(byte) mul_u16_sel::select#5 sin16s::@2/(byte) mul_u16_sel::select#0 sin16s::@8/(byte) mul_u16_sel::select#1 sin16s::@9/(byte) mul_u16_sel::select#2 )
-  (word) mul_u16_sel::v2#6 ← phi( sin16s::@10/(word) mul_u16_sel::v2#3 sin16s::@11/(word) mul_u16_sel::v2#4 sin16s::@12/(word) mul_u16_sel::v2#5 sin16s::@2/(word) mul_u16_sel::v2#0 sin16s::@8/(word) mul_u16_sel::v2#1 sin16s::@9/(word) mul_u16_sel::v2#2 )
-  (word) mul_u16_sel::v1#6 ← phi( sin16s::@10/(word) mul_u16_sel::v1#3 sin16s::@11/(word) mul_u16_sel::v1#4 sin16s::@12/(word) mul_u16_sel::v1#5 sin16s::@2/(word) mul_u16_sel::v1#0 sin16s::@8/(word) mul_u16_sel::v1#1 sin16s::@9/(word) mul_u16_sel::v1#2 )
-  (word) mul16u::a#1 ← (word) mul_u16_sel::v1#6
-  (word) mul16u::b#0 ← (word) mul_u16_sel::v2#6
+mul_u16_sel: scope:[mul_u16_sel]  from sin16s::@10 sin16s::@11 sin16s::@2 sin16s::@8 sin16s::@9
+  (byte) mul_u16_sel::select#6 ← phi( sin16s::@10/(byte) mul_u16_sel::select#3 sin16s::@11/(byte) mul_u16_sel::select#4 sin16s::@2/(byte) mul_u16_sel::select#0 sin16s::@8/(byte) mul_u16_sel::select#1 sin16s::@9/(byte) mul_u16_sel::select#2 )
+  (word) mul_u16_sel::v2#5 ← phi( sin16s::@10/(word) mul_u16_sel::v2#3 sin16s::@11/(word) mul_u16_sel::v2#4 sin16s::@2/(word) mul_u16_sel::v2#0 sin16s::@8/(word) mul_u16_sel::v2#1 sin16s::@9/(word) mul_u16_sel::v2#2 )
+  (word) mul_u16_sel::v1#5 ← phi( sin16s::@10/(word) mul_u16_sel::v1#3 sin16s::@11/(word) mul_u16_sel::v1#4 sin16s::@2/(word) mul_u16_sel::v1#0 sin16s::@8/(word) mul_u16_sel::v1#1 sin16s::@9/(word) mul_u16_sel::v1#2 )
+  (word) mul16u::a#1 ← (word) mul_u16_sel::v1#5
+  (word) mul16u::b#0 ← (word) mul_u16_sel::v2#5
   call mul16u param-assignment
   (dword) mul16u::return#2 ← (dword) mul16u::return#1
   to:mul_u16_sel::@2
 mul_u16_sel::@2: scope:[mul_u16_sel]  from mul_u16_sel
-  (byte) mul_u16_sel::select#6 ← phi( mul_u16_sel/(byte) mul_u16_sel::select#7 )
+  (byte) mul_u16_sel::select#5 ← phi( mul_u16_sel/(byte) mul_u16_sel::select#6 )
   (dword) mul16u::return#4 ← phi( mul_u16_sel/(dword) mul16u::return#2 )
   (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#4
-  (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#6
+  (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#5
   (word~) mul_u16_sel::$2 ← > (dword~) mul_u16_sel::$1
-  (word) mul_u16_sel::return#6 ← (word~) mul_u16_sel::$2
+  (word) mul_u16_sel::return#5 ← (word~) mul_u16_sel::$2
   to:mul_u16_sel::@return
 mul_u16_sel::@return: scope:[mul_u16_sel]  from mul_u16_sel::@2
-  (word) mul_u16_sel::return#14 ← phi( mul_u16_sel::@2/(word) mul_u16_sel::return#6 )
-  (word) mul_u16_sel::return#7 ← (word) mul_u16_sel::return#14
+  (word) mul_u16_sel::return#12 ← phi( mul_u16_sel::@2/(word) mul_u16_sel::return#5 )
+  (word) mul_u16_sel::return#6 ← (word) mul_u16_sel::return#12
   return 
   to:@return
-div32u16u: scope:[div32u16u]  from sin16s_gen
-  (word) rem16u#24 ← phi( sin16s_gen/(word) rem16u#22 )
-  (word) div32u16u::divisor#1 ← phi( sin16s_gen/(word) div32u16u::divisor#0 )
-  (dword) div32u16u::dividend#1 ← phi( sin16s_gen/(dword) div32u16u::dividend#0 )
-  (word~) div32u16u::$0 ← > (dword) div32u16u::dividend#1
-  (word) divr16u::dividend#1 ← (word~) div32u16u::$0
-  (word) divr16u::divisor#0 ← (word) div32u16u::divisor#1
-  (word) divr16u::rem#3 ← (byte/signed byte/word/signed word/dword/signed dword) 0
-  call divr16u param-assignment
-  (word) divr16u::return#2 ← (word) divr16u::return#1
-  to:div32u16u::@2
-div32u16u::@2: scope:[div32u16u]  from div32u16u
-  (word) div32u16u::divisor#2 ← phi( div32u16u/(word) div32u16u::divisor#1 )
-  (dword) div32u16u::dividend#2 ← phi( div32u16u/(dword) div32u16u::dividend#1 )
-  (word) rem16u#16 ← phi( div32u16u/(word) rem16u#2 )
-  (word) divr16u::return#5 ← phi( div32u16u/(word) divr16u::return#2 )
-  (word~) div32u16u::$1 ← (word) divr16u::return#5
-  (word) rem16u#7 ← (word) rem16u#16
-  (word) div32u16u::quotient_hi#0 ← (word~) div32u16u::$1
-  (word~) div32u16u::$2 ← < (dword) div32u16u::dividend#2
-  (word) divr16u::dividend#2 ← (word~) div32u16u::$2
-  (word) divr16u::divisor#1 ← (word) div32u16u::divisor#2
-  (word) divr16u::rem#4 ← (word) rem16u#7
-  call divr16u param-assignment
-  (word) divr16u::return#3 ← (word) divr16u::return#1
-  to:div32u16u::@3
-div32u16u::@3: scope:[div32u16u]  from div32u16u::@2
-  (word) div32u16u::quotient_hi#1 ← phi( div32u16u::@2/(word) div32u16u::quotient_hi#0 )
-  (word) rem16u#17 ← phi( div32u16u::@2/(word) rem16u#2 )
-  (word) divr16u::return#6 ← phi( div32u16u::@2/(word) divr16u::return#3 )
-  (word~) div32u16u::$3 ← (word) divr16u::return#6
-  (word) rem16u#8 ← (word) rem16u#17
-  (word) div32u16u::quotient_lo#0 ← (word~) div32u16u::$3
-  (dword) div32u16u::quotient#0 ← { (word) div32u16u::quotient_hi#1, (word) div32u16u::quotient_lo#0 }
-  (dword) div32u16u::return#1 ← (dword) div32u16u::quotient#0
-  to:div32u16u::@return
-div32u16u::@return: scope:[div32u16u]  from div32u16u::@3
-  (word) rem16u#18 ← phi( div32u16u::@3/(word) rem16u#8 )
-  (dword) div32u16u::return#4 ← phi( div32u16u::@3/(dword) div32u16u::return#1 )
-  (dword) div32u16u::return#2 ← (dword) div32u16u::return#4
-  (word) rem16u#9 ← (word) rem16u#18
-  return 
-  to:@return
-@26: scope:[]  from @21
-  (byte*) char_cursor#50 ← phi( @21/(byte*) char_cursor#55 )
-  (byte*) line_cursor#12 ← phi( @21/(byte*) line_cursor#15 )
-  (word) rem16u#25 ← phi( @21/(word) rem16u#28 )
+@26: scope:[]  from @22
+  (byte*) char_cursor#50 ← phi( @22/(byte*) char_cursor#55 )
+  (byte*) line_cursor#12 ← phi( @22/(byte*) line_cursor#15 )
+  (word) rem16u#25 ← phi( @22/(word) rem16u#28 )
   call main param-assignment
   to:@27
 @27: scope:[]  from @26
   (byte*) char_cursor#41 ← phi( @26/(byte*) char_cursor#20 )
   (byte*) line_cursor#9 ← phi( @26/(byte*) line_cursor#4 )
-  (word) rem16u#19 ← phi( @26/(word) rem16u#4 )
+  (word) rem16u#19 ← phi( @26/(word) rem16u#7 )
   (word) rem16u#10 ← (word) rem16u#19
   (byte*) line_cursor#5 ← (byte*) line_cursor#9
   (byte*) char_cursor#21 ← (byte*) char_cursor#41
@@ -3073,9 +3061,9 @@ div32u16u::@return: scope:[div32u16u]  from div32u16u::@3
 @end: scope:[]  from @27
 
 SYMBOL TABLE SSA
-(label) @10
+(label) @11
 (label) @2
-(label) @21
+(label) @22
 (label) @26
 (label) @27
 (label) @begin
@@ -3375,8 +3363,6 @@ SYMBOL TABLE SSA
 (word) mul_u16_sel::return#10
 (word) mul_u16_sel::return#11
 (word) mul_u16_sel::return#12
-(word) mul_u16_sel::return#13
-(word) mul_u16_sel::return#14
 (word) mul_u16_sel::return#2
 (word) mul_u16_sel::return#3
 (word) mul_u16_sel::return#4
@@ -3393,7 +3379,6 @@ SYMBOL TABLE SSA
 (byte) mul_u16_sel::select#4
 (byte) mul_u16_sel::select#5
 (byte) mul_u16_sel::select#6
-(byte) mul_u16_sel::select#7
 (word) mul_u16_sel::v1
 (word) mul_u16_sel::v1#0
 (word) mul_u16_sel::v1#1
@@ -3401,7 +3386,6 @@ SYMBOL TABLE SSA
 (word) mul_u16_sel::v1#3
 (word) mul_u16_sel::v1#4
 (word) mul_u16_sel::v1#5
-(word) mul_u16_sel::v1#6
 (word) mul_u16_sel::v2
 (word) mul_u16_sel::v2#0
 (word) mul_u16_sel::v2#1
@@ -3409,7 +3393,6 @@ SYMBOL TABLE SSA
 (word) mul_u16_sel::v2#3
 (word) mul_u16_sel::v2#4
 (word) mul_u16_sel::v2#5
-(word) mul_u16_sel::v2#6
 (void()) print_byte((byte) print_byte::b)
 (byte~) print_byte::$0
 (byte~) print_byte::$2
@@ -3524,15 +3507,14 @@ SYMBOL TABLE SSA
 (word~) sin16s::$12
 (word~) sin16s::$13
 (word~) sin16s::$14
-(word/signed word/dword/signed dword~) sin16s::$15
+(word~) sin16s::$15
 (word~) sin16s::$16
-(word~) sin16s::$17
-(signed word~) sin16s::$18
+(signed word~) sin16s::$17
+(boolean~) sin16s::$18
 (boolean~) sin16s::$19
 (dword~) sin16s::$2
-(boolean~) sin16s::$20
+(signed word~) sin16s::$20
 (signed word~) sin16s::$21
-(signed word~) sin16s::$22
 (boolean~) sin16s::$3
 (boolean~) sin16s::$4
 (dword~) sin16s::$5
@@ -3544,7 +3526,6 @@ SYMBOL TABLE SSA
 (label) sin16s::@10
 (label) sin16s::@11
 (label) sin16s::@12
-(label) sin16s::@13
 (label) sin16s::@2
 (label) sin16s::@3
 (label) sin16s::@4
@@ -3556,7 +3537,6 @@ SYMBOL TABLE SSA
 (byte) sin16s::isUpper
 (byte) sin16s::isUpper#0
 (byte) sin16s::isUpper#1
-(byte) sin16s::isUpper#10
 (byte) sin16s::isUpper#2
 (byte) sin16s::isUpper#3
 (byte) sin16s::isUpper#4
@@ -3581,7 +3561,6 @@ SYMBOL TABLE SSA
 (word) sin16s::usinx#2
 (word) sin16s::usinx#3
 (word) sin16s::usinx#4
-(word) sin16s::usinx#5
 (dword) sin16s::x
 (dword) sin16s::x#0
 (dword) sin16s::x#1
@@ -3656,12 +3635,24 @@ Inversing boolean not (boolean~) print_sword::$1 ← (signed word) print_sword::
 Inversing boolean not (boolean~) main::$3 ← (signed word) main::sw#0 < (byte/signed byte/word/signed word/dword/signed dword) 0 from (boolean~) main::$2 ← (signed word) main::sw#0 >= (byte/signed byte/word/signed word/dword/signed dword) 0
 Inversing boolean not (boolean~) sin16s::$1 ← (dword) sin16s::x#3 < (dword) PI_u4f28#0 from (boolean~) sin16s::$0 ← (dword) sin16s::x#3 >= (dword) PI_u4f28#0
 Inversing boolean not (boolean~) sin16s::$4 ← (dword) sin16s::x#4 < (dword) PI_HALF_u4f28#0 from (boolean~) sin16s::$3 ← (dword) sin16s::x#4 >= (dword) PI_HALF_u4f28#0
-Inversing boolean not (boolean~) sin16s::$20 ← (byte) sin16s::isUpper#2 == (byte/signed byte/word/signed word/dword/signed dword) 0 from (boolean~) sin16s::$19 ← (byte) sin16s::isUpper#2 != (byte/signed byte/word/signed word/dword/signed dword) 0
+Inversing boolean not (boolean~) sin16s::$19 ← (byte) sin16s::isUpper#2 == (byte/signed byte/word/signed word/dword/signed dword) 0 from (boolean~) sin16s::$18 ← (byte) sin16s::isUpper#2 != (byte/signed byte/word/signed word/dword/signed dword) 0
 Succesful SSA optimization Pass2UnaryNotSimplification
 Not aliassing across scopes: divr16u::rem#10 divr16u::rem#3
 Not aliassing across scopes: divr16u::dividend#5 divr16u::dividend#1
 Not aliassing across scopes: divr16u::divisor#6 divr16u::divisor#0
 Not aliassing across scopes: rem16u#1 divr16u::rem#9
+Not aliassing across scopes: div32u16u::dividend#1 div32u16u::dividend#0
+Not aliassing across scopes: div32u16u::divisor#1 div32u16u::divisor#0
+Not aliassing across scopes: rem16u#20 rem16u#23
+Not aliassing across scopes: divr16u::divisor#0 div32u16u::divisor#1
+Not aliassing across scopes: divr16u::return#2 divr16u::return#1
+Not aliassing across scopes: rem16u#12 rem16u#2
+Not aliassing across scopes: div32u16u::$1 divr16u::return#5
+Not aliassing across scopes: divr16u::divisor#1 div32u16u::divisor#2
+Not aliassing across scopes: divr16u::rem#4 rem16u#3
+Not aliassing across scopes: divr16u::return#3 divr16u::return#1
+Not aliassing across scopes: rem16u#13 rem16u#2
+Not aliassing across scopes: div32u16u::$3 divr16u::return#6
 Not aliassing across scopes: mul16u::b#1 mul16u::b#0
 Not aliassing across scopes: mul16u::a#5 mul16u::a#1
 Not aliassing across scopes: print_str::str#5 print_str::str#2
@@ -3682,12 +3673,12 @@ Not aliassing across scopes: print_char::ch#3 print_char::ch#1
 Not aliassing across scopes: char_cursor#33 char_cursor#46
 Not aliassing across scopes: print_cls::sc#0 SCREEN#0
 Not aliassing across scopes: line_cursor#1 SCREEN#0
-Not aliassing across scopes: rem16u#20 rem16u#25
+Not aliassing across scopes: rem16u#21 rem16u#25
 Not aliassing across scopes: line_cursor#13 line_cursor#12
 Not aliassing across scopes: char_cursor#53 char_cursor#50
 Not aliassing across scopes: sin16s_gen::sintab#0 main::sintab1#0
 Not aliassing across scopes: sin16s_gen::wavelength#0 main::wavelength#0
-Not aliassing across scopes: rem16u#12 rem16u#6
+Not aliassing across scopes: rem16u#15 rem16u#9
 Not aliassing across scopes: line_cursor#7 line_cursor#2
 Not aliassing across scopes: char_cursor#36 char_cursor#15
 Not aliassing across scopes: print_sword::w#1 main::sw#1
@@ -3695,59 +3686,44 @@ Not aliassing across scopes: char_cursor#37 char_cursor#5
 Not aliassing across scopes: char_cursor#38 char_cursor#2
 Not aliassing across scopes: char_cursor#39 char_cursor#2
 Not aliassing across scopes: sin16s_gen::wavelength#1 sin16s_gen::wavelength#0
-Not aliassing across scopes: rem16u#22 rem16u#20
+Not aliassing across scopes: rem16u#23 rem16u#21
 Not aliassing across scopes: sin16s_gen::sintab#5 sin16s_gen::sintab#0
 Not aliassing across scopes: div32u16u::dividend#0 PI2_u4f28#0
 Not aliassing across scopes: div32u16u::divisor#0 sin16s_gen::wavelength#1
-Not aliassing across scopes: div32u16u::return#0 div32u16u::return#2
-Not aliassing across scopes: rem16u#14 rem16u#9
-Not aliassing across scopes: sin16s_gen::$0 div32u16u::return#3
+Not aliassing across scopes: div32u16u::return#2 div32u16u::return#1
+Not aliassing across scopes: rem16u#17 rem16u#5
+Not aliassing across scopes: sin16s_gen::$0 div32u16u::return#4
 Not aliassing across scopes: sin16s::x#0 sin16s_gen::x#2
 Not aliassing across scopes: sin16s::return#0 sin16s::return#2
 Not aliassing across scopes: sin16s_gen::$1 sin16s::return#3
 Not aliassing across scopes: sin16s::x#3 sin16s::x#0
 Not aliassing across scopes: mul_u16_sel::v1#0 sin16s::x1#0
 Not aliassing across scopes: mul_u16_sel::v2#0 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#7
-Not aliassing across scopes: sin16s::$8 mul_u16_sel::return#8
+Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#6
+Not aliassing across scopes: sin16s::$8 mul_u16_sel::return#7
 Not aliassing across scopes: mul_u16_sel::v1#1 sin16s::x2#0
 Not aliassing across scopes: mul_u16_sel::v2#1 sin16s::x1#1
-Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#7
-Not aliassing across scopes: sin16s::$9 mul_u16_sel::return#9
+Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#6
+Not aliassing across scopes: sin16s::$9 mul_u16_sel::return#8
 Not aliassing across scopes: mul_u16_sel::v1#2 sin16s::x3#0
-Not aliassing across scopes: mul_u16_sel::return#2 mul_u16_sel::return#7
-Not aliassing across scopes: sin16s::$11 mul_u16_sel::return#10
+Not aliassing across scopes: mul_u16_sel::return#2 mul_u16_sel::return#6
+Not aliassing across scopes: sin16s::$11 mul_u16_sel::return#9
 Not aliassing across scopes: mul_u16_sel::v1#3 sin16s::x3#1
 Not aliassing across scopes: mul_u16_sel::v2#3 sin16s::x1#2
-Not aliassing across scopes: mul_u16_sel::return#3 mul_u16_sel::return#7
-Not aliassing across scopes: sin16s::$13 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::return#3 mul_u16_sel::return#6
+Not aliassing across scopes: sin16s::$13 mul_u16_sel::return#10
 Not aliassing across scopes: mul_u16_sel::v1#4 sin16s::x4#0
 Not aliassing across scopes: mul_u16_sel::v2#4 sin16s::x1#3
-Not aliassing across scopes: mul_u16_sel::return#4 mul_u16_sel::return#7
-Not aliassing across scopes: sin16s::$14 mul_u16_sel::return#12
-Not aliassing across scopes: mul_u16_sel::v1#5 sin16s::x5#0
-Not aliassing across scopes: mul_u16_sel::return#5 mul_u16_sel::return#7
-Not aliassing across scopes: sin16s::$16 mul_u16_sel::return#13
-Not aliassing across scopes: mul_u16_sel::v1#6 mul_u16_sel::v1#3
-Not aliassing across scopes: mul_u16_sel::v2#6 mul_u16_sel::v2#3
-Not aliassing across scopes: mul_u16_sel::select#7 mul_u16_sel::select#3
-Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#6
-Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#6
+Not aliassing across scopes: mul_u16_sel::return#4 mul_u16_sel::return#6
+Not aliassing across scopes: sin16s::$14 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::v1#5 mul_u16_sel::v1#3
+Not aliassing across scopes: mul_u16_sel::v2#5 mul_u16_sel::v2#3
+Not aliassing across scopes: mul_u16_sel::select#6 mul_u16_sel::select#3
+Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#5
+Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#5
 Not aliassing across scopes: mul16u::return#2 mul16u::return#1
 Not aliassing across scopes: mul_u16_sel::$0 mul16u::return#4
-Not aliassing across scopes: div32u16u::dividend#1 div32u16u::dividend#0
-Not aliassing across scopes: div32u16u::divisor#1 div32u16u::divisor#0
-Not aliassing across scopes: rem16u#24 rem16u#22
-Not aliassing across scopes: divr16u::divisor#0 div32u16u::divisor#1
-Not aliassing across scopes: divr16u::return#2 divr16u::return#1
-Not aliassing across scopes: rem16u#16 rem16u#2
-Not aliassing across scopes: div32u16u::$1 divr16u::return#5
-Not aliassing across scopes: divr16u::divisor#1 div32u16u::divisor#2
-Not aliassing across scopes: divr16u::rem#4 rem16u#7
-Not aliassing across scopes: divr16u::return#3 divr16u::return#1
-Not aliassing across scopes: rem16u#17 rem16u#2
-Not aliassing across scopes: div32u16u::$3 divr16u::return#6
-Not aliassing across scopes: rem16u#19 rem16u#4
+Not aliassing across scopes: rem16u#19 rem16u#7
 Not aliassing across scopes: line_cursor#9 line_cursor#4
 Not aliassing across scopes: char_cursor#41 char_cursor#20
 Alias (word) divr16u::rem#0 = (word~) divr16u::$0 (word) divr16u::rem#7 
@@ -3765,6 +3741,17 @@ Alias (word) divr16u::rem#2 = (word~) divr16u::$10
 Alias (word) divr16u::rem#11 = (word) divr16u::rem#9 
 Alias (word) divr16u::return#0 = (word) divr16u::quotient#5 (word) divr16u::quotient#8 (word) divr16u::return#4 (word) divr16u::return#1 
 Alias (word) rem16u#1 = (word) rem16u#11 (word) rem16u#2 
+Alias (word) divr16u::dividend#1 = (word~) div32u16u::$0 
+Alias (word) divr16u::return#2 = (word) divr16u::return#5 
+Alias (dword) div32u16u::dividend#1 = (dword) div32u16u::dividend#2 
+Alias (word) div32u16u::divisor#1 = (word) div32u16u::divisor#2 
+Alias (word) rem16u#12 = (word) rem16u#3 
+Alias (word) div32u16u::quotient_hi#0 = (word~) div32u16u::$1 (word) div32u16u::quotient_hi#1 
+Alias (word) divr16u::dividend#2 = (word~) div32u16u::$2 
+Alias (word) divr16u::return#3 = (word) divr16u::return#6 
+Alias (word) rem16u#13 = (word) rem16u#4 (word) rem16u#14 (word) rem16u#5 
+Alias (word) div32u16u::quotient_lo#0 = (word~) div32u16u::$3 
+Alias (dword) div32u16u::return#0 = (dword) div32u16u::quotient#0 (dword) div32u16u::return#3 (dword) div32u16u::return#1 
 Alias (word) mul16u::a#2 = (word) mul16u::a#3 (word) mul16u::a#6 
 Alias (dword) mul16u::mb#3 = (dword) mul16u::mb#4 (dword) mul16u::mb#5 
 Alias (dword) mul16u::res#2 = (dword) mul16u::res#5 (dword) mul16u::res#4 (dword) mul16u::return#0 (dword) mul16u::res#3 (dword) mul16u::return#3 (dword) mul16u::return#1 
@@ -3794,13 +3781,13 @@ Alias (byte*) line_cursor#1 = (byte*) char_cursor#14 (byte*) line_cursor#6 (byte
 Alias (byte*) line_cursor#10 = (byte*) line_cursor#13 
 Alias (byte*) char_cursor#47 = (byte*) char_cursor#53 
 Alias (word) main::wavelength#0 = (word) main::wavelength#8 (word) main::wavelength#6 
-Alias (word) rem16u#12 = (word) rem16u#3 (word) rem16u#33 
+Alias (word) rem16u#15 = (word) rem16u#6 (word) rem16u#33 
 Alias (byte*) line_cursor#3 = (byte*) line_cursor#7 
 Alias (byte*) char_cursor#16 = (byte*) char_cursor#36 
 Alias (signed word[120]) main::sintab1#0 = (signed word*) main::st1#0 
 Alias (signed word*) main::st1#3 = (signed word*) main::st1#4 (signed word*) main::st1#5 
 Alias (word) main::wavelength#1 = (word) main::wavelength#2 (word) main::wavelength#3 
-Alias (word) rem16u#13 = (word) rem16u#26 (word) rem16u#29 (word) rem16u#21 (word) rem16u#4 
+Alias (word) rem16u#16 = (word) rem16u#26 (word) rem16u#29 (word) rem16u#22 (word) rem16u#7 
 Alias (byte*) line_cursor#11 = (byte*) line_cursor#14 (byte*) line_cursor#16 (byte*) line_cursor#8 (byte*) line_cursor#4 
 Alias (byte*) char_cursor#17 = (byte*) char_cursor#37 
 Alias (byte*) char_cursor#18 = (byte*) char_cursor#38 (byte*) char_cursor#40 (byte*) char_cursor#20 
@@ -3812,10 +3799,10 @@ Alias (word) main::wavelength#4 = (word) main::wavelength#7 (word) main::wavelen
 Alias (word) rem16u#31 = (word) rem16u#34 (word) rem16u#32 
 Alias (byte*) line_cursor#17 = (byte*) line_cursor#19 (byte*) line_cursor#18 
 Alias (byte*) char_cursor#19 = (byte*) char_cursor#39 
-Alias (dword) div32u16u::return#0 = (dword) div32u16u::return#3 
+Alias (dword) div32u16u::return#2 = (dword) div32u16u::return#4 
 Alias (signed word*) sin16s_gen::sintab#4 = (signed word*) sin16s_gen::sintab#5 
 Alias (word) sin16s_gen::wavelength#1 = (word) sin16s_gen::wavelength#4 
-Alias (word) rem16u#14 = (word) rem16u#5 
+Alias (word) rem16u#17 = (word) rem16u#8 
 Alias (dword) sin16s_gen::step#0 = (dword~) sin16s_gen::$0 
 Alias (signed word) sin16s::return#0 = (signed word) sin16s::return#3 
 Alias (signed word*) sin16s_gen::sintab#2 = (signed word*) sin16s_gen::sintab#3 
@@ -3823,49 +3810,36 @@ Alias (dword) sin16s_gen::x#2 = (dword) sin16s_gen::x#3
 Alias (dword) sin16s_gen::step#1 = (dword) sin16s_gen::step#2 
 Alias (word) sin16s_gen::i#2 = (word) sin16s_gen::i#3 
 Alias (word) sin16s_gen::wavelength#2 = (word) sin16s_gen::wavelength#3 
-Alias (word) rem16u#15 = (word) rem16u#23 (word) rem16u#27 (word) rem16u#6 
+Alias (word) rem16u#18 = (word) rem16u#24 (word) rem16u#27 (word) rem16u#9 
 Alias (signed word*) sin16s_gen::sintab#1 = (signed word*~) sin16s_gen::$2 
 Alias (dword) sin16s_gen::x#1 = (dword~) sin16s_gen::$3 
 Alias (dword) sin16s::x#3 = (dword) sin16s::x#5 
 Alias (dword) sin16s::x#1 = (dword~) sin16s::$2 
 Alias (word) sin16s::x1#0 = (word~) sin16s::$7 (word) sin16s::x1#1 (word) sin16s::x1#4 (word) sin16s::x1#2 (word) sin16s::x1#3 
-Alias (word) mul_u16_sel::return#0 = (word) mul_u16_sel::return#8 
-Alias (byte) sin16s::isUpper#2 = (byte) sin16s::isUpper#7 (byte) sin16s::isUpper#8 (byte) sin16s::isUpper#6 (byte) sin16s::isUpper#5 (byte) sin16s::isUpper#4 (byte) sin16s::isUpper#3 
+Alias (word) mul_u16_sel::return#0 = (word) mul_u16_sel::return#7 
+Alias (byte) sin16s::isUpper#2 = (byte) sin16s::isUpper#6 (byte) sin16s::isUpper#7 (byte) sin16s::isUpper#5 (byte) sin16s::isUpper#4 (byte) sin16s::isUpper#3 
 Alias (word) sin16s::x2#0 = (word~) sin16s::$8 
-Alias (word) mul_u16_sel::return#1 = (word) mul_u16_sel::return#9 
+Alias (word) mul_u16_sel::return#1 = (word) mul_u16_sel::return#8 
 Alias (word) sin16s::x3#0 = (word~) sin16s::$9 (word) sin16s::x3#1 
 Alias (word) mul_u16_sel::v2#2 = (word/signed word/dword/signed dword~) sin16s::$10 
-Alias (word) mul_u16_sel::return#10 = (word) mul_u16_sel::return#2 
+Alias (word) mul_u16_sel::return#2 = (word) mul_u16_sel::return#9 
 Alias (word) sin16s::x3_6#0 = (word~) sin16s::$11 
-Alias (word) sin16s::usinx#0 = (word~) sin16s::$12 (word) sin16s::usinx#5 (word) sin16s::usinx#4 (word) sin16s::usinx#2 
-Alias (word) mul_u16_sel::return#11 = (word) mul_u16_sel::return#3 
+Alias (word) sin16s::usinx#0 = (word~) sin16s::$12 (word) sin16s::usinx#4 (word) sin16s::usinx#2 
+Alias (word) mul_u16_sel::return#10 = (word) mul_u16_sel::return#3 
 Alias (word) sin16s::x4#0 = (word~) sin16s::$13 
-Alias (word) mul_u16_sel::return#12 = (word) mul_u16_sel::return#4 
+Alias (word) mul_u16_sel::return#11 = (word) mul_u16_sel::return#4 
 Alias (word) sin16s::x5#0 = (word~) sin16s::$14 
-Alias (word) mul_u16_sel::v2#5 = (word/signed word/dword/signed dword~) sin16s::$15 
-Alias (word) mul_u16_sel::return#13 = (word) mul_u16_sel::return#5 
-Alias (word) sin16s::x5_128#0 = (word~) sin16s::$16 
-Alias (word) sin16s::usinx#1 = (word~) sin16s::$17 (word) sin16s::usinx#3 
-Alias (signed word) sin16s::sinx#0 = (signed word~) sin16s::$18 
+Alias (word) sin16s::x5_128#0 = (word~) sin16s::$15 
+Alias (word) sin16s::usinx#1 = (word~) sin16s::$16 (word) sin16s::usinx#3 
+Alias (signed word) sin16s::sinx#0 = (signed word~) sin16s::$17 
 Alias (dword) sin16s::x#4 = (dword) sin16s::x#7 
-Alias (byte) sin16s::isUpper#10 = (byte) sin16s::isUpper#9 
+Alias (byte) sin16s::isUpper#8 = (byte) sin16s::isUpper#9 
 Alias (dword) sin16s::x#2 = (dword~) sin16s::$5 
 Alias (signed word) sin16s::return#1 = (signed word) sin16s::sinx#2 (signed word) sin16s::return#4 (signed word) sin16s::return#2 
-Alias (signed word) sin16s::sinx#1 = (signed word~) sin16s::$22 
+Alias (signed word) sin16s::sinx#1 = (signed word~) sin16s::$21 
 Alias (dword) mul16u::return#2 = (dword) mul16u::return#4 
-Alias (byte) mul_u16_sel::select#6 = (byte) mul_u16_sel::select#7 
-Alias (word) mul_u16_sel::return#14 = (word) mul_u16_sel::return#6 (word~) mul_u16_sel::$2 (word) mul_u16_sel::return#7 
-Alias (word) divr16u::dividend#1 = (word~) div32u16u::$0 
-Alias (word) divr16u::return#2 = (word) divr16u::return#5 
-Alias (dword) div32u16u::dividend#1 = (dword) div32u16u::dividend#2 
-Alias (word) div32u16u::divisor#1 = (word) div32u16u::divisor#2 
-Alias (word) rem16u#16 = (word) rem16u#7 
-Alias (word) div32u16u::quotient_hi#0 = (word~) div32u16u::$1 (word) div32u16u::quotient_hi#1 
-Alias (word) divr16u::dividend#2 = (word~) div32u16u::$2 
-Alias (word) divr16u::return#3 = (word) divr16u::return#6 
-Alias (word) rem16u#17 = (word) rem16u#8 (word) rem16u#18 (word) rem16u#9 
-Alias (word) div32u16u::quotient_lo#0 = (word~) div32u16u::$3 
-Alias (dword) div32u16u::return#1 = (dword) div32u16u::quotient#0 (dword) div32u16u::return#4 (dword) div32u16u::return#2 
+Alias (byte) mul_u16_sel::select#5 = (byte) mul_u16_sel::select#6 
+Alias (word) mul_u16_sel::return#12 = (word) mul_u16_sel::return#5 (word~) mul_u16_sel::$2 (word) mul_u16_sel::return#6 
 Alias (word) rem16u#10 = (word) rem16u#19 
 Alias (byte*) line_cursor#5 = (byte*) line_cursor#9 
 Alias (byte*) char_cursor#21 = (byte*) char_cursor#41 
@@ -3874,6 +3848,18 @@ Not aliassing across scopes: divr16u::rem#10 divr16u::rem#3
 Not aliassing across scopes: divr16u::dividend#5 divr16u::dividend#1
 Not aliassing across scopes: divr16u::divisor#6 divr16u::divisor#0
 Not aliassing across scopes: rem16u#1 divr16u::rem#11
+Not aliassing across scopes: div32u16u::dividend#1 div32u16u::dividend#0
+Not aliassing across scopes: div32u16u::divisor#1 div32u16u::divisor#0
+Not aliassing across scopes: rem16u#20 rem16u#23
+Not aliassing across scopes: divr16u::divisor#0 div32u16u::divisor#1
+Not aliassing across scopes: divr16u::return#2 divr16u::return#0
+Not aliassing across scopes: rem16u#12 rem16u#1
+Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
+Not aliassing across scopes: divr16u::divisor#1 div32u16u::divisor#1
+Not aliassing across scopes: divr16u::rem#4 rem16u#12
+Not aliassing across scopes: divr16u::return#3 divr16u::return#0
+Not aliassing across scopes: rem16u#13 rem16u#1
+Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
 Not aliassing across scopes: mul16u::b#1 mul16u::b#0
 Not aliassing across scopes: mul16u::a#5 mul16u::a#1
 Not aliassing across scopes: print_str::str#5 print_str::str#2
@@ -3894,12 +3880,12 @@ Not aliassing across scopes: print_char::ch#3 print_char::ch#1
 Not aliassing across scopes: char_cursor#33 char_cursor#46
 Not aliassing across scopes: print_cls::sc#0 SCREEN#0
 Not aliassing across scopes: line_cursor#1 SCREEN#0
-Not aliassing across scopes: rem16u#20 rem16u#0
+Not aliassing across scopes: rem16u#21 rem16u#0
 Not aliassing across scopes: line_cursor#10 SCREEN#0
 Not aliassing across scopes: char_cursor#47 SCREEN#0
 Not aliassing across scopes: sin16s_gen::sintab#0 main::sintab1#0
 Not aliassing across scopes: sin16s_gen::wavelength#0 main::wavelength#0
-Not aliassing across scopes: rem16u#12 rem16u#15
+Not aliassing across scopes: rem16u#15 rem16u#18
 Not aliassing across scopes: line_cursor#3 line_cursor#1
 Not aliassing across scopes: char_cursor#16 line_cursor#1
 Not aliassing across scopes: print_sword::w#1 main::sw#1
@@ -3907,59 +3893,44 @@ Not aliassing across scopes: char_cursor#17 char_cursor#24
 Not aliassing across scopes: char_cursor#18 char_cursor#2
 Not aliassing across scopes: char_cursor#19 char_cursor#2
 Not aliassing across scopes: sin16s_gen::wavelength#1 sin16s_gen::wavelength#0
-Not aliassing across scopes: rem16u#22 rem16u#20
+Not aliassing across scopes: rem16u#23 rem16u#21
 Not aliassing across scopes: sin16s_gen::sintab#4 sin16s_gen::sintab#0
 Not aliassing across scopes: div32u16u::dividend#0 PI2_u4f28#0
 Not aliassing across scopes: div32u16u::divisor#0 sin16s_gen::wavelength#1
-Not aliassing across scopes: div32u16u::return#0 div32u16u::return#1
-Not aliassing across scopes: rem16u#14 rem16u#17
-Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#0
+Not aliassing across scopes: div32u16u::return#2 div32u16u::return#0
+Not aliassing across scopes: rem16u#17 rem16u#13
+Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#2
 Not aliassing across scopes: sin16s::x#0 sin16s_gen::x#2
 Not aliassing across scopes: sin16s::return#0 sin16s::return#1
 Not aliassing across scopes: sin16s_gen::$1 sin16s::return#0
 Not aliassing across scopes: sin16s::x#3 sin16s::x#0
 Not aliassing across scopes: mul_u16_sel::v1#0 sin16s::x1#0
 Not aliassing across scopes: mul_u16_sel::v2#0 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x2#0 mul_u16_sel::return#0
 Not aliassing across scopes: mul_u16_sel::v1#1 sin16s::x2#0
 Not aliassing across scopes: mul_u16_sel::v2#1 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x3#0 mul_u16_sel::return#1
 Not aliassing across scopes: mul_u16_sel::v1#2 sin16s::x3#0
-Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#10
+Not aliassing across scopes: mul_u16_sel::return#2 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#2
 Not aliassing across scopes: mul_u16_sel::v1#3 sin16s::x3#0
 Not aliassing across scopes: mul_u16_sel::v2#3 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#10
 Not aliassing across scopes: mul_u16_sel::v1#4 sin16s::x4#0
 Not aliassing across scopes: mul_u16_sel::v2#4 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#12 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#12
-Not aliassing across scopes: mul_u16_sel::v1#5 sin16s::x5#0
-Not aliassing across scopes: mul_u16_sel::return#13 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5_128#0 mul_u16_sel::return#13
-Not aliassing across scopes: mul_u16_sel::v1#6 mul_u16_sel::v1#3
-Not aliassing across scopes: mul_u16_sel::v2#6 mul_u16_sel::v2#3
-Not aliassing across scopes: mul_u16_sel::select#6 mul_u16_sel::select#3
-Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#6
-Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#6
+Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::v1#5 mul_u16_sel::v1#3
+Not aliassing across scopes: mul_u16_sel::v2#5 mul_u16_sel::v2#3
+Not aliassing across scopes: mul_u16_sel::select#5 mul_u16_sel::select#3
+Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#5
+Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#5
 Not aliassing across scopes: mul16u::return#2 mul16u::res#2
 Not aliassing across scopes: mul_u16_sel::$0 mul16u::return#2
-Not aliassing across scopes: div32u16u::dividend#1 div32u16u::dividend#0
-Not aliassing across scopes: div32u16u::divisor#1 div32u16u::divisor#0
-Not aliassing across scopes: rem16u#24 rem16u#22
-Not aliassing across scopes: divr16u::divisor#0 div32u16u::divisor#1
-Not aliassing across scopes: divr16u::return#2 divr16u::return#0
-Not aliassing across scopes: rem16u#16 rem16u#1
-Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
-Not aliassing across scopes: divr16u::divisor#1 div32u16u::divisor#1
-Not aliassing across scopes: divr16u::rem#4 rem16u#16
-Not aliassing across scopes: divr16u::return#3 divr16u::return#0
-Not aliassing across scopes: rem16u#17 rem16u#1
-Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
-Not aliassing across scopes: rem16u#10 rem16u#13
+Not aliassing across scopes: rem16u#10 rem16u#16
 Not aliassing across scopes: line_cursor#5 line_cursor#11
 Not aliassing across scopes: char_cursor#21 char_cursor#18
 Alias (word) divr16u::dividend#3 = (word) divr16u::dividend#4 
@@ -3972,14 +3943,26 @@ Alias (dword) mul16u::mb#2 = (dword) mul16u::mb#3
 Alias (signed word) main::sw#0 = (signed word) main::sw#1 
 Alias (signed word*) main::st1#2 = (signed word*) main::st1#3 
 Alias (word) main::wavelength#1 = (word) main::wavelength#4 
-Alias (word) rem16u#13 = (word) rem16u#31 
+Alias (word) rem16u#16 = (word) rem16u#31 
 Alias (byte*) line_cursor#11 = (byte*) line_cursor#17 
-Alias (byte) sin16s::isUpper#10 = (byte) sin16s::isUpper#2 
+Alias (byte) sin16s::isUpper#2 = (byte) sin16s::isUpper#8 
 Succesful SSA optimization Pass2AliasElimination
 Not aliassing across scopes: divr16u::rem#10 divr16u::rem#3
 Not aliassing across scopes: divr16u::dividend#5 divr16u::dividend#1
 Not aliassing across scopes: divr16u::divisor#6 divr16u::divisor#0
 Not aliassing across scopes: rem16u#1 divr16u::rem#11
+Not aliassing across scopes: div32u16u::dividend#1 div32u16u::dividend#0
+Not aliassing across scopes: div32u16u::divisor#1 div32u16u::divisor#0
+Not aliassing across scopes: rem16u#20 rem16u#23
+Not aliassing across scopes: divr16u::divisor#0 div32u16u::divisor#1
+Not aliassing across scopes: divr16u::return#2 divr16u::return#0
+Not aliassing across scopes: rem16u#12 rem16u#1
+Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
+Not aliassing across scopes: divr16u::divisor#1 div32u16u::divisor#1
+Not aliassing across scopes: divr16u::rem#4 rem16u#12
+Not aliassing across scopes: divr16u::return#3 divr16u::return#0
+Not aliassing across scopes: rem16u#13 rem16u#1
+Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
 Not aliassing across scopes: mul16u::b#1 mul16u::b#0
 Not aliassing across scopes: mul16u::a#5 mul16u::a#1
 Not aliassing across scopes: print_str::str#5 print_str::str#2
@@ -4000,12 +3983,12 @@ Not aliassing across scopes: print_char::ch#3 print_char::ch#1
 Not aliassing across scopes: char_cursor#33 char_cursor#46
 Not aliassing across scopes: print_cls::sc#0 SCREEN#0
 Not aliassing across scopes: line_cursor#1 SCREEN#0
-Not aliassing across scopes: rem16u#20 rem16u#0
+Not aliassing across scopes: rem16u#21 rem16u#0
 Not aliassing across scopes: line_cursor#10 SCREEN#0
 Not aliassing across scopes: char_cursor#47 SCREEN#0
 Not aliassing across scopes: sin16s_gen::sintab#0 main::sintab1#0
 Not aliassing across scopes: sin16s_gen::wavelength#0 main::wavelength#0
-Not aliassing across scopes: rem16u#12 rem16u#15
+Not aliassing across scopes: rem16u#15 rem16u#18
 Not aliassing across scopes: line_cursor#3 line_cursor#1
 Not aliassing across scopes: char_cursor#16 line_cursor#1
 Not aliassing across scopes: print_sword::w#1 main::sw#0
@@ -4013,70 +3996,60 @@ Not aliassing across scopes: char_cursor#17 char_cursor#24
 Not aliassing across scopes: char_cursor#18 char_cursor#2
 Not aliassing across scopes: char_cursor#19 char_cursor#2
 Not aliassing across scopes: sin16s_gen::wavelength#1 sin16s_gen::wavelength#0
-Not aliassing across scopes: rem16u#22 rem16u#20
+Not aliassing across scopes: rem16u#23 rem16u#21
 Not aliassing across scopes: sin16s_gen::sintab#4 sin16s_gen::sintab#0
 Not aliassing across scopes: div32u16u::dividend#0 PI2_u4f28#0
 Not aliassing across scopes: div32u16u::divisor#0 sin16s_gen::wavelength#1
-Not aliassing across scopes: div32u16u::return#0 div32u16u::return#1
-Not aliassing across scopes: rem16u#14 rem16u#17
-Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#0
+Not aliassing across scopes: div32u16u::return#2 div32u16u::return#0
+Not aliassing across scopes: rem16u#17 rem16u#13
+Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#2
 Not aliassing across scopes: sin16s::x#0 sin16s_gen::x#2
 Not aliassing across scopes: sin16s::return#0 sin16s::return#1
 Not aliassing across scopes: sin16s_gen::$1 sin16s::return#0
 Not aliassing across scopes: sin16s::x#3 sin16s::x#0
 Not aliassing across scopes: mul_u16_sel::v1#0 sin16s::x1#0
 Not aliassing across scopes: mul_u16_sel::v2#0 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x2#0 mul_u16_sel::return#0
 Not aliassing across scopes: mul_u16_sel::v1#1 sin16s::x2#0
 Not aliassing across scopes: mul_u16_sel::v2#1 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x3#0 mul_u16_sel::return#1
 Not aliassing across scopes: mul_u16_sel::v1#2 sin16s::x3#0
-Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#10
+Not aliassing across scopes: mul_u16_sel::return#2 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#2
 Not aliassing across scopes: mul_u16_sel::v1#3 sin16s::x3#0
 Not aliassing across scopes: mul_u16_sel::v2#3 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#10
 Not aliassing across scopes: mul_u16_sel::v1#4 sin16s::x4#0
 Not aliassing across scopes: mul_u16_sel::v2#4 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#12 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#12
-Not aliassing across scopes: mul_u16_sel::v1#5 sin16s::x5#0
-Not aliassing across scopes: mul_u16_sel::return#13 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5_128#0 mul_u16_sel::return#13
-Not aliassing across scopes: mul_u16_sel::v1#6 mul_u16_sel::v1#3
-Not aliassing across scopes: mul_u16_sel::v2#6 mul_u16_sel::v2#3
-Not aliassing across scopes: mul_u16_sel::select#6 mul_u16_sel::select#3
-Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#6
-Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#6
+Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::v1#5 mul_u16_sel::v1#3
+Not aliassing across scopes: mul_u16_sel::v2#5 mul_u16_sel::v2#3
+Not aliassing across scopes: mul_u16_sel::select#5 mul_u16_sel::select#3
+Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#5
+Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#5
 Not aliassing across scopes: mul16u::return#2 mul16u::res#2
 Not aliassing across scopes: mul_u16_sel::$0 mul16u::return#2
-Not aliassing across scopes: div32u16u::dividend#1 div32u16u::dividend#0
-Not aliassing across scopes: div32u16u::divisor#1 div32u16u::divisor#0
-Not aliassing across scopes: rem16u#24 rem16u#22
-Not aliassing across scopes: divr16u::divisor#0 div32u16u::divisor#1
-Not aliassing across scopes: divr16u::return#2 divr16u::return#0
-Not aliassing across scopes: rem16u#16 rem16u#1
-Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
-Not aliassing across scopes: divr16u::divisor#1 div32u16u::divisor#1
-Not aliassing across scopes: divr16u::rem#4 rem16u#16
-Not aliassing across scopes: divr16u::return#3 divr16u::return#0
-Not aliassing across scopes: rem16u#17 rem16u#1
-Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
-Not aliassing across scopes: rem16u#10 rem16u#13
+Not aliassing across scopes: rem16u#10 rem16u#16
 Not aliassing across scopes: line_cursor#5 line_cursor#11
 Not aliassing across scopes: char_cursor#21 char_cursor#18
 Self Phi Eliminated (word) divr16u::divisor#2
 Self Phi Eliminated (word) main::wavelength#1
-Self Phi Eliminated (word) rem16u#13
+Self Phi Eliminated (word) rem16u#16
 Self Phi Eliminated (byte*) line_cursor#11
 Self Phi Eliminated (dword) sin16s_gen::step#1
 Self Phi Eliminated (word) sin16s_gen::wavelength#2
-Self Phi Eliminated (word) rem16u#15
+Self Phi Eliminated (word) rem16u#18
 Succesful SSA optimization Pass2SelfPhiElimination
 Redundant Phi (word) divr16u::divisor#2 (word) divr16u::divisor#6
+Redundant Phi (dword) div32u16u::dividend#1 (dword) div32u16u::dividend#0
+Redundant Phi (word) div32u16u::divisor#1 (word) div32u16u::divisor#0
+Redundant Phi (word) rem16u#20 (word) rem16u#23
+Redundant Phi (word) rem16u#12 (word) rem16u#1
+Redundant Phi (word) rem16u#13 (word) rem16u#1
 Redundant Phi (word) mul16u::b#1 (word) mul16u::b#0
 Redundant Phi (word) mul16u::a#5 (word) mul16u::a#1
 Redundant Phi (signed word) print_sword::w#2 (signed word) print_sword::w#1
@@ -4089,32 +4062,27 @@ Redundant Phi (byte*) char_cursor#27 (byte*) char_cursor#10
 Redundant Phi (byte*) char_cursor#28 (byte*) char_cursor#10
 Redundant Phi (byte*) char_cursor#30 (byte*) char_cursor#12
 Redundant Phi (byte*) char_cursor#10 (byte*) char_cursor#12
-Redundant Phi (word) rem16u#20 (word) rem16u#0
+Redundant Phi (word) rem16u#21 (word) rem16u#0
 Redundant Phi (byte*) line_cursor#10 (byte*) SCREEN#0
 Redundant Phi (byte*) char_cursor#47 (byte*) SCREEN#0
-Redundant Phi (word) rem16u#12 (word) rem16u#15
+Redundant Phi (word) rem16u#15 (word) rem16u#18
 Redundant Phi (byte*) line_cursor#3 (byte*) line_cursor#1
 Redundant Phi (byte*) char_cursor#16 (byte*) line_cursor#1
 Redundant Phi (word) main::wavelength#1 (word) main::wavelength#0
-Redundant Phi (word) rem16u#13 (word) rem16u#12
+Redundant Phi (word) rem16u#16 (word) rem16u#15
 Redundant Phi (byte*) line_cursor#11 (byte*) line_cursor#3
 Redundant Phi (byte*) char_cursor#17 (byte*) char_cursor#24
 Redundant Phi (byte*) char_cursor#18 (byte*) char_cursor#2
 Redundant Phi (byte*) char_cursor#19 (byte*) char_cursor#2
 Redundant Phi (word) sin16s_gen::wavelength#1 (word) sin16s_gen::wavelength#0
-Redundant Phi (word) rem16u#22 (word) rem16u#20
+Redundant Phi (word) rem16u#23 (word) rem16u#21
 Redundant Phi (signed word*) sin16s_gen::sintab#4 (signed word*) sin16s_gen::sintab#0
-Redundant Phi (word) rem16u#14 (word) rem16u#17
+Redundant Phi (word) rem16u#17 (word) rem16u#13
 Redundant Phi (dword) sin16s_gen::step#1 (dword) sin16s_gen::step#0
 Redundant Phi (word) sin16s_gen::wavelength#2 (word) sin16s_gen::wavelength#1
-Redundant Phi (word) rem16u#15 (word) rem16u#14
+Redundant Phi (word) rem16u#18 (word) rem16u#17
 Redundant Phi (dword) sin16s::x#3 (dword) sin16s::x#0
-Redundant Phi (dword) div32u16u::dividend#1 (dword) div32u16u::dividend#0
-Redundant Phi (word) div32u16u::divisor#1 (word) div32u16u::divisor#0
-Redundant Phi (word) rem16u#24 (word) rem16u#22
-Redundant Phi (word) rem16u#16 (word) rem16u#1
-Redundant Phi (word) rem16u#17 (word) rem16u#1
-Redundant Phi (word) rem16u#10 (word) rem16u#13
+Redundant Phi (word) rem16u#10 (word) rem16u#16
 Redundant Phi (byte*) line_cursor#5 (byte*) line_cursor#11
 Redundant Phi (byte*) char_cursor#21 (byte*) char_cursor#18
 Succesful SSA optimization Pass2RedundantPhiElimination
@@ -4131,11 +4099,12 @@ Simple Condition (boolean~) main::$10 if((signed word*) main::st1#1<(signed word
 Simple Condition (boolean~) sin16s_gen::$4 if((word) sin16s_gen::i#1<(word) sin16s_gen::wavelength#0) goto sin16s_gen::@1
 Simple Condition (boolean~) sin16s::$1 if((dword) sin16s::x#0<(dword) PI_u4f28#0) goto sin16s::@1
 Simple Condition (boolean~) sin16s::$4 if((dword) sin16s::x#4<(dword) PI_HALF_u4f28#0) goto sin16s::@2
-Simple Condition (boolean~) sin16s::$20 if((byte) sin16s::isUpper#10==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@3
+Simple Condition (boolean~) sin16s::$19 if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@3
 Succesful SSA optimization Pass2ConditionalJumpSimplification
 Constant (const word) rem16u#0 = 0
 Constant (const word) divr16u::quotient#0 = 0
 Constant (const byte) divr16u::i#0 = 0
+Constant (const word) divr16u::rem#3 = 0
 Constant (const dword) mul16u::res#0 = 0
 Constant (const byte*) SCREEN#0 = ((byte*))1024
 Constant (const byte) print_char::ch#0 = '-'
@@ -4157,9 +4126,6 @@ Constant (const word) mul_u16_sel::v2#2 = 65536/6
 Constant (const byte) mul_u16_sel::select#2 = 1
 Constant (const byte) mul_u16_sel::select#3 = 0
 Constant (const byte) mul_u16_sel::select#4 = 0
-Constant (const word) mul_u16_sel::v2#5 = 65536/128
-Constant (const byte) mul_u16_sel::select#5 = 3
-Constant (const word) divr16u::rem#3 = 0
 Succesful SSA optimization Pass2ConstantIdentification
 Constant (const byte*) print_cls::sc#0 = SCREEN#0
 Constant (const byte*) print_cls::$0 = SCREEN#0+1000
@@ -4169,10 +4135,10 @@ Constant (const word) sin16s_gen::wavelength#0 = main::wavelength#0
 Constant (const word) main::$8 = main::wavelength#0*2
 Constant (const dword) div32u16u::dividend#0 = PI2_u4f28#0
 Succesful SSA optimization Pass2ConstantIdentification
-Constant (const signed word*) main::$9 = main::sintab1#0+main::$8
-Constant (const word) div32u16u::divisor#0 = sin16s_gen::wavelength#0
 Constant (const word) divr16u::dividend#1 = >div32u16u::dividend#0
 Constant (const word) divr16u::dividend#2 = <div32u16u::dividend#0
+Constant (const signed word*) main::$9 = main::sintab1#0+main::$8
+Constant (const word) div32u16u::divisor#0 = sin16s_gen::wavelength#0
 Succesful SSA optimization Pass2ConstantIdentification
 Constant (const word) divr16u::divisor#0 = div32u16u::divisor#0
 Constant (const word) divr16u::divisor#1 = div32u16u::divisor#0
@@ -4184,21 +4150,26 @@ Eliminating unused constant (const word) rem16u#0
 Succesful SSA optimization PassNEliminateUnusedVars
 Eliminating Noop Cast (word) print_word::w#0 ← ((word)) (signed word) print_sword::w#3
 Eliminating Noop Cast (signed word) sin16s::sinx#0 ← ((signed word)) (word) sin16s::usinx#1
-Eliminating Noop Cast (signed word~) sin16s::$21 ← ((signed word)) (word) sin16s::usinx#1
+Eliminating Noop Cast (signed word~) sin16s::$20 ← ((signed word)) (word) sin16s::usinx#1
 Succesful SSA optimization Pass2NopCastElimination
 Culled Empty Block (label) @2
 Culled Empty Block (label) mul16u::@3
-Culled Empty Block (label) @10
+Culled Empty Block (label) @11
 Culled Empty Block (label) print_sword::@3
 Culled Empty Block (label) print_word::@2
 Culled Empty Block (label) print_byte::@2
 Culled Empty Block (label) print_cls::@2
 Culled Empty Block (label) main::@6
 Culled Empty Block (label) main::@9
-Culled Empty Block (label) @21
+Culled Empty Block (label) @22
 Culled Empty Block (label) @27
 Succesful SSA optimization Pass2CullEmptyBlocks
 Not aliassing across scopes: rem16u#1 divr16u::rem#11
+Not aliassing across scopes: divr16u::return#2 divr16u::return#0
+Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
+Not aliassing across scopes: divr16u::rem#4 rem16u#1
+Not aliassing across scopes: divr16u::return#3 divr16u::return#0
+Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
 Not aliassing across scopes: mul16u::a#2 mul16u::a#1
 Not aliassing across scopes: char_cursor#51 char_cursor#49
 Not aliassing across scopes: print_sword::w#3 print_sword::w#1
@@ -4208,48 +4179,45 @@ Not aliassing across scopes: char_cursor#46 char_cursor#43
 Not aliassing across scopes: print_char::ch#3 print_char::ch#1
 Not aliassing across scopes: char_cursor#33 char_cursor#46
 Not aliassing across scopes: print_sword::w#1 main::sw#0
-Not aliassing across scopes: div32u16u::return#0 div32u16u::return#1
-Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#0
+Not aliassing across scopes: div32u16u::return#2 div32u16u::return#0
+Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#2
 Not aliassing across scopes: sin16s::x#0 sin16s_gen::x#2
 Not aliassing across scopes: sin16s::return#0 sin16s::return#1
 Not aliassing across scopes: sin16s_gen::$1 sin16s::return#0
 Not aliassing across scopes: sin16s::x#4 sin16s::x#0
 Not aliassing across scopes: mul_u16_sel::v1#0 sin16s::x1#0
 Not aliassing across scopes: mul_u16_sel::v2#0 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x2#0 mul_u16_sel::return#0
 Not aliassing across scopes: mul_u16_sel::v1#1 sin16s::x2#0
 Not aliassing across scopes: mul_u16_sel::v2#1 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x3#0 mul_u16_sel::return#1
 Not aliassing across scopes: mul_u16_sel::v1#2 sin16s::x3#0
-Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#10
+Not aliassing across scopes: mul_u16_sel::return#2 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#2
 Not aliassing across scopes: mul_u16_sel::v1#3 sin16s::x3#0
 Not aliassing across scopes: mul_u16_sel::v2#3 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#10
 Not aliassing across scopes: mul_u16_sel::v1#4 sin16s::x4#0
 Not aliassing across scopes: mul_u16_sel::v2#4 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#12 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#12
-Not aliassing across scopes: mul_u16_sel::v1#5 sin16s::x5#0
-Not aliassing across scopes: mul_u16_sel::return#13 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5_128#0 mul_u16_sel::return#13
-Not aliassing across scopes: mul_u16_sel::v1#6 mul_u16_sel::v1#3
-Not aliassing across scopes: mul_u16_sel::v2#6 mul_u16_sel::v2#3
-Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#6
-Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#6
+Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::v1#5 mul_u16_sel::v1#3
+Not aliassing across scopes: mul_u16_sel::v2#5 mul_u16_sel::v2#3
+Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#5
+Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#5
 Not aliassing across scopes: mul16u::return#2 mul16u::res#2
 Not aliassing across scopes: mul_u16_sel::$0 mul16u::return#2
-Not aliassing across scopes: divr16u::return#2 divr16u::return#0
-Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
-Not aliassing across scopes: divr16u::rem#4 rem16u#1
-Not aliassing across scopes: divr16u::return#3 divr16u::return#0
-Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
-Alias (dword) div32u16u::return#1 = (dword~) div32u16u::$4 
+Alias (dword) div32u16u::return#0 = (dword~) div32u16u::$4 
 Succesful SSA optimization Pass2AliasElimination
 Not aliassing across scopes: rem16u#1 divr16u::rem#11
+Not aliassing across scopes: divr16u::return#2 divr16u::return#0
+Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
+Not aliassing across scopes: divr16u::rem#4 rem16u#1
+Not aliassing across scopes: divr16u::return#3 divr16u::return#0
+Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
 Not aliassing across scopes: mul16u::a#2 mul16u::a#1
 Not aliassing across scopes: char_cursor#51 char_cursor#49
 Not aliassing across scopes: print_sword::w#3 print_sword::w#1
@@ -4259,47 +4227,44 @@ Not aliassing across scopes: char_cursor#46 char_cursor#43
 Not aliassing across scopes: print_char::ch#3 print_char::ch#1
 Not aliassing across scopes: char_cursor#33 char_cursor#46
 Not aliassing across scopes: print_sword::w#1 main::sw#0
-Not aliassing across scopes: div32u16u::return#0 div32u16u::return#1
-Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#0
+Not aliassing across scopes: div32u16u::return#2 div32u16u::return#0
+Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#2
 Not aliassing across scopes: sin16s::x#0 sin16s_gen::x#2
 Not aliassing across scopes: sin16s::return#0 sin16s::return#1
 Not aliassing across scopes: sin16s_gen::$1 sin16s::return#0
 Not aliassing across scopes: sin16s::x#4 sin16s::x#0
 Not aliassing across scopes: mul_u16_sel::v1#0 sin16s::x1#0
 Not aliassing across scopes: mul_u16_sel::v2#0 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x2#0 mul_u16_sel::return#0
 Not aliassing across scopes: mul_u16_sel::v1#1 sin16s::x2#0
 Not aliassing across scopes: mul_u16_sel::v2#1 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x3#0 mul_u16_sel::return#1
 Not aliassing across scopes: mul_u16_sel::v1#2 sin16s::x3#0
-Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#10
+Not aliassing across scopes: mul_u16_sel::return#2 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#2
 Not aliassing across scopes: mul_u16_sel::v1#3 sin16s::x3#0
 Not aliassing across scopes: mul_u16_sel::v2#3 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#10
 Not aliassing across scopes: mul_u16_sel::v1#4 sin16s::x4#0
 Not aliassing across scopes: mul_u16_sel::v2#4 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#12 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#12
-Not aliassing across scopes: mul_u16_sel::v1#5 sin16s::x5#0
-Not aliassing across scopes: mul_u16_sel::return#13 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5_128#0 mul_u16_sel::return#13
-Not aliassing across scopes: mul_u16_sel::v1#6 mul_u16_sel::v1#3
-Not aliassing across scopes: mul_u16_sel::v2#6 mul_u16_sel::v2#3
-Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#6
-Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#6
+Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::v1#5 mul_u16_sel::v1#3
+Not aliassing across scopes: mul_u16_sel::v2#5 mul_u16_sel::v2#3
+Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#5
+Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#5
 Not aliassing across scopes: mul16u::return#2 mul16u::res#2
 Not aliassing across scopes: mul_u16_sel::$0 mul16u::return#2
-Not aliassing across scopes: divr16u::return#2 divr16u::return#0
-Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
-Not aliassing across scopes: divr16u::rem#4 rem16u#1
-Not aliassing across scopes: divr16u::return#3 divr16u::return#0
-Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
 Multiple usages for variable. Not optimizing sub-constant (signed word*) main::st1#2
 Not aliassing across scopes: rem16u#1 divr16u::rem#11
+Not aliassing across scopes: divr16u::return#2 divr16u::return#0
+Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
+Not aliassing across scopes: divr16u::rem#4 rem16u#1
+Not aliassing across scopes: divr16u::return#3 divr16u::return#0
+Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
 Not aliassing across scopes: mul16u::a#2 mul16u::a#1
 Not aliassing across scopes: char_cursor#51 char_cursor#49
 Not aliassing across scopes: print_sword::w#3 print_sword::w#1
@@ -4309,45 +4274,37 @@ Not aliassing across scopes: char_cursor#46 char_cursor#43
 Not aliassing across scopes: print_char::ch#3 print_char::ch#1
 Not aliassing across scopes: char_cursor#33 char_cursor#46
 Not aliassing across scopes: print_sword::w#1 main::sw#0
-Not aliassing across scopes: div32u16u::return#0 div32u16u::return#1
-Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#0
+Not aliassing across scopes: div32u16u::return#2 div32u16u::return#0
+Not aliassing across scopes: sin16s_gen::step#0 div32u16u::return#2
 Not aliassing across scopes: sin16s::x#0 sin16s_gen::x#2
 Not aliassing across scopes: sin16s::return#0 sin16s::return#1
 Not aliassing across scopes: sin16s_gen::$1 sin16s::return#0
 Not aliassing across scopes: sin16s::x#4 sin16s::x#0
 Not aliassing across scopes: mul_u16_sel::v1#0 sin16s::x1#0
 Not aliassing across scopes: mul_u16_sel::v2#0 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#0 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x2#0 mul_u16_sel::return#0
 Not aliassing across scopes: mul_u16_sel::v1#1 sin16s::x2#0
 Not aliassing across scopes: mul_u16_sel::v2#1 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#14
+Not aliassing across scopes: mul_u16_sel::return#1 mul_u16_sel::return#12
 Not aliassing across scopes: sin16s::x3#0 mul_u16_sel::return#1
 Not aliassing across scopes: mul_u16_sel::v1#2 sin16s::x3#0
-Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#10
+Not aliassing across scopes: mul_u16_sel::return#2 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x3_6#0 mul_u16_sel::return#2
 Not aliassing across scopes: mul_u16_sel::v1#3 sin16s::x3#0
 Not aliassing across scopes: mul_u16_sel::v2#3 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::return#10 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x4#0 mul_u16_sel::return#10
 Not aliassing across scopes: mul_u16_sel::v1#4 sin16s::x4#0
 Not aliassing across scopes: mul_u16_sel::v2#4 sin16s::x1#0
-Not aliassing across scopes: mul_u16_sel::return#12 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#12
-Not aliassing across scopes: mul_u16_sel::v1#5 sin16s::x5#0
-Not aliassing across scopes: mul_u16_sel::return#13 mul_u16_sel::return#14
-Not aliassing across scopes: sin16s::x5_128#0 mul_u16_sel::return#13
-Not aliassing across scopes: mul_u16_sel::v1#6 mul_u16_sel::v1#3
-Not aliassing across scopes: mul_u16_sel::v2#6 mul_u16_sel::v2#3
-Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#6
-Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#6
+Not aliassing across scopes: mul_u16_sel::return#11 mul_u16_sel::return#12
+Not aliassing across scopes: sin16s::x5#0 mul_u16_sel::return#11
+Not aliassing across scopes: mul_u16_sel::v1#5 mul_u16_sel::v1#3
+Not aliassing across scopes: mul_u16_sel::v2#5 mul_u16_sel::v2#3
+Not aliassing across scopes: mul16u::a#1 mul_u16_sel::v1#5
+Not aliassing across scopes: mul16u::b#0 mul_u16_sel::v2#5
 Not aliassing across scopes: mul16u::return#2 mul16u::res#2
 Not aliassing across scopes: mul_u16_sel::$0 mul16u::return#2
-Not aliassing across scopes: divr16u::return#2 divr16u::return#0
-Not aliassing across scopes: div32u16u::quotient_hi#0 divr16u::return#2
-Not aliassing across scopes: divr16u::rem#4 rem16u#1
-Not aliassing across scopes: divr16u::return#3 divr16u::return#0
-Not aliassing across scopes: div32u16u::quotient_lo#0 divr16u::return#3
 Multiple usages for variable. Not optimizing sub-constant (signed word*) main::st1#2
 OPTIMIZING CONTROL FLOW GRAPH
 Inlining constant with var siblings (const word) divr16u::quotient#0
@@ -4400,43 +4357,25 @@ Inlining constant with different constant siblings (const byte) sin16s::isUpper#
 Inlining constant with var siblings (const byte) mul_u16_sel::select#0
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#0
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#0
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#0
 Inlining constant with var siblings (const byte) mul_u16_sel::select#1
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#1
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#1
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#1
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#1
 Inlining constant with var siblings (const word) mul_u16_sel::v2#2
 Inlining constant with var siblings (const word) mul_u16_sel::v2#2
 Inlining constant with var siblings (const word) mul_u16_sel::v2#2
 Inlining constant with var siblings (const word) mul_u16_sel::v2#2
 Inlining constant with var siblings (const word) mul_u16_sel::v2#2
-Inlining constant with different constant siblings (const word) mul_u16_sel::v2#2
 Inlining constant with var siblings (const byte) mul_u16_sel::select#2
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#2
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#2
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#2
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#2
 Inlining constant with var siblings (const byte) mul_u16_sel::select#3
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#3
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#3
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#3
 Inlining constant with var siblings (const byte) mul_u16_sel::select#4
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#4
 Inlining constant with different constant siblings (const byte) mul_u16_sel::select#4
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#4
-Inlining constant with var siblings (const word) mul_u16_sel::v2#5
-Inlining constant with var siblings (const word) mul_u16_sel::v2#5
-Inlining constant with var siblings (const word) mul_u16_sel::v2#5
-Inlining constant with var siblings (const word) mul_u16_sel::v2#5
-Inlining constant with var siblings (const word) mul_u16_sel::v2#5
-Inlining constant with different constant siblings (const word) mul_u16_sel::v2#5
-Inlining constant with var siblings (const byte) mul_u16_sel::select#5
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#5
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#5
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#5
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#5
-Inlining constant with different constant siblings (const byte) mul_u16_sel::select#5
 Constant inlined divr16u::rem#3 = (byte/signed byte/word/signed word/dword/signed dword) 0
 Constant inlined print_cls::$0 = (const byte*) SCREEN#0+(word/signed word/dword/signed dword) 1000
 Constant inlined divr16u::i#0 = (byte/signed byte/word/signed word/dword/signed dword) 0
@@ -4454,38 +4393,36 @@ Constant inlined print_cls::sc#0 = (const byte*) SCREEN#0
 Constant inlined sin16s_gen::sintab#0 = (const signed word[120]) main::sintab1#0
 Constant inlined divr16u::dividend#1 = >(const dword) PI2_u4f28#0
 Constant inlined divr16u::dividend#2 = <(const dword) PI2_u4f28#0
-Constant inlined mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 3
 Constant inlined mul_u16_sel::v2#2 = (dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6
 Constant inlined print_char::ch#0 = (byte) '-'
 Constant inlined sin16s_gen::x#0 = (byte/signed byte/word/signed word/dword/signed dword) 0
 Constant inlined print_str::str#2 = (const string) main::str1
+Constant inlined div32u16u::divisor#0 = (const word) main::wavelength#0
 Constant inlined print_str::str#1 = (const string) main::str
 Constant inlined print_byte::$4 = (const string) print_byte::hextab#0
-Constant inlined div32u16u::divisor#0 = (const word) main::wavelength#0
 Constant inlined mul_u16_sel::select#0 = (byte/signed byte/word/signed word/dword/signed dword) 0
 Constant inlined main::$9 = (const signed word[120]) main::sintab1#0+(const word) main::wavelength#0*(byte/signed byte/word/signed word/dword/signed dword) 2
 Constant inlined mul_u16_sel::select#1 = (byte/signed byte/word/signed word/dword/signed dword) 1
-Constant inlined mul_u16_sel::v2#5 = (dword/signed dword) 65536/(byte/word/signed word/dword/signed dword) 128
 Constant inlined mul_u16_sel::select#2 = (byte/signed byte/word/signed word/dword/signed dword) 1
 Constant inlined mul_u16_sel::select#3 = (byte/signed byte/word/signed word/dword/signed dword) 0
 Constant inlined main::$8 = (const word) main::wavelength#0*(byte/signed byte/word/signed word/dword/signed dword) 2
 Constant inlined mul_u16_sel::select#4 = (byte/signed byte/word/signed word/dword/signed dword) 0
 Succesful SSA optimization Pass2ConstantInlining
-Block Sequence Planned @begin @26 @end main main::@5 main::@1 main::@3 main::@2 main::@7 main::@8 main::@return print_str print_str::@1 print_str::@return print_str::@2 print_sword print_sword::@2 print_sword::@4 print_sword::@1 print_sword::@return print_word print_word::@1 print_word::@return print_byte print_byte::@1 print_byte::@return print_char print_char::@return print_cls print_cls::@1 print_cls::@return sin16s_gen sin16s_gen::@3 sin16s_gen::@1 sin16s_gen::@4 sin16s_gen::@return sin16s sin16s::@4 sin16s::@1 sin16s::@5 sin16s::@2 sin16s::@8 sin16s::@9 sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@13 sin16s::@6 sin16s::@3 sin16s::@return mul_u16_sel mul_u16_sel::@2 mul_u16_sel::@return mul16u mul16u::@1 mul16u::@return mul16u::@2 mul16u::@7 mul16u::@4 div32u16u div32u16u::@2 div32u16u::@3 div32u16u::@return divr16u divr16u::@1 divr16u::@4 divr16u::@2 divr16u::@5 divr16u::@3 divr16u::@6 divr16u::@return 
+Block Sequence Planned @begin @26 @end main main::@5 main::@1 main::@3 main::@2 main::@7 main::@8 main::@return print_str print_str::@1 print_str::@return print_str::@2 print_sword print_sword::@2 print_sword::@4 print_sword::@1 print_sword::@return print_word print_word::@1 print_word::@return print_byte print_byte::@1 print_byte::@return print_char print_char::@return print_cls print_cls::@1 print_cls::@return sin16s_gen sin16s_gen::@3 sin16s_gen::@1 sin16s_gen::@4 sin16s_gen::@return sin16s sin16s::@4 sin16s::@1 sin16s::@5 sin16s::@2 sin16s::@8 sin16s::@9 sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@6 sin16s::@3 sin16s::@return mul_u16_sel mul_u16_sel::@2 mul_u16_sel::@return mul16u mul16u::@1 mul16u::@return mul16u::@2 mul16u::@7 mul16u::@4 div32u16u div32u16u::@2 div32u16u::@3 div32u16u::@return divr16u divr16u::@1 divr16u::@4 divr16u::@2 divr16u::@5 divr16u::@3 divr16u::@6 divr16u::@return 
 Added new block during phi lifting main::@10(between main::@8 and main::@1)
 Added new block during phi lifting main::@11(between main::@1 and main::@2)
 Added new block during phi lifting print_sword::@5(between print_sword and print_sword::@1)
 Added new block during phi lifting print_cls::@3(between print_cls::@1 and print_cls::@1)
 Added new block during phi lifting sin16s_gen::@5(between sin16s_gen::@4 and sin16s_gen::@1)
-Added new block during phi lifting sin16s::@14(between sin16s and sin16s::@1)
-Fixing phi predecessor for sin16s::isUpper#10 to new block ( sin16s -> sin16s::@14 ) during phi lifting.
-Added new block during phi lifting sin16s::@15(between sin16s::@1 and sin16s::@2)
-Added new block during phi lifting sin16s::@16(between sin16s::@13 and sin16s::@3)
+Added new block during phi lifting sin16s::@13(between sin16s and sin16s::@1)
+Fixing phi predecessor for sin16s::isUpper#2 to new block ( sin16s -> sin16s::@13 ) during phi lifting.
+Added new block during phi lifting sin16s::@14(between sin16s::@1 and sin16s::@2)
+Added new block during phi lifting sin16s::@15(between sin16s::@12 and sin16s::@3)
 Added new block during phi lifting mul16u::@10(between mul16u::@2 and mul16u::@4)
 Added new block during phi lifting divr16u::@8(between divr16u::@3 and divr16u::@1)
 Added new block during phi lifting divr16u::@9(between divr16u::@1 and divr16u::@2)
 Added new block during phi lifting divr16u::@10(between divr16u::@2 and divr16u::@3)
-Block Sequence Planned @begin @26 @end main main::@5 main::@1 main::@3 main::@2 main::@7 main::@8 main::@return main::@10 main::@11 print_str print_str::@1 print_str::@return print_str::@2 print_sword print_sword::@2 print_sword::@4 print_sword::@1 print_sword::@return print_sword::@5 print_word print_word::@1 print_word::@return print_byte print_byte::@1 print_byte::@return print_char print_char::@return print_cls print_cls::@1 print_cls::@return print_cls::@3 sin16s_gen sin16s_gen::@3 sin16s_gen::@1 sin16s_gen::@4 sin16s_gen::@return sin16s_gen::@5 sin16s sin16s::@4 sin16s::@1 sin16s::@5 sin16s::@2 sin16s::@8 sin16s::@9 sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@13 sin16s::@6 sin16s::@3 sin16s::@return sin16s::@16 sin16s::@15 sin16s::@14 mul_u16_sel mul_u16_sel::@2 mul_u16_sel::@return mul16u mul16u::@1 mul16u::@return mul16u::@2 mul16u::@7 mul16u::@4 mul16u::@10 div32u16u div32u16u::@2 div32u16u::@3 div32u16u::@return divr16u divr16u::@1 divr16u::@4 divr16u::@2 divr16u::@5 divr16u::@3 divr16u::@6 divr16u::@return divr16u::@8 divr16u::@10 divr16u::@9 
+Block Sequence Planned @begin @26 @end main main::@5 main::@1 main::@3 main::@2 main::@7 main::@8 main::@return main::@10 main::@11 print_str print_str::@1 print_str::@return print_str::@2 print_sword print_sword::@2 print_sword::@4 print_sword::@1 print_sword::@return print_sword::@5 print_word print_word::@1 print_word::@return print_byte print_byte::@1 print_byte::@return print_char print_char::@return print_cls print_cls::@1 print_cls::@return print_cls::@3 sin16s_gen sin16s_gen::@3 sin16s_gen::@1 sin16s_gen::@4 sin16s_gen::@return sin16s_gen::@5 sin16s sin16s::@4 sin16s::@1 sin16s::@5 sin16s::@2 sin16s::@8 sin16s::@9 sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@6 sin16s::@3 sin16s::@return sin16s::@15 sin16s::@14 sin16s::@13 mul_u16_sel mul_u16_sel::@2 mul_u16_sel::@return mul16u mul16u::@1 mul16u::@return mul16u::@2 mul16u::@7 mul16u::@4 mul16u::@10 div32u16u div32u16u::@2 div32u16u::@3 div32u16u::@return divr16u divr16u::@1 divr16u::@4 divr16u::@2 divr16u::@5 divr16u::@3 divr16u::@6 divr16u::@return divr16u::@8 divr16u::@10 divr16u::@9 
 Adding NOP phi() at start of @begin
 Adding NOP phi() at start of @26
 Adding NOP phi() at start of @end
@@ -4501,9 +4438,9 @@ Calls in [print_sword] to print_char:38 print_word:43
 Calls in [print_word] to print_byte:50 print_byte:54 
 Calls in [print_byte] to print_char:61 print_char:66 
 Calls in [sin16s_gen] to div32u16u:80 sin16s:85 
-Calls in [sin16s] to mul_u16_sel:111 mul_u16_sel:118 mul_u16_sel:123 mul_u16_sel:131 mul_u16_sel:138 mul_u16_sel:143 
-Calls in [mul_u16_sel] to mul16u:158 
-Calls in [div32u16u] to divr16u:182 divr16u:187 
+Calls in [sin16s] to mul_u16_sel:111 mul_u16_sel:118 mul_u16_sel:123 mul_u16_sel:131 mul_u16_sel:138 
+Calls in [mul_u16_sel] to mul16u:154 
+Calls in [div32u16u] to divr16u:178 divr16u:183 
 
 Propagating live ranges...
 Propagating live ranges...
@@ -4547,10 +4484,6 @@ Propagating live ranges...
 Propagating live ranges...
 Propagating live ranges...
 Propagating live ranges...
-Propagating live ranges...
-Propagating live ranges...
-Propagating live ranges...
-Propagating live ranges...
 Created 38 initial phi equivalence classes
 Coalesced [11] char_cursor#59 ← char_cursor#49
 Coalesced [13] char_cursor#58 ← char_cursor#2
@@ -4581,52 +4514,51 @@ Coalesced [95] sin16s_gen::sintab#6 ← sin16s_gen::sintab#1
 Coalesced [96] sin16s_gen::i#4 ← sin16s_gen::i#1
 Coalesced [99] sin16s::x#9 ← sin16s::x#1
 Coalesced [103] sin16s::x#11 ← sin16s::x#2
-Coalesced [109] mul_u16_sel::v1#10 ← mul_u16_sel::v1#0
-Coalesced [110] mul_u16_sel::v2#9 ← mul_u16_sel::v2#0
-Coalesced [116] mul_u16_sel::v1#11 ← mul_u16_sel::v1#1
-Coalesced [117] mul_u16_sel::v2#10 ← mul_u16_sel::v2#1
-Coalesced [122] mul_u16_sel::v1#12 ← mul_u16_sel::v1#2
-Coalesced [129] mul_u16_sel::v1#7 ← mul_u16_sel::v1#3
-Coalesced [130] mul_u16_sel::v2#7 ← mul_u16_sel::v2#3
-Coalesced [136] mul_u16_sel::v1#8 ← mul_u16_sel::v1#4
-Coalesced [137] mul_u16_sel::v2#8 ← mul_u16_sel::v2#4
-Coalesced [142] mul_u16_sel::v1#9 ← mul_u16_sel::v1#5
-Coalesced [149] sin16s::return#6 ← sin16s::sinx#1
-Coalesced [153] sin16s::x#10 ← sin16s::x#4
-Coalesced [154] sin16s::x#8 ← sin16s::x#0
-Coalesced [165] mul16u::a#7 ← mul16u::a#1
-Coalesced [166] mul16u::mb#6 ← mul16u::mb#0
-Coalesced [173] mul16u::res#9 ← mul16u::res#1
-Coalesced [177] mul16u::a#8 ← mul16u::a#0
-Coalesced [178] mul16u::res#7 ← mul16u::res#6
-Coalesced [179] mul16u::mb#7 ← mul16u::mb#1
-Coalesced (already) [180] mul16u::res#8 ← mul16u::res#2
-Coalesced [186] divr16u::rem#12 ← divr16u::rem#4
-Coalesced [193] divr16u::rem#13 ← divr16u::rem#10
-Coalesced [194] divr16u::dividend#9 ← divr16u::dividend#5
-Coalesced [201] divr16u::rem#16 ← divr16u::rem#1
-Coalesced [208] divr16u::rem#18 ← divr16u::rem#2
-Coalesced [209] divr16u::return#8 ← divr16u::quotient#2
-Coalesced [215] divr16u::rem#14 ← divr16u::rem#11
-Coalesced [216] divr16u::dividend#10 ← divr16u::dividend#0
-Coalesced [217] divr16u::quotient#9 ← divr16u::return#0
-Coalesced [218] divr16u::i#7 ← divr16u::i#1
-Coalesced [219] divr16u::rem#17 ← divr16u::rem#6
-Coalesced [220] divr16u::return#7 ← divr16u::quotient#1
-Coalesced [221] divr16u::rem#15 ← divr16u::rem#0
+Coalesced [109] mul_u16_sel::v1#8 ← mul_u16_sel::v1#0
+Coalesced [110] mul_u16_sel::v2#8 ← mul_u16_sel::v2#0
+Coalesced [116] mul_u16_sel::v1#9 ← mul_u16_sel::v1#1
+Coalesced [117] mul_u16_sel::v2#9 ← mul_u16_sel::v2#1
+Coalesced [122] mul_u16_sel::v1#10 ← mul_u16_sel::v1#2
+Coalesced [129] mul_u16_sel::v1#6 ← mul_u16_sel::v1#3
+Coalesced [130] mul_u16_sel::v2#6 ← mul_u16_sel::v2#3
+Coalesced [136] mul_u16_sel::v1#7 ← mul_u16_sel::v1#4
+Coalesced [137] mul_u16_sel::v2#7 ← mul_u16_sel::v2#4
+Coalesced [145] sin16s::return#6 ← sin16s::sinx#1
+Coalesced [149] sin16s::x#10 ← sin16s::x#4
+Coalesced [150] sin16s::x#8 ← sin16s::x#0
+Coalesced [161] mul16u::a#7 ← mul16u::a#1
+Coalesced [162] mul16u::mb#6 ← mul16u::mb#0
+Coalesced [169] mul16u::res#9 ← mul16u::res#1
+Coalesced [173] mul16u::a#8 ← mul16u::a#0
+Coalesced [174] mul16u::res#7 ← mul16u::res#6
+Coalesced [175] mul16u::mb#7 ← mul16u::mb#1
+Coalesced (already) [176] mul16u::res#8 ← mul16u::res#2
+Coalesced [182] divr16u::rem#12 ← divr16u::rem#4
+Coalesced [189] divr16u::rem#13 ← divr16u::rem#10
+Coalesced [190] divr16u::dividend#9 ← divr16u::dividend#5
+Coalesced [197] divr16u::rem#16 ← divr16u::rem#1
+Coalesced [204] divr16u::rem#18 ← divr16u::rem#2
+Coalesced [205] divr16u::return#8 ← divr16u::quotient#2
+Coalesced [211] divr16u::rem#14 ← divr16u::rem#11
+Coalesced [212] divr16u::dividend#10 ← divr16u::dividend#0
+Coalesced [213] divr16u::quotient#9 ← divr16u::return#0
+Coalesced [214] divr16u::i#7 ← divr16u::i#1
+Coalesced [215] divr16u::rem#17 ← divr16u::rem#6
+Coalesced [216] divr16u::return#7 ← divr16u::quotient#1
+Coalesced [217] divr16u::rem#15 ← divr16u::rem#0
 Coalesced down to 24 phi equivalence classes
 Culled Empty Block (label) main::@10
 Culled Empty Block (label) main::@11
 Culled Empty Block (label) print_sword::@5
 Culled Empty Block (label) print_cls::@3
 Culled Empty Block (label) sin16s_gen::@5
-Culled Empty Block (label) sin16s::@15
 Culled Empty Block (label) sin16s::@14
+Culled Empty Block (label) sin16s::@13
 Culled Empty Block (label) mul16u::@10
 Culled Empty Block (label) divr16u::@8
 Culled Empty Block (label) divr16u::@10
 Culled Empty Block (label) divr16u::@9
-Block Sequence Planned @begin @26 @end main main::@5 main::@1 main::@3 main::@2 main::@7 main::@8 main::@return print_str print_str::@1 print_str::@return print_str::@2 print_sword print_sword::@2 print_sword::@4 print_sword::@1 print_sword::@return print_word print_word::@1 print_word::@return print_byte print_byte::@1 print_byte::@return print_char print_char::@return print_cls print_cls::@1 print_cls::@return sin16s_gen sin16s_gen::@3 sin16s_gen::@1 sin16s_gen::@4 sin16s_gen::@return sin16s sin16s::@4 sin16s::@1 sin16s::@5 sin16s::@2 sin16s::@8 sin16s::@9 sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@13 sin16s::@6 sin16s::@3 sin16s::@return sin16s::@16 mul_u16_sel mul_u16_sel::@2 mul_u16_sel::@return mul16u mul16u::@1 mul16u::@return mul16u::@2 mul16u::@7 mul16u::@4 div32u16u div32u16u::@2 div32u16u::@3 div32u16u::@return divr16u divr16u::@1 divr16u::@4 divr16u::@2 divr16u::@5 divr16u::@3 divr16u::@6 divr16u::@return 
+Block Sequence Planned @begin @26 @end main main::@5 main::@1 main::@3 main::@2 main::@7 main::@8 main::@return print_str print_str::@1 print_str::@return print_str::@2 print_sword print_sword::@2 print_sword::@4 print_sword::@1 print_sword::@return print_word print_word::@1 print_word::@return print_byte print_byte::@1 print_byte::@return print_char print_char::@return print_cls print_cls::@1 print_cls::@return sin16s_gen sin16s_gen::@3 sin16s_gen::@1 sin16s_gen::@4 sin16s_gen::@return sin16s sin16s::@4 sin16s::@1 sin16s::@5 sin16s::@2 sin16s::@8 sin16s::@9 sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@6 sin16s::@3 sin16s::@return sin16s::@15 mul_u16_sel mul_u16_sel::@2 mul_u16_sel::@return mul16u mul16u::@1 mul16u::@return mul16u::@2 mul16u::@7 mul16u::@4 div32u16u div32u16u::@2 div32u16u::@3 div32u16u::@return divr16u divr16u::@1 divr16u::@4 divr16u::@2 divr16u::@5 divr16u::@3 divr16u::@6 divr16u::@return 
 Adding NOP phi() at start of @begin
 Adding NOP phi() at start of @26
 Adding NOP phi() at start of @end
@@ -4671,9 +4603,6 @@ Propagating live ranges...
 Propagating live ranges...
 Propagating live ranges...
 Propagating live ranges...
-Propagating live ranges...
-Propagating live ranges...
-Propagating live ranges...
 
 FINAL CONTROL FLOW GRAPH
 @begin: scope:[]  from
@@ -4803,11 +4732,11 @@ print_cls::@return: scope:[print_cls]  from print_cls::@1
   to:@return
 sin16s_gen: scope:[sin16s_gen]  from main
   [58] phi() [ ] ( main:2::sin16s_gen:5 [ ] )
-  [59] call div32u16u param-assignment [ div32u16u::return#1 ] ( main:2::sin16s_gen:5 [ div32u16u::return#1 ] )
-  [60] (dword) div32u16u::return#0 ← (dword) div32u16u::return#1 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
+  [59] call div32u16u param-assignment [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
+  [60] (dword) div32u16u::return#2 ← (dword) div32u16u::return#0 [ div32u16u::return#2 ] ( main:2::sin16s_gen:5 [ div32u16u::return#2 ] )
   to:sin16s_gen::@3
 sin16s_gen::@3: scope:[sin16s_gen]  from sin16s_gen
-  [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#0 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] )
+  [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#2 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] )
   to:sin16s_gen::@1
 sin16s_gen::@1: scope:[sin16s_gen]  from sin16s_gen::@3 sin16s_gen::@4
   [62] (word) sin16s_gen::i#2 ← phi( sin16s_gen::@3/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s_gen::@4/(word) sin16s_gen::i#1 ) [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 ] )
@@ -4835,171 +4764,166 @@ sin16s::@4: scope:[sin16s]  from sin16s
   [74] (dword) sin16s::x#1 ← (dword) sin16s::x#0 - (const dword) PI_u4f28#0 [ sin16s::x#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#1 ] )
   to:sin16s::@1
 sin16s::@1: scope:[sin16s]  from sin16s sin16s::@4
-  [75] (byte) sin16s::isUpper#10 ← phi( sin16s/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@4/(byte/signed byte/word/signed word/dword/signed dword) 1 ) [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] )
-  [75] (dword) sin16s::x#4 ← phi( sin16s/(dword) sin16s::x#0 sin16s::@4/(dword) sin16s::x#1 ) [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] )
-  [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] )
+  [75] (byte) sin16s::isUpper#2 ← phi( sin16s/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@4/(byte/signed byte/word/signed word/dword/signed dword) 1 ) [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] )
+  [75] (dword) sin16s::x#4 ← phi( sin16s/(dword) sin16s::x#0 sin16s::@4/(dword) sin16s::x#1 ) [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] )
+  [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] )
   to:sin16s::@5
 sin16s::@5: scope:[sin16s]  from sin16s::@1
-  [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#10 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#2 ] )
+  [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#2 ] )
   to:sin16s::@2
 sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
-  [78] (dword) sin16s::x#6 ← phi( sin16s::@1/(dword) sin16s::x#4 sin16s::@5/(dword) sin16s::x#2 ) [ sin16s::isUpper#10 sin16s::x#6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#6 ] )
-  [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#10 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::$6 ] )
-  [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#10 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 ] )
-  [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] )
-  [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] )
-  [83] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] )
+  [78] (dword) sin16s::x#6 ← phi( sin16s::@1/(dword) sin16s::x#4 sin16s::@5/(dword) sin16s::x#2 ) [ sin16s::isUpper#2 sin16s::x#6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#6 ] )
+  [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#2 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::$6 ] )
+  [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 ] )
+  [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] )
+  [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] )
+  [83] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] )
   to:sin16s::@8
 sin16s::@8: scope:[sin16s]  from sin16s::@2
-  [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] )
-  [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] )
-  [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] )
-  [88] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] )
+  [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] )
+  [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] )
+  [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] )
+  [88] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] )
   to:sin16s::@9
 sin16s::@9: scope:[sin16s]  from sin16s::@8
-  [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] )
-  [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] )
-  [92] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] )
-  [93] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] )
+  [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] )
+  [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] )
+  [92] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] )
+  [93] (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] )
   to:sin16s::@10
 sin16s::@10: scope:[sin16s]  from sin16s::@9
-  [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] )
-  [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] )
-  [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] )
-  [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] )
-  [98] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  [99] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] )
+  [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] )
+  [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] )
+  [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] )
+  [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] )
+  [98] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  [99] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] )
   to:sin16s::@11
 sin16s::@11: scope:[sin16s]  from sin16s::@10
-  [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] )
-  [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] )
-  [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] )
-  [103] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  [104] (word) mul_u16_sel::return#12 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] )
+  [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] )
+  [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] )
+  [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] )
+  [103] call mul_u16_sel param-assignment [ sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  [104] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] )
   to:sin16s::@12
 sin16s::@12: scope:[sin16s]  from sin16s::@11
-  [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] )
-  [106] (word) mul_u16_sel::v1#5 ← (word) sin16s::x5#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] )
-  [107] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  [108] (word) mul_u16_sel::return#13 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] )
-  to:sin16s::@13
-sin16s::@13: scope:[sin16s]  from sin16s::@12
-  [109] (word) sin16s::x5_128#0 ← (word) mul_u16_sel::return#13 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] )
-  [110] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#10 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#1 ] )
-  [111] if((byte) sin16s::isUpper#10==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@16 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] )
+  [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] )
+  [106] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] )
+  [107] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] )
+  [108] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] )
   to:sin16s::@6
-sin16s::@6: scope:[sin16s]  from sin16s::@13
-  [112] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] )
+sin16s::@6: scope:[sin16s]  from sin16s::@12
+  [109] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] )
   to:sin16s::@3
-sin16s::@3: scope:[sin16s]  from sin16s::@16 sin16s::@6
-  [113] (signed word) sin16s::return#1 ← phi( sin16s::@16/(signed word~) sin16s::return#5 sin16s::@6/(signed word) sin16s::sinx#1 ) [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
+sin16s::@3: scope:[sin16s]  from sin16s::@15 sin16s::@6
+  [110] (signed word) sin16s::return#1 ← phi( sin16s::@15/(signed word~) sin16s::return#5 sin16s::@6/(signed word) sin16s::sinx#1 ) [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
   to:sin16s::@return
 sin16s::@return: scope:[sin16s]  from sin16s::@3
-  [114] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
+  [111] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
   to:@return
-sin16s::@16: scope:[sin16s]  from sin16s::@13
-  [115] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] )
+sin16s::@15: scope:[sin16s]  from sin16s::@12
+  [112] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] )
   to:sin16s::@3
-mul_u16_sel: scope:[mul_u16_sel]  from sin16s::@10 sin16s::@11 sin16s::@12 sin16s::@2 sin16s::@8 sin16s::@9
-  [116] (byte) mul_u16_sel::select#6 ← phi( sin16s::@10/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@11/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@12/(byte/signed byte/word/signed word/dword/signed dword) 3 sin16s::@2/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@8/(byte/signed byte/word/signed word/dword/signed dword) 1 sin16s::@9/(byte/signed byte/word/signed word/dword/signed dword) 1 ) [ mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] )
-  [116] (word) mul_u16_sel::v2#6 ← phi( sin16s::@10/(word) mul_u16_sel::v2#3 sin16s::@11/(word) mul_u16_sel::v2#4 sin16s::@12/(dword/signed dword) 65536/(byte/word/signed word/dword/signed dword) 128 sin16s::@2/(word) mul_u16_sel::v2#0 sin16s::@8/(word) mul_u16_sel::v2#1 sin16s::@9/(dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 ) [ mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] )
-  [116] (word) mul_u16_sel::v1#6 ← phi( sin16s::@10/(word) mul_u16_sel::v1#3 sin16s::@11/(word) mul_u16_sel::v1#4 sin16s::@12/(word) mul_u16_sel::v1#5 sin16s::@2/(word) mul_u16_sel::v1#0 sin16s::@8/(word) mul_u16_sel::v1#1 sin16s::@9/(word) mul_u16_sel::v1#2 ) [ mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#6 mul_u16_sel::v2#6 mul_u16_sel::select#6 ] )
-  [117] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#6 [ mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] )
-  [118] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#6 [ mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] )
-  [119] call mul16u param-assignment [ mul_u16_sel::select#6 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
-  [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#6 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] )
+mul_u16_sel: scope:[mul_u16_sel]  from sin16s::@10 sin16s::@11 sin16s::@2 sin16s::@8 sin16s::@9
+  [113] (byte) mul_u16_sel::select#5 ← phi( sin16s::@10/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@11/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@2/(byte/signed byte/word/signed word/dword/signed dword) 0 sin16s::@8/(byte/signed byte/word/signed word/dword/signed dword) 1 sin16s::@9/(byte/signed byte/word/signed word/dword/signed dword) 1 ) [ mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] )
+  [113] (word) mul_u16_sel::v2#5 ← phi( sin16s::@10/(word) mul_u16_sel::v2#3 sin16s::@11/(word) mul_u16_sel::v2#4 sin16s::@2/(word) mul_u16_sel::v2#0 sin16s::@8/(word) mul_u16_sel::v2#1 sin16s::@9/(dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 ) [ mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] )
+  [113] (word) mul_u16_sel::v1#5 ← phi( sin16s::@10/(word) mul_u16_sel::v1#3 sin16s::@11/(word) mul_u16_sel::v1#4 sin16s::@2/(word) mul_u16_sel::v1#0 sin16s::@8/(word) mul_u16_sel::v1#1 sin16s::@9/(word) mul_u16_sel::v1#2 ) [ mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#5 mul_u16_sel::v2#5 mul_u16_sel::select#5 ] )
+  [114] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#5 [ mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] )
+  [115] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#5 [ mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] )
+  [116] call mul16u param-assignment [ mul_u16_sel::select#5 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
+  [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] )
   to:mul_u16_sel::@2
 mul_u16_sel::@2: scope:[mul_u16_sel]  from mul_u16_sel
-  [121] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#6 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] )
-  [122] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#6 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] )
-  [123] (word) mul_u16_sel::return#14 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] )
+  [118] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#5 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] )
+  [119] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#5 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::$1 ] )
+  [120] (word) mul_u16_sel::return#12 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] )
   to:mul_u16_sel::@return
 mul_u16_sel::@return: scope:[mul_u16_sel]  from mul_u16_sel::@2
-  [124] return  [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] )
+  [121] return  [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] )
   to:@return
 mul16u: scope:[mul16u]  from mul_u16_sel
-  [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] )
+  [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] )
   to:mul16u::@1
 mul16u::@1: scope:[mul16u]  from mul16u mul16u::@4
-  [126] (dword) mul16u::mb#2 ← phi( mul16u/(dword) mul16u::mb#0 mul16u::@4/(dword) mul16u::mb#1 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
-  [126] (dword) mul16u::res#2 ← phi( mul16u/(byte/signed byte/word/signed word/dword/signed dword) 0 mul16u::@4/(dword) mul16u::res#6 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
-  [126] (word) mul16u::a#2 ← phi( mul16u/(word) mul16u::a#1 mul16u::@4/(word) mul16u::a#0 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
-  [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [123] (dword) mul16u::mb#2 ← phi( mul16u/(dword) mul16u::mb#0 mul16u::@4/(dword) mul16u::mb#1 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [123] (dword) mul16u::res#2 ← phi( mul16u/(byte/signed byte/word/signed word/dword/signed dword) 0 mul16u::@4/(dword) mul16u::res#6 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [123] (word) mul16u::a#2 ← phi( mul16u/(word) mul16u::a#1 mul16u::@4/(word) mul16u::a#0 ) [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
   to:mul16u::@return
 mul16u::@return: scope:[mul16u]  from mul16u::@1
-  [128] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
+  [125] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
   to:@return
 mul16u::@2: scope:[mul16u]  from mul16u::@1
-  [129] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] )
-  [130] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
+  [126] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] )
+  [127] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] )
   to:mul16u::@7
 mul16u::@7: scope:[mul16u]  from mul16u::@2
-  [131] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] )
+  [128] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] )
   to:mul16u::@4
 mul16u::@4: scope:[mul16u]  from mul16u::@2 mul16u::@7
-  [132] (dword) mul16u::res#6 ← phi( mul16u::@2/(dword) mul16u::res#2 mul16u::@7/(dword) mul16u::res#1 ) [ mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] )
-  [133] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] )
-  [134] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] )
+  [129] (dword) mul16u::res#6 ← phi( mul16u::@2/(dword) mul16u::res#2 mul16u::@7/(dword) mul16u::res#1 ) [ mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#6 ] )
+  [130] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] )
+  [131] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] )
   to:mul16u::@1
 div32u16u: scope:[div32u16u]  from sin16s_gen
-  [135] phi() [ ] ( main:2::sin16s_gen:5::div32u16u:59 [ ] )
-  [136] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
-  [137] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] )
+  [132] phi() [ ] ( main:2::sin16s_gen:5::div32u16u:59 [ ] )
+  [133] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
+  [134] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] )
   to:div32u16u::@2
 div32u16u::@2: scope:[div32u16u]  from div32u16u
-  [138] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] )
-  [139] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] )
-  [140] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
-  [141] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] )
+  [135] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] )
+  [136] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] )
+  [137] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
+  [138] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] )
   to:div32u16u::@3
 div32u16u::@3: scope:[div32u16u]  from div32u16u::@2
-  [142] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] )
-  [143] (dword) div32u16u::return#1 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] )
+  [139] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] )
+  [140] (dword) div32u16u::return#0 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] )
   to:div32u16u::@return
 div32u16u::@return: scope:[div32u16u]  from div32u16u::@3
-  [144] return  [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] )
+  [141] return  [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] )
   to:@return
 divr16u: scope:[divr16u]  from div32u16u div32u16u::@2
-  [145] (word) divr16u::divisor#6 ← phi( div32u16u/(const word) main::wavelength#0 div32u16u::@2/(const word) main::wavelength#0 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
-  [145] (word) divr16u::dividend#5 ← phi( div32u16u/>(const dword) PI2_u4f28#0 div32u16u::@2/<(const dword) PI2_u4f28#0 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
-  [145] (word) divr16u::rem#10 ← phi( div32u16u/(byte/signed byte/word/signed word/dword/signed dword) 0 div32u16u::@2/(word) divr16u::rem#4 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
+  [142] (word) divr16u::divisor#6 ← phi( div32u16u/(const word) main::wavelength#0 div32u16u::@2/(const word) main::wavelength#0 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
+  [142] (word) divr16u::dividend#5 ← phi( div32u16u/>(const dword) PI2_u4f28#0 div32u16u::@2/<(const dword) PI2_u4f28#0 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
+  [142] (word) divr16u::rem#10 ← phi( div32u16u/(byte/signed byte/word/signed word/dword/signed dword) 0 div32u16u::@2/(word) divr16u::rem#4 ) [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::rem#10 divr16u::dividend#5 divr16u::divisor#6 ] )
   to:divr16u::@1
 divr16u::@1: scope:[divr16u]  from divr16u divr16u::@3
-  [146] (byte) divr16u::i#2 ← phi( divr16u/(byte/signed byte/word/signed word/dword/signed dword) 0 divr16u::@3/(byte) divr16u::i#1 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
-  [146] (word) divr16u::quotient#3 ← phi( divr16u/(byte/signed byte/word/signed word/dword/signed dword) 0 divr16u::@3/(word) divr16u::return#0 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
-  [146] (word) divr16u::dividend#3 ← phi( divr16u/(word) divr16u::dividend#5 divr16u::@3/(word) divr16u::dividend#0 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
-  [146] (word) divr16u::rem#5 ← phi( divr16u/(word) divr16u::rem#10 divr16u::@3/(word) divr16u::rem#11 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
-  [147] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] )
-  [148] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] )
-  [149] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] )
-  [150] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] )
+  [143] (byte) divr16u::i#2 ← phi( divr16u/(byte/signed byte/word/signed word/dword/signed dword) 0 divr16u::@3/(byte) divr16u::i#1 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
+  [143] (word) divr16u::quotient#3 ← phi( divr16u/(byte/signed byte/word/signed word/dword/signed dword) 0 divr16u::@3/(word) divr16u::return#0 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
+  [143] (word) divr16u::dividend#3 ← phi( divr16u/(word) divr16u::dividend#5 divr16u::@3/(word) divr16u::dividend#0 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
+  [143] (word) divr16u::rem#5 ← phi( divr16u/(word) divr16u::rem#10 divr16u::@3/(word) divr16u::rem#11 ) [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::rem#5 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 ] )
+  [144] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] )
+  [145] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] )
+  [146] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] )
+  [147] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] )
   to:divr16u::@4
 divr16u::@4: scope:[divr16u]  from divr16u::@1
-  [151] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] )
+  [148] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] )
   to:divr16u::@2
 divr16u::@2: scope:[divr16u]  from divr16u::@1 divr16u::@4
-  [152] (word) divr16u::rem#6 ← phi( divr16u::@1/(word) divr16u::rem#0 divr16u::@4/(word) divr16u::rem#1 ) [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] )
-  [153] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] )
-  [154] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] )
-  [155] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] )
+  [149] (word) divr16u::rem#6 ← phi( divr16u::@1/(word) divr16u::rem#0 divr16u::@4/(word) divr16u::rem#1 ) [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#6 ] )
+  [150] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] )
+  [151] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] )
+  [152] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] )
   to:divr16u::@5
 divr16u::@5: scope:[divr16u]  from divr16u::@2
-  [156] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] )
-  [157] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] )
+  [153] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] )
+  [154] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] )
   to:divr16u::@3
 divr16u::@3: scope:[divr16u]  from divr16u::@2 divr16u::@5
-  [158] (word) divr16u::return#0 ← phi( divr16u::@2/(word) divr16u::quotient#1 divr16u::@5/(word) divr16u::quotient#2 ) [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] )
-  [158] (word) divr16u::rem#11 ← phi( divr16u::@2/(word) divr16u::rem#6 divr16u::@5/(word) divr16u::rem#2 ) [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] )
-  [159] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] )
-  [160] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] )
+  [155] (word) divr16u::return#0 ← phi( divr16u::@2/(word) divr16u::quotient#1 divr16u::@5/(word) divr16u::quotient#2 ) [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] )
+  [155] (word) divr16u::rem#11 ← phi( divr16u::@2/(word) divr16u::rem#6 divr16u::@5/(word) divr16u::rem#2 ) [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::i#2 divr16u::rem#11 divr16u::dividend#0 ] )
+  [156] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] )
+  [157] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] )
   to:divr16u::@6
 divr16u::@6: scope:[divr16u]  from divr16u::@3
-  [161] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  [158] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
   to:divr16u::@return
 divr16u::@return: scope:[divr16u]  from divr16u::@6
-  [162] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  [159] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
   to:@return
 
 DOMINATORS
@@ -5049,11 +4973,10 @@ sin16s::@9 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s
 sin16s::@10 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@10 sin16s::@2 
 sin16s::@11 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@11 sin16s::@10 sin16s::@2 
 sin16s::@12 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@2 
-sin16s::@13 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@13 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@2 
-sin16s::@6 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@13 sin16s::@6 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@2 
-sin16s::@3 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@13 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@3 sin16s::@2 
-sin16s::@return dominated by  @26 main sin16s @begin sin16s::@return sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@13 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@3 sin16s::@2 
-sin16s::@16 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@16 sin16s::@8 sin16s::@13 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@2 
+sin16s::@6 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@6 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@2 
+sin16s::@3 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@3 sin16s::@2 
+sin16s::@return dominated by  @26 main sin16s @begin sin16s::@return sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@3 sin16s::@2 
+sin16s::@15 dominated by  @26 main sin16s @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@9 sin16s::@8 sin16s::@15 sin16s::@12 sin16s::@11 sin16s::@10 sin16s::@2 
 mul_u16_sel dominated by  @26 main sin16s mul_u16_sel @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@2 
 mul_u16_sel::@2 dominated by  @26 main sin16s mul_u16_sel @begin sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@2 mul_u16_sel::@2 
 mul_u16_sel::@return dominated by  @26 main sin16s mul_u16_sel @begin mul_u16_sel::@return sin16s_gen sin16s_gen::@3 sin16s::@1 sin16s_gen::@1 sin16s::@2 mul_u16_sel::@2 
@@ -5149,8 +5072,8 @@ VARIABLE REGISTER WEIGHTS
 (word) div32u16u::quotient_lo
 (word) div32u16u::quotient_lo#0 4.0
 (dword) div32u16u::return
-(dword) div32u16u::return#0 4.0
-(dword) div32u16u::return#1 1.3333333333333333
+(dword) div32u16u::return#0 1.3333333333333333
+(dword) div32u16u::return#2 4.0
 (word()) divr16u((word) divr16u::dividend , (word) divr16u::divisor , (word) divr16u::rem)
 (byte~) divr16u::$1 22.0
 (byte~) divr16u::$2 22.0
@@ -5215,25 +5138,23 @@ VARIABLE REGISTER WEIGHTS
 (word) mul_u16_sel::return#1 4.0
 (word) mul_u16_sel::return#10 4.0
 (word) mul_u16_sel::return#11 4.0
-(word) mul_u16_sel::return#12 4.0
-(word) mul_u16_sel::return#13 4.0
-(word) mul_u16_sel::return#14 1.75
+(word) mul_u16_sel::return#12 1.714285714285714
+(word) mul_u16_sel::return#2 4.0
 (byte) mul_u16_sel::select
-(byte) mul_u16_sel::select#6 0.3333333333333333
+(byte) mul_u16_sel::select#5 0.3333333333333333
 (word) mul_u16_sel::v1
 (word) mul_u16_sel::v1#0 2.0
 (word) mul_u16_sel::v1#1 2.0
 (word) mul_u16_sel::v1#2 4.0
 (word) mul_u16_sel::v1#3 2.0
 (word) mul_u16_sel::v1#4 2.0
-(word) mul_u16_sel::v1#5 4.0
-(word) mul_u16_sel::v1#6 14.0
+(word) mul_u16_sel::v1#5 12.0
 (word) mul_u16_sel::v2
 (word) mul_u16_sel::v2#0 4.0
 (word) mul_u16_sel::v2#1 4.0
 (word) mul_u16_sel::v2#3 4.0
 (word) mul_u16_sel::v2#4 4.0
-(word) mul_u16_sel::v2#6 5.0
+(word) mul_u16_sel::v2#5 5.0
 (void()) print_byte((byte) print_byte::b)
 (byte~) print_byte::$0 4.0
 (byte~) print_byte::$2 4.0
@@ -5268,7 +5189,7 @@ VARIABLE REGISTER WEIGHTS
 (signed word()) sin16s((dword) sin16s::x)
 (dword~) sin16s::$6 4.0
 (byte) sin16s::isUpper
-(byte) sin16s::isUpper#10 0.05555555555555555
+(byte) sin16s::isUpper#2 0.06060606060606061
 (signed word) sin16s::return
 (signed word) sin16s::return#0 22.0
 (signed word) sin16s::return#1 5.0
@@ -5276,7 +5197,7 @@ VARIABLE REGISTER WEIGHTS
 (signed word) sin16s::sinx
 (signed word) sin16s::sinx#1 4.0
 (word) sin16s::usinx
-(word) sin16s::usinx#0 0.26666666666666666
+(word) sin16s::usinx#0 0.3333333333333333
 (word) sin16s::usinx#1 1.0
 (dword) sin16s::x
 (dword) sin16s::x#0 8.5
@@ -5324,12 +5245,12 @@ Initial phi equivalence classes
 [ sin16s_gen::x#2 sin16s_gen::x#1 ]
 [ sin16s_gen::sintab#2 sin16s_gen::sintab#1 ]
 [ sin16s_gen::i#2 sin16s_gen::i#1 ]
-[ sin16s::isUpper#10 ]
+[ sin16s::isUpper#2 ]
 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ]
 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ]
-[ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ]
-[ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ]
-[ mul_u16_sel::select#6 ]
+[ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ]
+[ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ]
+[ mul_u16_sel::select#5 ]
 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ]
 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ]
 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
@@ -5341,7 +5262,7 @@ Initial phi equivalence classes
 Added variable main::sw#0 to zero page equivalence class [ main::sw#0 ]
 Added variable print_byte::$0 to zero page equivalence class [ print_byte::$0 ]
 Added variable print_byte::$2 to zero page equivalence class [ print_byte::$2 ]
-Added variable div32u16u::return#0 to zero page equivalence class [ div32u16u::return#0 ]
+Added variable div32u16u::return#2 to zero page equivalence class [ div32u16u::return#2 ]
 Added variable sin16s_gen::step#0 to zero page equivalence class [ sin16s_gen::step#0 ]
 Added variable sin16s::return#0 to zero page equivalence class [ sin16s::return#0 ]
 Added variable sin16s_gen::$1 to zero page equivalence class [ sin16s_gen::$1 ]
@@ -5351,27 +5272,26 @@ Added variable mul_u16_sel::return#0 to zero page equivalence class [ mul_u16_se
 Added variable sin16s::x2#0 to zero page equivalence class [ sin16s::x2#0 ]
 Added variable mul_u16_sel::return#1 to zero page equivalence class [ mul_u16_sel::return#1 ]
 Added variable sin16s::x3#0 to zero page equivalence class [ sin16s::x3#0 ]
-Added variable mul_u16_sel::return#10 to zero page equivalence class [ mul_u16_sel::return#10 ]
+Added variable mul_u16_sel::return#2 to zero page equivalence class [ mul_u16_sel::return#2 ]
 Added variable sin16s::x3_6#0 to zero page equivalence class [ sin16s::x3_6#0 ]
 Added variable sin16s::usinx#0 to zero page equivalence class [ sin16s::usinx#0 ]
-Added variable mul_u16_sel::return#11 to zero page equivalence class [ mul_u16_sel::return#11 ]
+Added variable mul_u16_sel::return#10 to zero page equivalence class [ mul_u16_sel::return#10 ]
 Added variable sin16s::x4#0 to zero page equivalence class [ sin16s::x4#0 ]
-Added variable mul_u16_sel::return#12 to zero page equivalence class [ mul_u16_sel::return#12 ]
+Added variable mul_u16_sel::return#11 to zero page equivalence class [ mul_u16_sel::return#11 ]
 Added variable sin16s::x5#0 to zero page equivalence class [ sin16s::x5#0 ]
-Added variable mul_u16_sel::return#13 to zero page equivalence class [ mul_u16_sel::return#13 ]
 Added variable sin16s::x5_128#0 to zero page equivalence class [ sin16s::x5_128#0 ]
 Added variable sin16s::usinx#1 to zero page equivalence class [ sin16s::usinx#1 ]
 Added variable mul16u::b#0 to zero page equivalence class [ mul16u::b#0 ]
 Added variable mul16u::return#2 to zero page equivalence class [ mul16u::return#2 ]
 Added variable mul_u16_sel::$0 to zero page equivalence class [ mul_u16_sel::$0 ]
 Added variable mul_u16_sel::$1 to zero page equivalence class [ mul_u16_sel::$1 ]
-Added variable mul_u16_sel::return#14 to zero page equivalence class [ mul_u16_sel::return#14 ]
+Added variable mul_u16_sel::return#12 to zero page equivalence class [ mul_u16_sel::return#12 ]
 Added variable mul16u::$1 to zero page equivalence class [ mul16u::$1 ]
 Added variable divr16u::return#2 to zero page equivalence class [ divr16u::return#2 ]
 Added variable div32u16u::quotient_hi#0 to zero page equivalence class [ div32u16u::quotient_hi#0 ]
 Added variable divr16u::return#3 to zero page equivalence class [ divr16u::return#3 ]
 Added variable div32u16u::quotient_lo#0 to zero page equivalence class [ div32u16u::quotient_lo#0 ]
-Added variable div32u16u::return#1 to zero page equivalence class [ div32u16u::return#1 ]
+Added variable div32u16u::return#0 to zero page equivalence class [ div32u16u::return#0 ]
 Added variable divr16u::$1 to zero page equivalence class [ divr16u::$1 ]
 Added variable divr16u::$2 to zero page equivalence class [ divr16u::$2 ]
 Added variable rem16u#1 to zero page equivalence class [ rem16u#1 ]
@@ -5386,12 +5306,12 @@ Complete equivalence classes
 [ sin16s_gen::x#2 sin16s_gen::x#1 ]
 [ sin16s_gen::sintab#2 sin16s_gen::sintab#1 ]
 [ sin16s_gen::i#2 sin16s_gen::i#1 ]
-[ sin16s::isUpper#10 ]
+[ sin16s::isUpper#2 ]
 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ]
 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ]
-[ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ]
-[ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ]
-[ mul_u16_sel::select#6 ]
+[ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ]
+[ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ]
+[ mul_u16_sel::select#5 ]
 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ]
 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ]
 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
@@ -5403,7 +5323,7 @@ Complete equivalence classes
 [ main::sw#0 ]
 [ print_byte::$0 ]
 [ print_byte::$2 ]
-[ div32u16u::return#0 ]
+[ div32u16u::return#2 ]
 [ sin16s_gen::step#0 ]
 [ sin16s::return#0 ]
 [ sin16s_gen::$1 ]
@@ -5413,27 +5333,26 @@ Complete equivalence classes
 [ sin16s::x2#0 ]
 [ mul_u16_sel::return#1 ]
 [ sin16s::x3#0 ]
-[ mul_u16_sel::return#10 ]
+[ mul_u16_sel::return#2 ]
 [ sin16s::x3_6#0 ]
 [ sin16s::usinx#0 ]
-[ mul_u16_sel::return#11 ]
+[ mul_u16_sel::return#10 ]
 [ sin16s::x4#0 ]
-[ mul_u16_sel::return#12 ]
+[ mul_u16_sel::return#11 ]
 [ sin16s::x5#0 ]
-[ mul_u16_sel::return#13 ]
 [ sin16s::x5_128#0 ]
 [ sin16s::usinx#1 ]
 [ mul16u::b#0 ]
 [ mul16u::return#2 ]
 [ mul_u16_sel::$0 ]
 [ mul_u16_sel::$1 ]
-[ mul_u16_sel::return#14 ]
+[ mul_u16_sel::return#12 ]
 [ mul16u::$1 ]
 [ divr16u::return#2 ]
 [ div32u16u::quotient_hi#0 ]
 [ divr16u::return#3 ]
 [ div32u16u::quotient_lo#0 ]
-[ div32u16u::return#1 ]
+[ div32u16u::return#0 ]
 [ divr16u::$1 ]
 [ divr16u::$2 ]
 [ rem16u#1 ]
@@ -5447,12 +5366,12 @@ Allocated zp ZP_WORD:12 [ print_cls::sc#2 print_cls::sc#1 ]
 Allocated zp ZP_DWORD:14 [ sin16s_gen::x#2 sin16s_gen::x#1 ]
 Allocated zp ZP_WORD:18 [ sin16s_gen::sintab#2 sin16s_gen::sintab#1 ]
 Allocated zp ZP_WORD:20 [ sin16s_gen::i#2 sin16s_gen::i#1 ]
-Allocated zp ZP_BYTE:22 [ sin16s::isUpper#10 ]
+Allocated zp ZP_BYTE:22 [ sin16s::isUpper#2 ]
 Allocated zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ]
 Allocated zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ]
-Allocated zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ]
-Allocated zp ZP_WORD:31 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ]
-Allocated zp ZP_BYTE:33 [ mul_u16_sel::select#6 ]
+Allocated zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ]
+Allocated zp ZP_WORD:31 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ]
+Allocated zp ZP_BYTE:33 [ mul_u16_sel::select#5 ]
 Allocated zp ZP_WORD:34 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ]
 Allocated zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ]
 Allocated zp ZP_DWORD:40 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
@@ -5464,7 +5383,7 @@ Allocated zp ZP_BYTE:52 [ divr16u::i#2 divr16u::i#1 ]
 Allocated zp ZP_WORD:53 [ main::sw#0 ]
 Allocated zp ZP_BYTE:55 [ print_byte::$0 ]
 Allocated zp ZP_BYTE:56 [ print_byte::$2 ]
-Allocated zp ZP_DWORD:57 [ div32u16u::return#0 ]
+Allocated zp ZP_DWORD:57 [ div32u16u::return#2 ]
 Allocated zp ZP_DWORD:61 [ sin16s_gen::step#0 ]
 Allocated zp ZP_WORD:65 [ sin16s::return#0 ]
 Allocated zp ZP_WORD:67 [ sin16s_gen::$1 ]
@@ -5474,30 +5393,29 @@ Allocated zp ZP_WORD:75 [ mul_u16_sel::return#0 ]
 Allocated zp ZP_WORD:77 [ sin16s::x2#0 ]
 Allocated zp ZP_WORD:79 [ mul_u16_sel::return#1 ]
 Allocated zp ZP_WORD:81 [ sin16s::x3#0 ]
-Allocated zp ZP_WORD:83 [ mul_u16_sel::return#10 ]
+Allocated zp ZP_WORD:83 [ mul_u16_sel::return#2 ]
 Allocated zp ZP_WORD:85 [ sin16s::x3_6#0 ]
 Allocated zp ZP_WORD:87 [ sin16s::usinx#0 ]
-Allocated zp ZP_WORD:89 [ mul_u16_sel::return#11 ]
+Allocated zp ZP_WORD:89 [ mul_u16_sel::return#10 ]
 Allocated zp ZP_WORD:91 [ sin16s::x4#0 ]
-Allocated zp ZP_WORD:93 [ mul_u16_sel::return#12 ]
+Allocated zp ZP_WORD:93 [ mul_u16_sel::return#11 ]
 Allocated zp ZP_WORD:95 [ sin16s::x5#0 ]
-Allocated zp ZP_WORD:97 [ mul_u16_sel::return#13 ]
-Allocated zp ZP_WORD:99 [ sin16s::x5_128#0 ]
-Allocated zp ZP_WORD:101 [ sin16s::usinx#1 ]
-Allocated zp ZP_WORD:103 [ mul16u::b#0 ]
-Allocated zp ZP_DWORD:105 [ mul16u::return#2 ]
-Allocated zp ZP_DWORD:109 [ mul_u16_sel::$0 ]
-Allocated zp ZP_DWORD:113 [ mul_u16_sel::$1 ]
-Allocated zp ZP_WORD:117 [ mul_u16_sel::return#14 ]
-Allocated zp ZP_BYTE:119 [ mul16u::$1 ]
-Allocated zp ZP_WORD:120 [ divr16u::return#2 ]
-Allocated zp ZP_WORD:122 [ div32u16u::quotient_hi#0 ]
-Allocated zp ZP_WORD:124 [ divr16u::return#3 ]
-Allocated zp ZP_WORD:126 [ div32u16u::quotient_lo#0 ]
-Allocated zp ZP_DWORD:128 [ div32u16u::return#1 ]
-Allocated zp ZP_BYTE:132 [ divr16u::$1 ]
-Allocated zp ZP_BYTE:133 [ divr16u::$2 ]
-Allocated zp ZP_WORD:134 [ rem16u#1 ]
+Allocated zp ZP_WORD:97 [ sin16s::x5_128#0 ]
+Allocated zp ZP_WORD:99 [ sin16s::usinx#1 ]
+Allocated zp ZP_WORD:101 [ mul16u::b#0 ]
+Allocated zp ZP_DWORD:103 [ mul16u::return#2 ]
+Allocated zp ZP_DWORD:107 [ mul_u16_sel::$0 ]
+Allocated zp ZP_DWORD:111 [ mul_u16_sel::$1 ]
+Allocated zp ZP_WORD:115 [ mul_u16_sel::return#12 ]
+Allocated zp ZP_BYTE:117 [ mul16u::$1 ]
+Allocated zp ZP_WORD:118 [ divr16u::return#2 ]
+Allocated zp ZP_WORD:120 [ div32u16u::quotient_hi#0 ]
+Allocated zp ZP_WORD:122 [ divr16u::return#3 ]
+Allocated zp ZP_WORD:124 [ div32u16u::quotient_lo#0 ]
+Allocated zp ZP_DWORD:126 [ div32u16u::return#0 ]
+Allocated zp ZP_BYTE:130 [ divr16u::$1 ]
+Allocated zp ZP_BYTE:131 [ divr16u::$2 ]
+Allocated zp ZP_WORD:132 [ rem16u#1 ]
 
 INITIAL ASM
 //SEG0 Basic Upstart
@@ -5509,7 +5427,7 @@ INITIAL ASM
   .const PI2_u4f28 = $6487ed51
   .const PI_u4f28 = $3243f6a9
   .const PI_HALF_u4f28 = $1921fb54
-  .label rem16u = $86
+  .label rem16u = $84
   .label char_cursor = $a
 //SEG2 @begin
 bbegin:
@@ -5875,30 +5793,30 @@ sin16s_gen: {
     .label sintab = $12
     .label x = $e
     .label i = $14
-  //SEG123 [59] call div32u16u param-assignment [ div32u16u::return#1 ] ( main:2::sin16s_gen:5 [ div32u16u::return#1 ] )
-  //SEG124 [135] phi from sin16s_gen to div32u16u [phi:sin16s_gen->div32u16u]
+  //SEG123 [59] call div32u16u param-assignment [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
+  //SEG124 [132] phi from sin16s_gen to div32u16u [phi:sin16s_gen->div32u16u]
   div32u16u_from_sin16s_gen:
     jsr div32u16u
-  //SEG125 [60] (dword) div32u16u::return#0 ← (dword) div32u16u::return#1 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] ) -- vduz1=vduz2 
-    lda div32u16u.return_1
-    sta div32u16u.return
-    lda div32u16u.return_1+1
-    sta div32u16u.return+1
-    lda div32u16u.return_1+2
-    sta div32u16u.return+2
-    lda div32u16u.return_1+3
-    sta div32u16u.return+3
+  //SEG125 [60] (dword) div32u16u::return#2 ← (dword) div32u16u::return#0 [ div32u16u::return#2 ] ( main:2::sin16s_gen:5 [ div32u16u::return#2 ] ) -- vduz1=vduz2 
+    lda div32u16u.return
+    sta div32u16u.return_2
+    lda div32u16u.return+1
+    sta div32u16u.return_2+1
+    lda div32u16u.return+2
+    sta div32u16u.return_2+2
+    lda div32u16u.return+3
+    sta div32u16u.return_2+3
     jmp b3
   //SEG126 sin16s_gen::@3
   b3:
-  //SEG127 [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#0 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] ) -- vduz1=vduz2 
-    lda div32u16u.return
+  //SEG127 [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#2 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] ) -- vduz1=vduz2 
+    lda div32u16u.return_2
     sta step
-    lda div32u16u.return+1
+    lda div32u16u.return_2+1
     sta step+1
-    lda div32u16u.return+2
+    lda div32u16u.return_2+2
     sta step+2
-    lda div32u16u.return+3
+    lda div32u16u.return_2+3
     sta step+3
   //SEG128 [62] phi from sin16s_gen::@3 to sin16s_gen::@1 [phi:sin16s_gen::@3->sin16s_gen::@1]
   b1_from_b3:
@@ -6013,8 +5931,8 @@ sin16s: {
     .label usinx = $57
     .label x4 = $5b
     .label x5 = $5f
-    .label x5_128 = $63
-    .label usinx_1 = $65
+    .label x5_128 = $61
+    .label usinx_1 = $63
     .label return_1 = $1b
     .label sinx = $1b
     .label isUpper = $16
@@ -6055,21 +5973,21 @@ sin16s: {
     sta x+3
   //SEG153 [75] phi from sin16s::@4 to sin16s::@1 [phi:sin16s::@4->sin16s::@1]
   b1_from_b4:
-  //SEG154 [75] phi (byte) sin16s::isUpper#10 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@4->sin16s::@1#0] -- vbuz1=vbuc1 
+  //SEG154 [75] phi (byte) sin16s::isUpper#2 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@4->sin16s::@1#0] -- vbuz1=vbuc1 
     lda #1
     sta isUpper
   //SEG155 [75] phi (dword) sin16s::x#4 = (dword) sin16s::x#1 [phi:sin16s::@4->sin16s::@1#1] -- register_copy 
     jmp b1
   //SEG156 [75] phi from sin16s to sin16s::@1 [phi:sin16s->sin16s::@1]
   b1_from_sin16s:
-  //SEG157 [75] phi (byte) sin16s::isUpper#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s->sin16s::@1#0] -- vbuz1=vbuc1 
+  //SEG157 [75] phi (byte) sin16s::isUpper#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s->sin16s::@1#0] -- vbuz1=vbuc1 
     lda #0
     sta isUpper
   //SEG158 [75] phi (dword) sin16s::x#4 = (dword) sin16s::x#0 [phi:sin16s->sin16s::@1#1] -- register_copy 
     jmp b1
   //SEG159 sin16s::@1
   b1:
-  //SEG160 [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] ) -- vduz1_lt_vduc1_then_la1 
+  //SEG160 [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] ) -- vduz1_lt_vduc1_then_la1 
     lda x+3
     cmp #>PI_HALF_u4f28>>$10
     bcc b2_from_b1
@@ -6089,7 +6007,7 @@ sin16s: {
     jmp b5
   //SEG161 sin16s::@5
   b5:
-  //SEG162 [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#10 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#2 ] ) -- vduz1=vduc1_minus_vduz1 
+  //SEG162 [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#2 ] ) -- vduz1=vduc1_minus_vduz1 
     lda #<PI_u4f28
     sec
     sbc x
@@ -6110,7 +6028,7 @@ sin16s: {
     jmp b2
   //SEG165 sin16s::@2
   b2:
-  //SEG166 [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#10 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::$6 ] ) -- vduz1=vduz2_rol_3 
+  //SEG166 [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#2 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::$6 ] ) -- vduz1=vduz2_rol_3 
     lda x
     sta _6
     lda x+1
@@ -6127,107 +6045,107 @@ sin16s: {
     rol _6+3
     dey
     bne !-
-  //SEG167 [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#10 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 ] ) -- vwuz1=_hi_vduz2 
+  //SEG167 [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 ] ) -- vwuz1=_hi_vduz2 
     lda _6+2
     sta x1
     lda _6+3
     sta x1+1
-  //SEG168 [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ) -- vwuz1=vwuz2 
+  //SEG168 [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v1
     lda x1+1
     sta mul_u16_sel.v1+1
-  //SEG169 [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) -- vwuz1=vwuz2 
+  //SEG169 [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG170 [83] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  //SEG171 [116] phi from sin16s::@2 to mul_u16_sel [phi:sin16s::@2->mul_u16_sel]
+  //SEG170 [83] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  //SEG171 [113] phi from sin16s::@2 to mul_u16_sel [phi:sin16s::@2->mul_u16_sel]
   mul_u16_sel_from_b2:
-  //SEG172 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@2->mul_u16_sel#0] -- vbuz1=vbuc1 
+  //SEG172 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@2->mul_u16_sel#0] -- vbuz1=vbuc1 
     lda #0
     sta mul_u16_sel.select
-  //SEG173 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#0 [phi:sin16s::@2->mul_u16_sel#1] -- register_copy 
-  //SEG174 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#0 [phi:sin16s::@2->mul_u16_sel#2] -- register_copy 
+  //SEG173 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#0 [phi:sin16s::@2->mul_u16_sel#1] -- register_copy 
+  //SEG174 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#0 [phi:sin16s::@2->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG175 [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_14
+  //SEG175 [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ) -- vwuz1=vwuz2 
+    lda mul_u16_sel.return_12
     sta mul_u16_sel.return
-    lda mul_u16_sel.return_14+1
+    lda mul_u16_sel.return_12+1
     sta mul_u16_sel.return+1
     jmp b8
   //SEG176 sin16s::@8
   b8:
-  //SEG177 [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ) -- vwuz1=vwuz2 
+  //SEG177 [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ) -- vwuz1=vwuz2 
     lda mul_u16_sel.return
     sta x2
     lda mul_u16_sel.return+1
     sta x2+1
-  //SEG178 [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ) -- vwuz1=vwuz2 
+  //SEG178 [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ) -- vwuz1=vwuz2 
     lda x2
     sta mul_u16_sel.v1
     lda x2+1
     sta mul_u16_sel.v1+1
-  //SEG179 [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) -- vwuz1=vwuz2 
+  //SEG179 [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG180 [88] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  //SEG181 [116] phi from sin16s::@8 to mul_u16_sel [phi:sin16s::@8->mul_u16_sel]
+  //SEG180 [88] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  //SEG181 [113] phi from sin16s::@8 to mul_u16_sel [phi:sin16s::@8->mul_u16_sel]
   mul_u16_sel_from_b8:
-  //SEG182 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@8->mul_u16_sel#0] -- vbuz1=vbuc1 
+  //SEG182 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@8->mul_u16_sel#0] -- vbuz1=vbuc1 
     lda #1
     sta mul_u16_sel.select
-  //SEG183 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#1 [phi:sin16s::@8->mul_u16_sel#1] -- register_copy 
-  //SEG184 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#1 [phi:sin16s::@8->mul_u16_sel#2] -- register_copy 
+  //SEG183 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#1 [phi:sin16s::@8->mul_u16_sel#1] -- register_copy 
+  //SEG184 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#1 [phi:sin16s::@8->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG185 [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_14
+  //SEG185 [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ) -- vwuz1=vwuz2 
+    lda mul_u16_sel.return_12
     sta mul_u16_sel.return_1
-    lda mul_u16_sel.return_14+1
+    lda mul_u16_sel.return_12+1
     sta mul_u16_sel.return_1+1
     jmp b9
   //SEG186 sin16s::@9
   b9:
-  //SEG187 [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ) -- vwuz1=vwuz2 
+  //SEG187 [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ) -- vwuz1=vwuz2 
     lda mul_u16_sel.return_1
     sta x3
     lda mul_u16_sel.return_1+1
     sta x3+1
-  //SEG188 [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ) -- vwuz1=vwuz2 
+  //SEG188 [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ) -- vwuz1=vwuz2 
     lda x3
     sta mul_u16_sel.v1
     lda x3+1
     sta mul_u16_sel.v1+1
-  //SEG189 [92] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] )
-  //SEG190 [116] phi from sin16s::@9 to mul_u16_sel [phi:sin16s::@9->mul_u16_sel]
+  //SEG189 [92] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] )
+  //SEG190 [113] phi from sin16s::@9 to mul_u16_sel [phi:sin16s::@9->mul_u16_sel]
   mul_u16_sel_from_b9:
-  //SEG191 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@9->mul_u16_sel#0] -- vbuz1=vbuc1 
+  //SEG191 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@9->mul_u16_sel#0] -- vbuz1=vbuc1 
     lda #1
     sta mul_u16_sel.select
-  //SEG192 [116] phi (word) mul_u16_sel::v2#6 = (dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 [phi:sin16s::@9->mul_u16_sel#1] -- vwuz1=vwuc1 
+  //SEG192 [113] phi (word) mul_u16_sel::v2#5 = (dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 [phi:sin16s::@9->mul_u16_sel#1] -- vwuz1=vwuc1 
     lda #<$10000/6
     sta mul_u16_sel.v2
     lda #>$10000/6
     sta mul_u16_sel.v2+1
-  //SEG193 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#2 [phi:sin16s::@9->mul_u16_sel#2] -- register_copy 
+  //SEG193 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#2 [phi:sin16s::@9->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG194 [93] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_14
-    sta mul_u16_sel.return_10
-    lda mul_u16_sel.return_14+1
-    sta mul_u16_sel.return_10+1
+  //SEG194 [93] (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ) -- vwuz1=vwuz2 
+    lda mul_u16_sel.return_12
+    sta mul_u16_sel.return_2
+    lda mul_u16_sel.return_12+1
+    sta mul_u16_sel.return_2+1
     jmp b10
   //SEG195 sin16s::@10
   b10:
-  //SEG196 [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_10
+  //SEG196 [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ) -- vwuz1=vwuz2 
+    lda mul_u16_sel.return_2
     sta x3_6
-    lda mul_u16_sel.return_10+1
+    lda mul_u16_sel.return_2+1
     sta x3_6+1
-  //SEG197 [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) -- vwuz1=vwuz2_minus_vwuz3 
+  //SEG197 [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) -- vwuz1=vwuz2_minus_vwuz3 
     lda x1
     sec
     sbc x3_6
@@ -6235,102 +6153,82 @@ sin16s: {
     lda x1+1
     sbc x3_6+1
     sta usinx+1
-  //SEG198 [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ) -- vwuz1=vwuz2 
+  //SEG198 [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ) -- vwuz1=vwuz2 
     lda x3
     sta mul_u16_sel.v1
     lda x3+1
     sta mul_u16_sel.v1+1
-  //SEG199 [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) -- vwuz1=vwuz2 
+  //SEG199 [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG200 [98] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG201 [116] phi from sin16s::@10 to mul_u16_sel [phi:sin16s::@10->mul_u16_sel]
+  //SEG200 [98] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  //SEG201 [113] phi from sin16s::@10 to mul_u16_sel [phi:sin16s::@10->mul_u16_sel]
   mul_u16_sel_from_b10:
-  //SEG202 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@10->mul_u16_sel#0] -- vbuz1=vbuc1 
+  //SEG202 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@10->mul_u16_sel#0] -- vbuz1=vbuc1 
     lda #0
     sta mul_u16_sel.select
-  //SEG203 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#3 [phi:sin16s::@10->mul_u16_sel#1] -- register_copy 
-  //SEG204 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#3 [phi:sin16s::@10->mul_u16_sel#2] -- register_copy 
+  //SEG203 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#3 [phi:sin16s::@10->mul_u16_sel#1] -- register_copy 
+  //SEG204 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#3 [phi:sin16s::@10->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG205 [99] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_14
-    sta mul_u16_sel.return_11
-    lda mul_u16_sel.return_14+1
-    sta mul_u16_sel.return_11+1
+  //SEG205 [99] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ) -- vwuz1=vwuz2 
+    lda mul_u16_sel.return_12
+    sta mul_u16_sel.return_10
+    lda mul_u16_sel.return_12+1
+    sta mul_u16_sel.return_10+1
     jmp b11
   //SEG206 sin16s::@11
   b11:
-  //SEG207 [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_11
+  //SEG207 [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ) -- vwuz1=vwuz2 
+    lda mul_u16_sel.return_10
     sta x4
-    lda mul_u16_sel.return_11+1
+    lda mul_u16_sel.return_10+1
     sta x4+1
-  //SEG208 [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ) -- vwuz1=vwuz2 
+  //SEG208 [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ) -- vwuz1=vwuz2 
     lda x4
     sta mul_u16_sel.v1
     lda x4+1
     sta mul_u16_sel.v1+1
-  //SEG209 [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) -- vwuz1=vwuz2 
+  //SEG209 [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG210 [103] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG211 [116] phi from sin16s::@11 to mul_u16_sel [phi:sin16s::@11->mul_u16_sel]
+  //SEG210 [103] call mul_u16_sel param-assignment [ sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  //SEG211 [113] phi from sin16s::@11 to mul_u16_sel [phi:sin16s::@11->mul_u16_sel]
   mul_u16_sel_from_b11:
-  //SEG212 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@11->mul_u16_sel#0] -- vbuz1=vbuc1 
+  //SEG212 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@11->mul_u16_sel#0] -- vbuz1=vbuc1 
     lda #0
     sta mul_u16_sel.select
-  //SEG213 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#4 [phi:sin16s::@11->mul_u16_sel#1] -- register_copy 
-  //SEG214 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#4 [phi:sin16s::@11->mul_u16_sel#2] -- register_copy 
+  //SEG213 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#4 [phi:sin16s::@11->mul_u16_sel#1] -- register_copy 
+  //SEG214 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#4 [phi:sin16s::@11->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG215 [104] (word) mul_u16_sel::return#12 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_14
-    sta mul_u16_sel.return_12
-    lda mul_u16_sel.return_14+1
-    sta mul_u16_sel.return_12+1
+  //SEG215 [104] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ) -- vwuz1=vwuz2 
+    lda mul_u16_sel.return_12
+    sta mul_u16_sel.return_11
+    lda mul_u16_sel.return_12+1
+    sta mul_u16_sel.return_11+1
     jmp b12
   //SEG216 sin16s::@12
   b12:
-  //SEG217 [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_12
+  //SEG217 [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ) -- vwuz1=vwuz2 
+    lda mul_u16_sel.return_11
     sta x5
-    lda mul_u16_sel.return_12+1
+    lda mul_u16_sel.return_11+1
     sta x5+1
-  //SEG218 [106] (word) mul_u16_sel::v1#5 ← (word) sin16s::x5#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ) -- vwuz1=vwuz2 
-    lda x5
-    sta mul_u16_sel.v1
+  //SEG218 [106] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) -- vwuz1=vwuz2_ror_4 
     lda x5+1
-    sta mul_u16_sel.v1+1
-  //SEG219 [107] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG220 [116] phi from sin16s::@12 to mul_u16_sel [phi:sin16s::@12->mul_u16_sel]
-  mul_u16_sel_from_b12:
-  //SEG221 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 3 [phi:sin16s::@12->mul_u16_sel#0] -- vbuz1=vbuc1 
-    lda #3
-    sta mul_u16_sel.select
-  //SEG222 [116] phi (word) mul_u16_sel::v2#6 = (dword/signed dword) 65536/(byte/word/signed word/dword/signed dword) 128 [phi:sin16s::@12->mul_u16_sel#1] -- vwuz1=vwuc1 
-    lda #<$10000/$80
-    sta mul_u16_sel.v2
-    lda #>$10000/$80
-    sta mul_u16_sel.v2+1
-  //SEG223 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#5 [phi:sin16s::@12->mul_u16_sel#2] -- register_copy 
-    jsr mul_u16_sel
-  //SEG224 [108] (word) mul_u16_sel::return#13 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_14
-    sta mul_u16_sel.return_13
-    lda mul_u16_sel.return_14+1
-    sta mul_u16_sel.return_13+1
-    jmp b13
-  //SEG225 sin16s::@13
-  b13:
-  //SEG226 [109] (word) sin16s::x5_128#0 ← (word) mul_u16_sel::return#13 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return_13
-    sta x5_128
-    lda mul_u16_sel.return_13+1
     sta x5_128+1
-  //SEG227 [110] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#10 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#1 ] ) -- vwuz1=vwuz2_plus_vwuz3 
+    lda x5
+    sta x5_128
+    ldy #4
+  !:
+    lsr x5_128+1
+    ror x5_128
+    dey
+    bne !-
+  //SEG219 [107] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) -- vwuz1=vwuz2_plus_vwuz3 
     lda usinx_1
     clc
     adc usinx
@@ -6338,13 +6236,13 @@ sin16s: {
     lda usinx_1+1
     adc usinx+1
     sta x5_128+1
-  //SEG228 [111] if((byte) sin16s::isUpper#10==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@16 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) -- vbuz1_eq_0_then_la1 
+  //SEG220 [108] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) -- vbuz1_eq_0_then_la1 
     lda isUpper
-    beq b16
+    beq b15
     jmp b6
-  //SEG229 sin16s::@6
+  //SEG221 sin16s::@6
   b6:
-  //SEG230 [112] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) -- vwsz1=_neg_vwsz2 
+  //SEG222 [109] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) -- vwsz1=_neg_vwsz2 
     sec
     lda usinx_1
     eor #$ff
@@ -6354,54 +6252,53 @@ sin16s: {
     eor #$ff
     adc #0
     sta sinx+1
-  //SEG231 [113] phi from sin16s::@16 sin16s::@6 to sin16s::@3 [phi:sin16s::@16/sin16s::@6->sin16s::@3]
-  b3_from_b16:
+  //SEG223 [110] phi from sin16s::@15 sin16s::@6 to sin16s::@3 [phi:sin16s::@15/sin16s::@6->sin16s::@3]
+  b3_from_b15:
   b3_from_b6:
-  //SEG232 [113] phi (signed word) sin16s::return#1 = (signed word~) sin16s::return#5 [phi:sin16s::@16/sin16s::@6->sin16s::@3#0] -- register_copy 
+  //SEG224 [110] phi (signed word) sin16s::return#1 = (signed word~) sin16s::return#5 [phi:sin16s::@15/sin16s::@6->sin16s::@3#0] -- register_copy 
     jmp b3
-  //SEG233 sin16s::@3
+  //SEG225 sin16s::@3
   b3:
     jmp breturn
-  //SEG234 sin16s::@return
+  //SEG226 sin16s::@return
   breturn:
-  //SEG235 [114] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
+  //SEG227 [111] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
     rts
-  //SEG236 sin16s::@16
-  b16:
-  //SEG237 [115] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) -- vwsz1=vwsz2 
+  //SEG228 sin16s::@15
+  b15:
+  //SEG229 [112] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) -- vwsz1=vwsz2 
     lda usinx_1
     sta return_5
     lda usinx_1+1
     sta return_5+1
-    jmp b3_from_b16
+    jmp b3_from_b15
 }
-//SEG238 mul_u16_sel
+//SEG230 mul_u16_sel
 mul_u16_sel: {
-    .label _0 = $6d
-    .label _1 = $71
+    .label _0 = $6b
+    .label _1 = $6f
     .label v1 = $1d
     .label v2 = $1f
     .label return = $4b
     .label return_1 = $4f
-    .label return_10 = $53
-    .label return_11 = $59
-    .label return_12 = $5d
-    .label return_13 = $61
+    .label return_2 = $53
+    .label return_10 = $59
+    .label return_11 = $5d
     .label select = $21
-    .label return_14 = $75
-  //SEG239 [117] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#6 [ mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ) -- vwuz1=vwuz2 
+    .label return_12 = $73
+  //SEG231 [114] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#5 [ mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ) -- vwuz1=vwuz2 
     lda v1
     sta mul16u.a
     lda v1+1
     sta mul16u.a+1
-  //SEG240 [118] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#6 [ mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ) -- vwuz1=vwuz2 
+  //SEG232 [115] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#5 [ mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ) -- vwuz1=vwuz2 
     lda v2
     sta mul16u.b
     lda v2+1
     sta mul16u.b+1
-  //SEG241 [119] call mul16u param-assignment [ mul_u16_sel::select#6 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
+  //SEG233 [116] call mul16u param-assignment [ mul_u16_sel::select#5 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
     jsr mul16u
-  //SEG242 [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#6 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] ) -- vduz1=vduz2 
+  //SEG234 [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] ) -- vduz1=vduz2 
     lda mul16u.res
     sta mul16u.return
     lda mul16u.res+1
@@ -6411,9 +6308,9 @@ mul_u16_sel: {
     lda mul16u.res+3
     sta mul16u.return+3
     jmp b2
-  //SEG243 mul_u16_sel::@2
+  //SEG235 mul_u16_sel::@2
   b2:
-  //SEG244 [121] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#6 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] ) -- vduz1=vduz2 
+  //SEG236 [118] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#5 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] ) -- vduz1=vduz2 
     lda mul16u.return
     sta _0
     lda mul16u.return+1
@@ -6422,7 +6319,7 @@ mul_u16_sel: {
     sta _0+2
     lda mul16u.return+3
     sta _0+3
-  //SEG245 [122] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#6 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] ) -- vduz1=vduz2_rol_vbuz3 
+  //SEG237 [119] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#5 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::$1 ] ) -- vduz1=vduz2_rol_vbuz3 
     lda _0
     sta _1
     lda _0+1
@@ -6441,26 +6338,26 @@ mul_u16_sel: {
     dex
     bne !-
   !e:
-  //SEG246 [123] (word) mul_u16_sel::return#14 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] ) -- vwuz1=_hi_vduz2 
+  //SEG238 [120] (word) mul_u16_sel::return#12 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] ) -- vwuz1=_hi_vduz2 
     lda _1+2
-    sta return_14
+    sta return_12
     lda _1+3
-    sta return_14+1
+    sta return_12+1
     jmp breturn
-  //SEG247 mul_u16_sel::@return
+  //SEG239 mul_u16_sel::@return
   breturn:
-  //SEG248 [124] return  [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] )
+  //SEG240 [121] return  [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] )
     rts
 }
-//SEG249 mul16u
+//SEG241 mul16u
 mul16u: {
-    .label _1 = $77
+    .label _1 = $75
     .label mb = $28
     .label a = $22
     .label res = $24
-    .label b = $67
-    .label return = $69
-  //SEG250 [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] ) -- vduz1=_dword_vwuz2 
+    .label b = $65
+    .label return = $67
+  //SEG242 [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) -- vduz1=_dword_vwuz2 
     lda b
     sta mb
     lda b+1
@@ -6468,43 +6365,43 @@ mul16u: {
     lda #0
     sta mb+2
     sta mb+3
-  //SEG251 [126] phi from mul16u to mul16u::@1 [phi:mul16u->mul16u::@1]
+  //SEG243 [123] phi from mul16u to mul16u::@1 [phi:mul16u->mul16u::@1]
   b1_from_mul16u:
-  //SEG252 [126] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#0 [phi:mul16u->mul16u::@1#0] -- register_copy 
-  //SEG253 [126] phi (dword) mul16u::res#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:mul16u->mul16u::@1#1] -- vduz1=vbuc1 
+  //SEG244 [123] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#0 [phi:mul16u->mul16u::@1#0] -- register_copy 
+  //SEG245 [123] phi (dword) mul16u::res#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:mul16u->mul16u::@1#1] -- vduz1=vbuc1 
     lda #0
     sta res
     lda #0
     sta res+1
     sta res+2
     sta res+3
-  //SEG254 [126] phi (word) mul16u::a#2 = (word) mul16u::a#1 [phi:mul16u->mul16u::@1#2] -- register_copy 
+  //SEG246 [123] phi (word) mul16u::a#2 = (word) mul16u::a#1 [phi:mul16u->mul16u::@1#2] -- register_copy 
     jmp b1
-  //SEG255 mul16u::@1
+  //SEG247 mul16u::@1
   b1:
-  //SEG256 [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vwuz1_neq_0_then_la1 
+  //SEG248 [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vwuz1_neq_0_then_la1 
     lda a
     bne b2
     lda a+1
     bne b2
     jmp breturn
-  //SEG257 mul16u::@return
+  //SEG249 mul16u::@return
   breturn:
-  //SEG258 [128] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
+  //SEG250 [125] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
     rts
-  //SEG259 mul16u::@2
+  //SEG251 mul16u::@2
   b2:
-  //SEG260 [129] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) -- vbuz1=vwuz2_band_vbuc1 
+  //SEG252 [126] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) -- vbuz1=vwuz2_band_vbuc1 
     lda a
     and #1
     sta _1
-  //SEG261 [130] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vbuz1_eq_0_then_la1 
+  //SEG253 [127] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vbuz1_eq_0_then_la1 
     lda _1
     beq b4_from_b2
     jmp b7
-  //SEG262 mul16u::@7
+  //SEG254 mul16u::@7
   b7:
-  //SEG263 [131] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) -- vduz1=vduz1_plus_vduz2 
+  //SEG255 [128] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) -- vduz1=vduz1_plus_vduz2 
     lda res
     clc
     adc mb
@@ -6518,183 +6415,183 @@ mul16u: {
     lda res+3
     adc mb+3
     sta res+3
-  //SEG264 [132] phi from mul16u::@2 mul16u::@7 to mul16u::@4 [phi:mul16u::@2/mul16u::@7->mul16u::@4]
+  //SEG256 [129] phi from mul16u::@2 mul16u::@7 to mul16u::@4 [phi:mul16u::@2/mul16u::@7->mul16u::@4]
   b4_from_b2:
   b4_from_b7:
-  //SEG265 [132] phi (dword) mul16u::res#6 = (dword) mul16u::res#2 [phi:mul16u::@2/mul16u::@7->mul16u::@4#0] -- register_copy 
+  //SEG257 [129] phi (dword) mul16u::res#6 = (dword) mul16u::res#2 [phi:mul16u::@2/mul16u::@7->mul16u::@4#0] -- register_copy 
     jmp b4
-  //SEG266 mul16u::@4
+  //SEG258 mul16u::@4
   b4:
-  //SEG267 [133] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ) -- vwuz1=vwuz1_ror_1 
+  //SEG259 [130] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ) -- vwuz1=vwuz1_ror_1 
     clc
     ror a+1
     ror a
-  //SEG268 [134] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ) -- vduz1=vduz1_rol_1 
+  //SEG260 [131] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ) -- vduz1=vduz1_rol_1 
     asl mb
     rol mb+1
     rol mb+2
     rol mb+3
-  //SEG269 [126] phi from mul16u::@4 to mul16u::@1 [phi:mul16u::@4->mul16u::@1]
+  //SEG261 [123] phi from mul16u::@4 to mul16u::@1 [phi:mul16u::@4->mul16u::@1]
   b1_from_b4:
-  //SEG270 [126] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#1 [phi:mul16u::@4->mul16u::@1#0] -- register_copy 
-  //SEG271 [126] phi (dword) mul16u::res#2 = (dword) mul16u::res#6 [phi:mul16u::@4->mul16u::@1#1] -- register_copy 
-  //SEG272 [126] phi (word) mul16u::a#2 = (word) mul16u::a#0 [phi:mul16u::@4->mul16u::@1#2] -- register_copy 
+  //SEG262 [123] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#1 [phi:mul16u::@4->mul16u::@1#0] -- register_copy 
+  //SEG263 [123] phi (dword) mul16u::res#2 = (dword) mul16u::res#6 [phi:mul16u::@4->mul16u::@1#1] -- register_copy 
+  //SEG264 [123] phi (word) mul16u::a#2 = (word) mul16u::a#0 [phi:mul16u::@4->mul16u::@1#2] -- register_copy 
     jmp b1
 }
-//SEG273 div32u16u
+//SEG265 div32u16u
 div32u16u: {
-    .label return = $39
-    .label quotient_hi = $7a
-    .label quotient_lo = $7e
-    .label return_1 = $80
-  //SEG274 [136] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
-  //SEG275 [145] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
+    .label quotient_hi = $78
+    .label quotient_lo = $7c
+    .label return = $7e
+    .label return_2 = $39
+  //SEG266 [133] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
+  //SEG267 [142] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
   divr16u_from_div32u16u:
-  //SEG276 [145] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
+  //SEG268 [142] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
     lda #<main.wavelength
     sta divr16u.divisor
     lda #>main.wavelength
     sta divr16u.divisor+1
-  //SEG277 [145] phi (word) divr16u::dividend#5 = >(const dword) PI2_u4f28#0 [phi:div32u16u->divr16u#1] -- vwuz1=vwuc1 
+  //SEG269 [142] phi (word) divr16u::dividend#5 = >(const dword) PI2_u4f28#0 [phi:div32u16u->divr16u#1] -- vwuz1=vwuc1 
     lda #<PI2_u4f28>>16
     sta divr16u.dividend
     lda #>PI2_u4f28>>16
     sta divr16u.dividend+1
-  //SEG278 [145] phi (word) divr16u::rem#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:div32u16u->divr16u#2] -- vwuz1=vbuc1 
+  //SEG270 [142] phi (word) divr16u::rem#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:div32u16u->divr16u#2] -- vwuz1=vbuc1 
     lda #<0
     sta divr16u.rem
     lda #>0
     sta divr16u.rem+1
     jsr divr16u
-  //SEG279 [137] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] ) -- vwuz1=vwuz2 
+  //SEG271 [134] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] ) -- vwuz1=vwuz2 
     lda divr16u.return
     sta divr16u.return_2
     lda divr16u.return+1
     sta divr16u.return_2+1
     jmp b2
-  //SEG280 div32u16u::@2
+  //SEG272 div32u16u::@2
   b2:
-  //SEG281 [138] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) -- vwuz1=vwuz2 
+  //SEG273 [135] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) -- vwuz1=vwuz2 
     lda divr16u.return_2
     sta quotient_hi
     lda divr16u.return_2+1
     sta quotient_hi+1
-  //SEG282 [139] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ) -- vwuz1=vwuz2 
+  //SEG274 [136] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ) -- vwuz1=vwuz2 
     lda rem16u
     sta divr16u.rem
     lda rem16u+1
     sta divr16u.rem+1
-  //SEG283 [140] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
-  //SEG284 [145] phi from div32u16u::@2 to divr16u [phi:div32u16u::@2->divr16u]
+  //SEG275 [137] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
+  //SEG276 [142] phi from div32u16u::@2 to divr16u [phi:div32u16u::@2->divr16u]
   divr16u_from_b2:
-  //SEG285 [145] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u::@2->divr16u#0] -- vwuz1=vwuc1 
+  //SEG277 [142] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u::@2->divr16u#0] -- vwuz1=vwuc1 
     lda #<main.wavelength
     sta divr16u.divisor
     lda #>main.wavelength
     sta divr16u.divisor+1
-  //SEG286 [145] phi (word) divr16u::dividend#5 = <(const dword) PI2_u4f28#0 [phi:div32u16u::@2->divr16u#1] -- vwuz1=vwuc1 
+  //SEG278 [142] phi (word) divr16u::dividend#5 = <(const dword) PI2_u4f28#0 [phi:div32u16u::@2->divr16u#1] -- vwuz1=vwuc1 
     lda #<PI2_u4f28&$ffff
     sta divr16u.dividend
     lda #>PI2_u4f28&$ffff
     sta divr16u.dividend+1
-  //SEG287 [145] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:div32u16u::@2->divr16u#2] -- register_copy 
+  //SEG279 [142] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:div32u16u::@2->divr16u#2] -- register_copy 
     jsr divr16u
-  //SEG288 [141] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ) -- vwuz1=vwuz2 
+  //SEG280 [138] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ) -- vwuz1=vwuz2 
     lda divr16u.return
     sta divr16u.return_3
     lda divr16u.return+1
     sta divr16u.return_3+1
     jmp b3
-  //SEG289 div32u16u::@3
+  //SEG281 div32u16u::@3
   b3:
-  //SEG290 [142] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ) -- vwuz1=vwuz2 
+  //SEG282 [139] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ) -- vwuz1=vwuz2 
     lda divr16u.return_3
     sta quotient_lo
     lda divr16u.return_3+1
     sta quotient_lo+1
-  //SEG291 [143] (dword) div32u16u::return#1 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] ) -- vduz1=vwuz2_dword_vwuz3 
+  //SEG283 [140] (dword) div32u16u::return#0 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] ) -- vduz1=vwuz2_dword_vwuz3 
     lda quotient_hi
-    sta return_1+2
+    sta return+2
     lda quotient_hi+1
-    sta return_1+3
+    sta return+3
     lda quotient_lo
-    sta return_1
+    sta return
     lda quotient_lo+1
-    sta return_1+1
+    sta return+1
     jmp breturn
-  //SEG292 div32u16u::@return
+  //SEG284 div32u16u::@return
   breturn:
-  //SEG293 [144] return  [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] )
+  //SEG285 [141] return  [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] )
     rts
 }
-//SEG294 divr16u
+//SEG286 divr16u
 divr16u: {
-    .label _1 = $84
-    .label _2 = $85
+    .label _1 = $82
+    .label _2 = $83
     .label rem = $2e
     .label dividend = $30
     .label quotient = $32
     .label i = $34
     .label return = $32
-    .label return_2 = $78
-    .label return_3 = $7c
+    .label return_2 = $76
+    .label return_3 = $7a
     .label divisor = $2c
-  //SEG295 [146] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
+  //SEG287 [143] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
   b1_from_divr16u:
-  //SEG296 [146] phi (byte) divr16u::i#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#0] -- vbuz1=vbuc1 
+  //SEG288 [143] phi (byte) divr16u::i#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#0] -- vbuz1=vbuc1 
     lda #0
     sta i
-  //SEG297 [146] phi (word) divr16u::quotient#3 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#1] -- vwuz1=vbuc1 
+  //SEG289 [143] phi (word) divr16u::quotient#3 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#1] -- vwuz1=vbuc1 
     lda #<0
     sta quotient
     lda #>0
     sta quotient+1
-  //SEG298 [146] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#5 [phi:divr16u->divr16u::@1#2] -- register_copy 
-  //SEG299 [146] phi (word) divr16u::rem#5 = (word) divr16u::rem#10 [phi:divr16u->divr16u::@1#3] -- register_copy 
+  //SEG290 [143] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#5 [phi:divr16u->divr16u::@1#2] -- register_copy 
+  //SEG291 [143] phi (word) divr16u::rem#5 = (word) divr16u::rem#10 [phi:divr16u->divr16u::@1#3] -- register_copy 
     jmp b1
-  //SEG300 [146] phi from divr16u::@3 to divr16u::@1 [phi:divr16u::@3->divr16u::@1]
+  //SEG292 [143] phi from divr16u::@3 to divr16u::@1 [phi:divr16u::@3->divr16u::@1]
   b1_from_b3:
-  //SEG301 [146] phi (byte) divr16u::i#2 = (byte) divr16u::i#1 [phi:divr16u::@3->divr16u::@1#0] -- register_copy 
-  //SEG302 [146] phi (word) divr16u::quotient#3 = (word) divr16u::return#0 [phi:divr16u::@3->divr16u::@1#1] -- register_copy 
-  //SEG303 [146] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#0 [phi:divr16u::@3->divr16u::@1#2] -- register_copy 
-  //SEG304 [146] phi (word) divr16u::rem#5 = (word) divr16u::rem#11 [phi:divr16u::@3->divr16u::@1#3] -- register_copy 
+  //SEG293 [143] phi (byte) divr16u::i#2 = (byte) divr16u::i#1 [phi:divr16u::@3->divr16u::@1#0] -- register_copy 
+  //SEG294 [143] phi (word) divr16u::quotient#3 = (word) divr16u::return#0 [phi:divr16u::@3->divr16u::@1#1] -- register_copy 
+  //SEG295 [143] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#0 [phi:divr16u::@3->divr16u::@1#2] -- register_copy 
+  //SEG296 [143] phi (word) divr16u::rem#5 = (word) divr16u::rem#11 [phi:divr16u::@3->divr16u::@1#3] -- register_copy 
     jmp b1
-  //SEG305 divr16u::@1
+  //SEG297 divr16u::@1
   b1:
-  //SEG306 [147] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG298 [144] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vwuz1=vwuz1_rol_1 
     asl rem
     rol rem+1
-  //SEG307 [148] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) -- vbuz1=_hi_vwuz2 
+  //SEG299 [145] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) -- vbuz1=_hi_vwuz2 
     lda dividend+1
     sta _1
-  //SEG308 [149] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) -- vbuz1=vbuz2_band_vbuc1 
+  //SEG300 [146] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) -- vbuz1=vbuz2_band_vbuc1 
     lda #$80
     and _1
     sta _2
-  //SEG309 [150] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vbuz1_eq_0_then_la1 
+  //SEG301 [147] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vbuz1_eq_0_then_la1 
     lda _2
     beq b2_from_b1
     jmp b4
-  //SEG310 divr16u::@4
+  //SEG302 divr16u::@4
   b4:
-  //SEG311 [151] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) -- vwuz1=vwuz1_bor_vbuc1 
+  //SEG303 [148] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) -- vwuz1=vwuz1_bor_vbuc1 
     lda #1
     ora rem
     sta rem
-  //SEG312 [152] phi from divr16u::@1 divr16u::@4 to divr16u::@2 [phi:divr16u::@1/divr16u::@4->divr16u::@2]
+  //SEG304 [149] phi from divr16u::@1 divr16u::@4 to divr16u::@2 [phi:divr16u::@1/divr16u::@4->divr16u::@2]
   b2_from_b1:
   b2_from_b4:
-  //SEG313 [152] phi (word) divr16u::rem#6 = (word) divr16u::rem#0 [phi:divr16u::@1/divr16u::@4->divr16u::@2#0] -- register_copy 
+  //SEG305 [149] phi (word) divr16u::rem#6 = (word) divr16u::rem#0 [phi:divr16u::@1/divr16u::@4->divr16u::@2#0] -- register_copy 
     jmp b2
-  //SEG314 divr16u::@2
+  //SEG306 divr16u::@2
   b2:
-  //SEG315 [153] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG307 [150] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ) -- vwuz1=vwuz1_rol_1 
     asl dividend
     rol dividend+1
-  //SEG316 [154] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG308 [151] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1=vwuz1_rol_1 
     asl quotient
     rol quotient+1
-  //SEG317 [155] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1_lt_vwuz2_then_la1 
+  //SEG309 [152] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1_lt_vwuz2_then_la1 
     lda rem+1
     cmp divisor+1
     bcc b3_from_b2
@@ -6704,14 +6601,14 @@ divr16u: {
     bcc b3_from_b2
   !:
     jmp b5
-  //SEG318 divr16u::@5
+  //SEG310 divr16u::@5
   b5:
-  //SEG319 [156] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ) -- vwuz1=_inc_vwuz1 
+  //SEG311 [153] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ) -- vwuz1=_inc_vwuz1 
     inc quotient
     bne !+
     inc quotient+1
   !:
-  //SEG320 [157] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) -- vwuz1=vwuz1_minus_vwuz2 
+  //SEG312 [154] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) -- vwuz1=vwuz1_minus_vwuz2 
     lda rem
     sec
     sbc divisor
@@ -6719,32 +6616,32 @@ divr16u: {
     lda rem+1
     sbc divisor+1
     sta rem+1
-  //SEG321 [158] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
+  //SEG313 [155] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
   b3_from_b2:
   b3_from_b5:
-  //SEG322 [158] phi (word) divr16u::return#0 = (word) divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy 
-  //SEG323 [158] phi (word) divr16u::rem#11 = (word) divr16u::rem#6 [phi:divr16u::@2/divr16u::@5->divr16u::@3#1] -- register_copy 
+  //SEG314 [155] phi (word) divr16u::return#0 = (word) divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy 
+  //SEG315 [155] phi (word) divr16u::rem#11 = (word) divr16u::rem#6 [phi:divr16u::@2/divr16u::@5->divr16u::@3#1] -- register_copy 
     jmp b3
-  //SEG324 divr16u::@3
+  //SEG316 divr16u::@3
   b3:
-  //SEG325 [159] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuz1=_inc_vbuz1 
+  //SEG317 [156] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuz1=_inc_vbuz1 
     inc i
-  //SEG326 [160] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuz1_neq_vbuc1_then_la1 
+  //SEG318 [157] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuz1_neq_vbuc1_then_la1 
     lda i
     cmp #$10
     bne b1_from_b3
     jmp b6
-  //SEG327 divr16u::@6
+  //SEG319 divr16u::@6
   b6:
-  //SEG328 [161] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] ) -- vwuz1=vwuz2 
+  //SEG320 [158] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] ) -- vwuz1=vwuz2 
     lda rem
     sta rem16u
     lda rem+1
     sta rem16u+1
     jmp breturn
-  //SEG329 divr16u::@return
+  //SEG321 divr16u::@return
   breturn:
-  //SEG330 [162] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  //SEG322 [159] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
     rts
 }
 
@@ -6765,8 +6662,8 @@ Statement [49] *((byte*) char_cursor#33) ← (byte) print_char::ch#3 [ char_curs
 Removing always clobbered register reg byte y as potential for zp ZP_BYTE:8 [ print_byte::b#2 print_byte::b#0 print_byte::b#1 ]
 Statement [54] *((byte*) print_cls::sc#2) ← (byte) ' ' [ print_cls::sc#2 ] ( main:2::print_cls:7 [ print_cls::sc#2 ] ) always clobbers reg byte a reg byte y 
 Statement [56] if((byte*) print_cls::sc#1!=(const byte*) SCREEN#0+(word/signed word/dword/signed dword) 1000) goto print_cls::@1 [ print_cls::sc#1 ] ( main:2::print_cls:7 [ print_cls::sc#1 ] ) always clobbers reg byte a 
-Statement [60] (dword) div32u16u::return#0 ← (dword) div32u16u::return#1 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] ) always clobbers reg byte a 
-Statement [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#0 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] ) always clobbers reg byte a 
+Statement [60] (dword) div32u16u::return#2 ← (dword) div32u16u::return#0 [ div32u16u::return#2 ] ( main:2::sin16s_gen:5 [ div32u16u::return#2 ] ) always clobbers reg byte a 
+Statement [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#2 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] ) always clobbers reg byte a 
 Statement [63] (dword) sin16s::x#0 ← (dword) sin16s_gen::x#2 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#0 ] ) always clobbers reg byte a 
 Statement [65] (signed word) sin16s::return#0 ← (signed word) sin16s::return#1 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#0 ] ) always clobbers reg byte a 
 Statement [66] (signed word~) sin16s_gen::$1 ← (signed word) sin16s::return#0 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s_gen::$1 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s_gen::$1 ] ) always clobbers reg byte a 
@@ -6776,63 +6673,61 @@ Statement [69] (dword) sin16s_gen::x#1 ← (dword) sin16s_gen::x#2 + (dword) sin
 Statement [71] if((word) sin16s_gen::i#1<(const word) main::wavelength#0) goto sin16s_gen::@1 [ sin16s_gen::step#0 sin16s_gen::x#1 sin16s_gen::sintab#1 sin16s_gen::i#1 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#1 sin16s_gen::sintab#1 sin16s_gen::i#1 ] ) always clobbers reg byte a 
 Statement [73] if((dword) sin16s::x#0<(const dword) PI_u4f28#0) goto sin16s::@1 [ sin16s::x#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#0 ] ) always clobbers reg byte a 
 Statement [74] (dword) sin16s::x#1 ← (dword) sin16s::x#0 - (const dword) PI_u4f28#0 [ sin16s::x#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#1 ] ) always clobbers reg byte a 
-Statement [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] ) always clobbers reg byte a 
-Removing always clobbered register reg byte a as potential for zp ZP_BYTE:22 [ sin16s::isUpper#10 ]
-Statement [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#10 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#2 ] ) always clobbers reg byte a 
-Statement [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#10 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::$6 ] ) always clobbers reg byte a reg byte y 
-Removing always clobbered register reg byte y as potential for zp ZP_BYTE:22 [ sin16s::isUpper#10 ]
-Statement [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#10 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 ] ) always clobbers reg byte a 
-Statement [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ) always clobbers reg byte a 
-Statement [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) always clobbers reg byte a 
-Statement [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ) always clobbers reg byte a 
-Statement [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ) always clobbers reg byte a 
-Statement [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ) always clobbers reg byte a 
-Statement [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) always clobbers reg byte a 
-Statement [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ) always clobbers reg byte a 
-Statement [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ) always clobbers reg byte a 
-Statement [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ) always clobbers reg byte a 
-Statement [93] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ) always clobbers reg byte a 
-Statement [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ) always clobbers reg byte a 
-Statement [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) always clobbers reg byte a 
-Statement [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ) always clobbers reg byte a 
-Statement [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) always clobbers reg byte a 
-Statement [99] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ) always clobbers reg byte a 
-Statement [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ) always clobbers reg byte a 
-Statement [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ) always clobbers reg byte a 
-Statement [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) always clobbers reg byte a 
-Statement [104] (word) mul_u16_sel::return#12 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ) always clobbers reg byte a 
-Statement [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ) always clobbers reg byte a 
-Statement [106] (word) mul_u16_sel::v1#5 ← (word) sin16s::x5#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ) always clobbers reg byte a 
-Statement [108] (word) mul_u16_sel::return#13 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ) always clobbers reg byte a 
-Statement [109] (word) sin16s::x5_128#0 ← (word) mul_u16_sel::return#13 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ) always clobbers reg byte a 
-Statement [110] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#10 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#1 ] ) always clobbers reg byte a 
-Statement [112] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) always clobbers reg byte a 
-Statement [115] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) always clobbers reg byte a 
-Statement [117] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#6 [ mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ) always clobbers reg byte a 
-Removing always clobbered register reg byte a as potential for zp ZP_BYTE:33 [ mul_u16_sel::select#6 ]
-Statement [118] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#6 [ mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a 
-Statement [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#6 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] ) always clobbers reg byte a 
-Statement [121] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#6 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] ) always clobbers reg byte a 
-Statement [122] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#6 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] ) always clobbers reg byte a reg byte x 
-Removing always clobbered register reg byte x as potential for zp ZP_BYTE:22 [ sin16s::isUpper#10 ]
-Statement [123] (word) mul_u16_sel::return#14 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] ) always clobbers reg byte a 
-Statement [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a 
-Statement [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a 
-Statement [129] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) always clobbers reg byte a 
-Statement [131] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) always clobbers reg byte a 
-Statement [137] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] ) always clobbers reg byte a 
-Statement [138] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) always clobbers reg byte a 
-Statement [139] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ) always clobbers reg byte a 
-Statement [141] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ) always clobbers reg byte a 
-Statement [142] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ) always clobbers reg byte a 
-Statement [143] (dword) div32u16u::return#1 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] ) always clobbers reg byte a 
-Statement [148] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) always clobbers reg byte a 
+Statement [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] ) always clobbers reg byte a 
+Removing always clobbered register reg byte a as potential for zp ZP_BYTE:22 [ sin16s::isUpper#2 ]
+Statement [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#2 ] ) always clobbers reg byte a 
+Statement [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#2 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::$6 ] ) always clobbers reg byte a reg byte y 
+Removing always clobbered register reg byte y as potential for zp ZP_BYTE:22 [ sin16s::isUpper#2 ]
+Statement [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 ] ) always clobbers reg byte a 
+Statement [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ) always clobbers reg byte a 
+Statement [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) always clobbers reg byte a 
+Statement [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ) always clobbers reg byte a 
+Statement [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ) always clobbers reg byte a 
+Statement [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ) always clobbers reg byte a 
+Statement [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) always clobbers reg byte a 
+Statement [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ) always clobbers reg byte a 
+Statement [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ) always clobbers reg byte a 
+Statement [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ) always clobbers reg byte a 
+Statement [93] (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ) always clobbers reg byte a 
+Statement [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ) always clobbers reg byte a 
+Statement [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) always clobbers reg byte a 
+Statement [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ) always clobbers reg byte a 
+Statement [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) always clobbers reg byte a 
+Statement [99] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ) always clobbers reg byte a 
+Statement [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ) always clobbers reg byte a 
+Statement [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ) always clobbers reg byte a 
+Statement [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) always clobbers reg byte a 
+Statement [104] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ) always clobbers reg byte a 
+Statement [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ) always clobbers reg byte a 
+Statement [106] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) always clobbers reg byte a reg byte y 
+Statement [107] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) always clobbers reg byte a 
+Statement [109] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) always clobbers reg byte a 
+Statement [112] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) always clobbers reg byte a 
+Statement [114] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#5 [ mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ) always clobbers reg byte a 
+Removing always clobbered register reg byte a as potential for zp ZP_BYTE:33 [ mul_u16_sel::select#5 ]
+Statement [115] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#5 [ mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a 
+Statement [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] ) always clobbers reg byte a 
+Statement [118] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#5 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] ) always clobbers reg byte a 
+Statement [119] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#5 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::$1 ] ) always clobbers reg byte a reg byte x 
+Removing always clobbered register reg byte x as potential for zp ZP_BYTE:22 [ sin16s::isUpper#2 ]
+Statement [120] (word) mul_u16_sel::return#12 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] ) always clobbers reg byte a 
+Statement [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a 
+Statement [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a 
+Statement [126] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) always clobbers reg byte a 
+Statement [128] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) always clobbers reg byte a 
+Statement [134] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] ) always clobbers reg byte a 
+Statement [135] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) always clobbers reg byte a 
+Statement [136] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ) always clobbers reg byte a 
+Statement [138] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ) always clobbers reg byte a 
+Statement [139] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ) always clobbers reg byte a 
+Statement [140] (dword) div32u16u::return#0 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] ) always clobbers reg byte a 
+Statement [145] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) always clobbers reg byte a 
 Removing always clobbered register reg byte a as potential for zp ZP_BYTE:52 [ divr16u::i#2 divr16u::i#1 ]
-Statement [149] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) always clobbers reg byte a 
-Statement [151] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) always clobbers reg byte a 
-Statement [155] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) always clobbers reg byte a 
-Statement [157] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) always clobbers reg byte a 
-Statement [161] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] ) always clobbers reg byte a 
+Statement [146] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) always clobbers reg byte a 
+Statement [148] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) always clobbers reg byte a 
+Statement [152] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) always clobbers reg byte a 
+Statement [154] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) always clobbers reg byte a 
+Statement [158] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] ) always clobbers reg byte a 
 Statement [9] (signed word) main::sw#0 ← *((signed word*) main::st1#2) [ main::st1#2 char_cursor#49 main::sw#0 ] ( main:2 [ main::st1#2 char_cursor#49 main::sw#0 ] ) always clobbers reg byte a reg byte y 
 Statement [10] if((signed word) main::sw#0<(byte/signed byte/word/signed word/dword/signed dword) 0) goto main::@2 [ main::st1#2 char_cursor#49 main::sw#0 ] ( main:2 [ main::st1#2 char_cursor#49 main::sw#0 ] ) always clobbers reg byte a 
 Statement [14] (signed word) print_sword::w#1 ← (signed word) main::sw#0 [ main::st1#2 char_cursor#48 print_sword::w#1 ] ( main:2 [ main::st1#2 char_cursor#48 print_sword::w#1 ] ) always clobbers reg byte a 
@@ -6848,8 +6743,8 @@ Statement [44] (byte~) print_byte::$2 ← (byte) print_byte::b#2 & (byte/signed
 Statement [49] *((byte*) char_cursor#33) ← (byte) print_char::ch#3 [ char_cursor#33 ] ( main:2::print_sword:15::print_char:30 [ main::st1#2 print_sword::w#1 char_cursor#33 ] main:2::print_sword:15::print_word:33::print_byte:36::print_char:43 [ main::st1#2 print_sword::w#3 print_byte::b#2 char_cursor#33 ] main:2::print_sword:15::print_word:33::print_byte:38::print_char:43 [ main::st1#2 print_byte::b#2 char_cursor#33 ] main:2::print_sword:15::print_word:33::print_byte:36::print_char:46 [ main::st1#2 print_sword::w#3 char_cursor#33 ] main:2::print_sword:15::print_word:33::print_byte:38::print_char:46 [ main::st1#2 char_cursor#33 ] ) always clobbers reg byte y 
 Statement [54] *((byte*) print_cls::sc#2) ← (byte) ' ' [ print_cls::sc#2 ] ( main:2::print_cls:7 [ print_cls::sc#2 ] ) always clobbers reg byte a reg byte y 
 Statement [56] if((byte*) print_cls::sc#1!=(const byte*) SCREEN#0+(word/signed word/dword/signed dword) 1000) goto print_cls::@1 [ print_cls::sc#1 ] ( main:2::print_cls:7 [ print_cls::sc#1 ] ) always clobbers reg byte a 
-Statement [60] (dword) div32u16u::return#0 ← (dword) div32u16u::return#1 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] ) always clobbers reg byte a 
-Statement [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#0 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] ) always clobbers reg byte a 
+Statement [60] (dword) div32u16u::return#2 ← (dword) div32u16u::return#0 [ div32u16u::return#2 ] ( main:2::sin16s_gen:5 [ div32u16u::return#2 ] ) always clobbers reg byte a 
+Statement [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#2 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] ) always clobbers reg byte a 
 Statement [63] (dword) sin16s::x#0 ← (dword) sin16s_gen::x#2 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#0 ] ) always clobbers reg byte a 
 Statement [65] (signed word) sin16s::return#0 ← (signed word) sin16s::return#1 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#0 ] ) always clobbers reg byte a 
 Statement [66] (signed word~) sin16s_gen::$1 ← (signed word) sin16s::return#0 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s_gen::$1 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s_gen::$1 ] ) always clobbers reg byte a 
@@ -6859,59 +6754,57 @@ Statement [69] (dword) sin16s_gen::x#1 ← (dword) sin16s_gen::x#2 + (dword) sin
 Statement [71] if((word) sin16s_gen::i#1<(const word) main::wavelength#0) goto sin16s_gen::@1 [ sin16s_gen::step#0 sin16s_gen::x#1 sin16s_gen::sintab#1 sin16s_gen::i#1 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 sin16s_gen::x#1 sin16s_gen::sintab#1 sin16s_gen::i#1 ] ) always clobbers reg byte a 
 Statement [73] if((dword) sin16s::x#0<(const dword) PI_u4f28#0) goto sin16s::@1 [ sin16s::x#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#0 ] ) always clobbers reg byte a 
 Statement [74] (dword) sin16s::x#1 ← (dword) sin16s::x#0 - (const dword) PI_u4f28#0 [ sin16s::x#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#1 ] ) always clobbers reg byte a 
-Statement [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] ) always clobbers reg byte a 
-Statement [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#10 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#2 ] ) always clobbers reg byte a 
-Statement [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#10 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::$6 ] ) always clobbers reg byte a reg byte y 
-Statement [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#10 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 ] ) always clobbers reg byte a 
-Statement [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ) always clobbers reg byte a 
-Statement [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) always clobbers reg byte a 
-Statement [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ) always clobbers reg byte a 
-Statement [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ) always clobbers reg byte a 
-Statement [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ) always clobbers reg byte a 
-Statement [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) always clobbers reg byte a 
-Statement [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ) always clobbers reg byte a 
-Statement [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ) always clobbers reg byte a 
-Statement [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ) always clobbers reg byte a 
-Statement [93] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ) always clobbers reg byte a 
-Statement [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ) always clobbers reg byte a 
-Statement [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) always clobbers reg byte a 
-Statement [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ) always clobbers reg byte a 
-Statement [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) always clobbers reg byte a 
-Statement [99] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ) always clobbers reg byte a 
-Statement [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ) always clobbers reg byte a 
-Statement [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ) always clobbers reg byte a 
-Statement [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) always clobbers reg byte a 
-Statement [104] (word) mul_u16_sel::return#12 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ) always clobbers reg byte a 
-Statement [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ) always clobbers reg byte a 
-Statement [106] (word) mul_u16_sel::v1#5 ← (word) sin16s::x5#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ) always clobbers reg byte a 
-Statement [108] (word) mul_u16_sel::return#13 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ) always clobbers reg byte a 
-Statement [109] (word) sin16s::x5_128#0 ← (word) mul_u16_sel::return#13 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ) always clobbers reg byte a 
-Statement [110] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#10 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#1 ] ) always clobbers reg byte a 
-Statement [111] if((byte) sin16s::isUpper#10==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@16 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) always clobbers reg byte a 
-Statement [112] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) always clobbers reg byte a 
-Statement [115] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) always clobbers reg byte a 
-Statement [117] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#6 [ mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ) always clobbers reg byte a 
-Statement [118] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#6 [ mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a 
-Statement [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#6 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] ) always clobbers reg byte a 
-Statement [121] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#6 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] ) always clobbers reg byte a 
-Statement [122] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#6 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] ) always clobbers reg byte a reg byte x 
-Statement [123] (word) mul_u16_sel::return#14 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] ) always clobbers reg byte a 
-Statement [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a 
-Statement [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a 
-Statement [129] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) always clobbers reg byte a 
-Statement [131] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) always clobbers reg byte a 
-Statement [137] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] ) always clobbers reg byte a 
-Statement [138] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) always clobbers reg byte a 
-Statement [139] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ) always clobbers reg byte a 
-Statement [141] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ) always clobbers reg byte a 
-Statement [142] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ) always clobbers reg byte a 
-Statement [143] (dword) div32u16u::return#1 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] ) always clobbers reg byte a 
-Statement [148] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) always clobbers reg byte a 
-Statement [149] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) always clobbers reg byte a 
-Statement [151] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) always clobbers reg byte a 
-Statement [155] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) always clobbers reg byte a 
-Statement [157] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) always clobbers reg byte a 
-Statement [161] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] ) always clobbers reg byte a 
+Statement [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] ) always clobbers reg byte a 
+Statement [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#2 ] ) always clobbers reg byte a 
+Statement [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#2 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::$6 ] ) always clobbers reg byte a reg byte y 
+Statement [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 ] ) always clobbers reg byte a 
+Statement [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ) always clobbers reg byte a 
+Statement [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) always clobbers reg byte a 
+Statement [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ) always clobbers reg byte a 
+Statement [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ) always clobbers reg byte a 
+Statement [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ) always clobbers reg byte a 
+Statement [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) always clobbers reg byte a 
+Statement [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ) always clobbers reg byte a 
+Statement [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ) always clobbers reg byte a 
+Statement [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ) always clobbers reg byte a 
+Statement [93] (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ) always clobbers reg byte a 
+Statement [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ) always clobbers reg byte a 
+Statement [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) always clobbers reg byte a 
+Statement [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ) always clobbers reg byte a 
+Statement [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) always clobbers reg byte a 
+Statement [99] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ) always clobbers reg byte a 
+Statement [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ) always clobbers reg byte a 
+Statement [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ) always clobbers reg byte a 
+Statement [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) always clobbers reg byte a 
+Statement [104] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ) always clobbers reg byte a 
+Statement [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ) always clobbers reg byte a 
+Statement [106] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) always clobbers reg byte a reg byte y 
+Statement [107] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) always clobbers reg byte a 
+Statement [108] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) always clobbers reg byte a 
+Statement [109] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) always clobbers reg byte a 
+Statement [112] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) always clobbers reg byte a 
+Statement [114] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#5 [ mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ) always clobbers reg byte a 
+Statement [115] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#5 [ mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a 
+Statement [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] ) always clobbers reg byte a 
+Statement [118] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#5 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] ) always clobbers reg byte a 
+Statement [119] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#5 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::$1 ] ) always clobbers reg byte a reg byte x 
+Statement [120] (word) mul_u16_sel::return#12 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] ) always clobbers reg byte a 
+Statement [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a 
+Statement [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a 
+Statement [126] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) always clobbers reg byte a 
+Statement [128] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) always clobbers reg byte a 
+Statement [134] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] ) always clobbers reg byte a 
+Statement [135] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) always clobbers reg byte a 
+Statement [136] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ) always clobbers reg byte a 
+Statement [138] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ) always clobbers reg byte a 
+Statement [139] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ) always clobbers reg byte a 
+Statement [140] (dword) div32u16u::return#0 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] ) always clobbers reg byte a 
+Statement [145] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) always clobbers reg byte a 
+Statement [146] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) always clobbers reg byte a 
+Statement [148] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) always clobbers reg byte a 
+Statement [152] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) always clobbers reg byte a 
+Statement [154] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) always clobbers reg byte a 
+Statement [158] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] ) always clobbers reg byte a 
 Potential registers zp ZP_WORD:2 [ main::st1#2 main::st1#1 ] : zp ZP_WORD:2 , 
 Potential registers zp ZP_WORD:4 [ print_str::str#3 print_str::str#5 print_str::str#0 ] : zp ZP_WORD:4 , 
 Potential registers zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 ] : zp ZP_WORD:6 , 
@@ -6922,12 +6815,12 @@ Potential registers zp ZP_WORD:12 [ print_cls::sc#2 print_cls::sc#1 ] : zp ZP_WO
 Potential registers zp ZP_DWORD:14 [ sin16s_gen::x#2 sin16s_gen::x#1 ] : zp ZP_DWORD:14 , 
 Potential registers zp ZP_WORD:18 [ sin16s_gen::sintab#2 sin16s_gen::sintab#1 ] : zp ZP_WORD:18 , 
 Potential registers zp ZP_WORD:20 [ sin16s_gen::i#2 sin16s_gen::i#1 ] : zp ZP_WORD:20 , 
-Potential registers zp ZP_BYTE:22 [ sin16s::isUpper#10 ] : zp ZP_BYTE:22 , 
+Potential registers zp ZP_BYTE:22 [ sin16s::isUpper#2 ] : zp ZP_BYTE:22 , 
 Potential registers zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] : zp ZP_DWORD:23 , 
 Potential registers zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] : zp ZP_WORD:27 , 
-Potential registers zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ] : zp ZP_WORD:29 , 
-Potential registers zp ZP_WORD:31 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ] : zp ZP_WORD:31 , 
-Potential registers zp ZP_BYTE:33 [ mul_u16_sel::select#6 ] : zp ZP_BYTE:33 , reg byte x , reg byte y , 
+Potential registers zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ] : zp ZP_WORD:29 , 
+Potential registers zp ZP_WORD:31 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ] : zp ZP_WORD:31 , 
+Potential registers zp ZP_BYTE:33 [ mul_u16_sel::select#5 ] : zp ZP_BYTE:33 , reg byte x , reg byte y , 
 Potential registers zp ZP_WORD:34 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ] : zp ZP_WORD:34 , 
 Potential registers zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] : zp ZP_DWORD:36 , 
 Potential registers zp ZP_DWORD:40 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] : zp ZP_DWORD:40 , 
@@ -6939,7 +6832,7 @@ Potential registers zp ZP_BYTE:52 [ divr16u::i#2 divr16u::i#1 ] : zp ZP_BYTE:52
 Potential registers zp ZP_WORD:53 [ main::sw#0 ] : zp ZP_WORD:53 , 
 Potential registers zp ZP_BYTE:55 [ print_byte::$0 ] : zp ZP_BYTE:55 , reg byte a , reg byte x , reg byte y , 
 Potential registers zp ZP_BYTE:56 [ print_byte::$2 ] : zp ZP_BYTE:56 , reg byte a , reg byte x , reg byte y , 
-Potential registers zp ZP_DWORD:57 [ div32u16u::return#0 ] : zp ZP_DWORD:57 , 
+Potential registers zp ZP_DWORD:57 [ div32u16u::return#2 ] : zp ZP_DWORD:57 , 
 Potential registers zp ZP_DWORD:61 [ sin16s_gen::step#0 ] : zp ZP_DWORD:61 , 
 Potential registers zp ZP_WORD:65 [ sin16s::return#0 ] : zp ZP_WORD:65 , 
 Potential registers zp ZP_WORD:67 [ sin16s_gen::$1 ] : zp ZP_WORD:67 , 
@@ -6949,91 +6842,89 @@ Potential registers zp ZP_WORD:75 [ mul_u16_sel::return#0 ] : zp ZP_WORD:75 ,
 Potential registers zp ZP_WORD:77 [ sin16s::x2#0 ] : zp ZP_WORD:77 , 
 Potential registers zp ZP_WORD:79 [ mul_u16_sel::return#1 ] : zp ZP_WORD:79 , 
 Potential registers zp ZP_WORD:81 [ sin16s::x3#0 ] : zp ZP_WORD:81 , 
-Potential registers zp ZP_WORD:83 [ mul_u16_sel::return#10 ] : zp ZP_WORD:83 , 
+Potential registers zp ZP_WORD:83 [ mul_u16_sel::return#2 ] : zp ZP_WORD:83 , 
 Potential registers zp ZP_WORD:85 [ sin16s::x3_6#0 ] : zp ZP_WORD:85 , 
 Potential registers zp ZP_WORD:87 [ sin16s::usinx#0 ] : zp ZP_WORD:87 , 
-Potential registers zp ZP_WORD:89 [ mul_u16_sel::return#11 ] : zp ZP_WORD:89 , 
+Potential registers zp ZP_WORD:89 [ mul_u16_sel::return#10 ] : zp ZP_WORD:89 , 
 Potential registers zp ZP_WORD:91 [ sin16s::x4#0 ] : zp ZP_WORD:91 , 
-Potential registers zp ZP_WORD:93 [ mul_u16_sel::return#12 ] : zp ZP_WORD:93 , 
+Potential registers zp ZP_WORD:93 [ mul_u16_sel::return#11 ] : zp ZP_WORD:93 , 
 Potential registers zp ZP_WORD:95 [ sin16s::x5#0 ] : zp ZP_WORD:95 , 
-Potential registers zp ZP_WORD:97 [ mul_u16_sel::return#13 ] : zp ZP_WORD:97 , 
-Potential registers zp ZP_WORD:99 [ sin16s::x5_128#0 ] : zp ZP_WORD:99 , 
-Potential registers zp ZP_WORD:101 [ sin16s::usinx#1 ] : zp ZP_WORD:101 , 
-Potential registers zp ZP_WORD:103 [ mul16u::b#0 ] : zp ZP_WORD:103 , 
-Potential registers zp ZP_DWORD:105 [ mul16u::return#2 ] : zp ZP_DWORD:105 , 
-Potential registers zp ZP_DWORD:109 [ mul_u16_sel::$0 ] : zp ZP_DWORD:109 , 
-Potential registers zp ZP_DWORD:113 [ mul_u16_sel::$1 ] : zp ZP_DWORD:113 , 
-Potential registers zp ZP_WORD:117 [ mul_u16_sel::return#14 ] : zp ZP_WORD:117 , 
-Potential registers zp ZP_BYTE:119 [ mul16u::$1 ] : zp ZP_BYTE:119 , reg byte a , reg byte x , reg byte y , 
-Potential registers zp ZP_WORD:120 [ divr16u::return#2 ] : zp ZP_WORD:120 , 
-Potential registers zp ZP_WORD:122 [ div32u16u::quotient_hi#0 ] : zp ZP_WORD:122 , 
-Potential registers zp ZP_WORD:124 [ divr16u::return#3 ] : zp ZP_WORD:124 , 
-Potential registers zp ZP_WORD:126 [ div32u16u::quotient_lo#0 ] : zp ZP_WORD:126 , 
-Potential registers zp ZP_DWORD:128 [ div32u16u::return#1 ] : zp ZP_DWORD:128 , 
-Potential registers zp ZP_BYTE:132 [ divr16u::$1 ] : zp ZP_BYTE:132 , reg byte a , reg byte x , reg byte y , 
-Potential registers zp ZP_BYTE:133 [ divr16u::$2 ] : zp ZP_BYTE:133 , reg byte a , reg byte x , reg byte y , 
-Potential registers zp ZP_WORD:134 [ rem16u#1 ] : zp ZP_WORD:134 , 
+Potential registers zp ZP_WORD:97 [ sin16s::x5_128#0 ] : zp ZP_WORD:97 , 
+Potential registers zp ZP_WORD:99 [ sin16s::usinx#1 ] : zp ZP_WORD:99 , 
+Potential registers zp ZP_WORD:101 [ mul16u::b#0 ] : zp ZP_WORD:101 , 
+Potential registers zp ZP_DWORD:103 [ mul16u::return#2 ] : zp ZP_DWORD:103 , 
+Potential registers zp ZP_DWORD:107 [ mul_u16_sel::$0 ] : zp ZP_DWORD:107 , 
+Potential registers zp ZP_DWORD:111 [ mul_u16_sel::$1 ] : zp ZP_DWORD:111 , 
+Potential registers zp ZP_WORD:115 [ mul_u16_sel::return#12 ] : zp ZP_WORD:115 , 
+Potential registers zp ZP_BYTE:117 [ mul16u::$1 ] : zp ZP_BYTE:117 , reg byte a , reg byte x , reg byte y , 
+Potential registers zp ZP_WORD:118 [ divr16u::return#2 ] : zp ZP_WORD:118 , 
+Potential registers zp ZP_WORD:120 [ div32u16u::quotient_hi#0 ] : zp ZP_WORD:120 , 
+Potential registers zp ZP_WORD:122 [ divr16u::return#3 ] : zp ZP_WORD:122 , 
+Potential registers zp ZP_WORD:124 [ div32u16u::quotient_lo#0 ] : zp ZP_WORD:124 , 
+Potential registers zp ZP_DWORD:126 [ div32u16u::return#0 ] : zp ZP_DWORD:126 , 
+Potential registers zp ZP_BYTE:130 [ divr16u::$1 ] : zp ZP_BYTE:130 , reg byte a , reg byte x , reg byte y , 
+Potential registers zp ZP_BYTE:131 [ divr16u::$2 ] : zp ZP_BYTE:131 , reg byte a , reg byte x , reg byte y , 
+Potential registers zp ZP_WORD:132 [ rem16u#1 ] : zp ZP_WORD:132 , 
 
 REGISTER UPLIFT SCOPES
-Uplift Scope [mul16u] 353.83: zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] 249.57: zp ZP_DWORD:40 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] 202: zp ZP_BYTE:119 [ mul16u::$1 ] 170: zp ZP_WORD:34 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ] 4: zp ZP_WORD:103 [ mul16u::b#0 ] 4: zp ZP_DWORD:105 [ mul16u::return#2 ] 
+Uplift Scope [mul16u] 353.83: zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] 249.57: zp ZP_DWORD:40 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] 202: zp ZP_BYTE:117 [ mul16u::$1 ] 170: zp ZP_WORD:34 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ] 4: zp ZP_WORD:101 [ mul16u::b#0 ] 4: zp ZP_DWORD:103 [ mul16u::return#2 ] 
 Uplift Scope [print_str] 305.5: zp ZP_WORD:4 [ print_str::str#3 print_str::str#5 print_str::str#0 ] 
-Uplift Scope [divr16u] 106.92: zp ZP_WORD:46 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] 35.54: zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] 22: zp ZP_BYTE:132 [ divr16u::$1 ] 22: zp ZP_BYTE:133 [ divr16u::$2 ] 18.19: zp ZP_BYTE:52 [ divr16u::i#2 divr16u::i#1 ] 9.75: zp ZP_WORD:48 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] 4: zp ZP_WORD:120 [ divr16u::return#2 ] 4: zp ZP_WORD:124 [ divr16u::return#3 ] 1.38: zp ZP_WORD:44 [ divr16u::divisor#6 ] 
-Uplift Scope [] 191.74: zp ZP_WORD:10 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 ] 0.8: zp ZP_WORD:134 [ rem16u#1 ] 
-Uplift Scope [sin16s] 27.5: zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] 22: zp ZP_WORD:65 [ sin16s::return#0 ] 13: zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] 4: zp ZP_DWORD:69 [ sin16s::$6 ] 4: zp ZP_WORD:77 [ sin16s::x2#0 ] 4: zp ZP_WORD:85 [ sin16s::x3_6#0 ] 4: zp ZP_WORD:91 [ sin16s::x4#0 ] 4: zp ZP_WORD:95 [ sin16s::x5#0 ] 4: zp ZP_WORD:99 [ sin16s::x5_128#0 ] 1: zp ZP_WORD:81 [ sin16s::x3#0 ] 1: zp ZP_WORD:101 [ sin16s::usinx#1 ] 0.64: zp ZP_WORD:73 [ sin16s::x1#0 ] 0.27: zp ZP_WORD:87 [ sin16s::usinx#0 ] 0.06: zp ZP_BYTE:22 [ sin16s::isUpper#10 ] 
-Uplift Scope [mul_u16_sel] 30: zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ] 21: zp ZP_WORD:31 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ] 4: zp ZP_WORD:75 [ mul_u16_sel::return#0 ] 4: zp ZP_WORD:79 [ mul_u16_sel::return#1 ] 4: zp ZP_WORD:83 [ mul_u16_sel::return#10 ] 4: zp ZP_WORD:89 [ mul_u16_sel::return#11 ] 4: zp ZP_WORD:93 [ mul_u16_sel::return#12 ] 4: zp ZP_WORD:97 [ mul_u16_sel::return#13 ] 4: zp ZP_DWORD:109 [ mul_u16_sel::$0 ] 4: zp ZP_DWORD:113 [ mul_u16_sel::$1 ] 1.75: zp ZP_WORD:117 [ mul_u16_sel::return#14 ] 0.33: zp ZP_BYTE:33 [ mul_u16_sel::select#6 ] 
+Uplift Scope [divr16u] 106.92: zp ZP_WORD:46 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] 35.54: zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] 22: zp ZP_BYTE:130 [ divr16u::$1 ] 22: zp ZP_BYTE:131 [ divr16u::$2 ] 18.19: zp ZP_BYTE:52 [ divr16u::i#2 divr16u::i#1 ] 9.75: zp ZP_WORD:48 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] 4: zp ZP_WORD:118 [ divr16u::return#2 ] 4: zp ZP_WORD:122 [ divr16u::return#3 ] 1.38: zp ZP_WORD:44 [ divr16u::divisor#6 ] 
+Uplift Scope [] 191.74: zp ZP_WORD:10 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 ] 0.8: zp ZP_WORD:132 [ rem16u#1 ] 
+Uplift Scope [sin16s] 27.5: zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] 22: zp ZP_WORD:65 [ sin16s::return#0 ] 13: zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] 4: zp ZP_DWORD:69 [ sin16s::$6 ] 4: zp ZP_WORD:77 [ sin16s::x2#0 ] 4: zp ZP_WORD:85 [ sin16s::x3_6#0 ] 4: zp ZP_WORD:91 [ sin16s::x4#0 ] 4: zp ZP_WORD:95 [ sin16s::x5#0 ] 4: zp ZP_WORD:97 [ sin16s::x5_128#0 ] 1: zp ZP_WORD:81 [ sin16s::x3#0 ] 1: zp ZP_WORD:99 [ sin16s::usinx#1 ] 0.64: zp ZP_WORD:73 [ sin16s::x1#0 ] 0.33: zp ZP_WORD:87 [ sin16s::usinx#0 ] 0.06: zp ZP_BYTE:22 [ sin16s::isUpper#2 ] 
+Uplift Scope [mul_u16_sel] 24: zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ] 21: zp ZP_WORD:31 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ] 4: zp ZP_WORD:75 [ mul_u16_sel::return#0 ] 4: zp ZP_WORD:79 [ mul_u16_sel::return#1 ] 4: zp ZP_WORD:83 [ mul_u16_sel::return#2 ] 4: zp ZP_WORD:89 [ mul_u16_sel::return#10 ] 4: zp ZP_WORD:93 [ mul_u16_sel::return#11 ] 4: zp ZP_DWORD:107 [ mul_u16_sel::$0 ] 4: zp ZP_DWORD:111 [ mul_u16_sel::$1 ] 1.71: zp ZP_WORD:115 [ mul_u16_sel::return#12 ] 0.33: zp ZP_BYTE:33 [ mul_u16_sel::select#5 ] 
 Uplift Scope [sin16s_gen] 22: zp ZP_WORD:67 [ sin16s_gen::$1 ] 19.25: zp ZP_WORD:20 [ sin16s_gen::i#2 sin16s_gen::i#1 ] 12.05: zp ZP_DWORD:14 [ sin16s_gen::x#2 sin16s_gen::x#1 ] 11: zp ZP_WORD:18 [ sin16s_gen::sintab#2 sin16s_gen::sintab#1 ] 1.18: zp ZP_DWORD:61 [ sin16s_gen::step#0 ] 
 Uplift Scope [print_cls] 33: zp ZP_WORD:12 [ print_cls::sc#2 print_cls::sc#1 ] 
 Uplift Scope [main] 19.8: zp ZP_WORD:2 [ main::st1#2 main::st1#1 ] 6.6: zp ZP_WORD:53 [ main::sw#0 ] 
 Uplift Scope [print_byte] 10: zp ZP_BYTE:8 [ print_byte::b#2 print_byte::b#0 print_byte::b#1 ] 4: zp ZP_BYTE:55 [ print_byte::$0 ] 4: zp ZP_BYTE:56 [ print_byte::$2 ] 
 Uplift Scope [print_char] 14: zp ZP_BYTE:9 [ print_char::ch#3 print_char::ch#1 print_char::ch#2 ] 
-Uplift Scope [div32u16u] 4: zp ZP_DWORD:57 [ div32u16u::return#0 ] 4: zp ZP_WORD:126 [ div32u16u::quotient_lo#0 ] 1.33: zp ZP_DWORD:128 [ div32u16u::return#1 ] 0.8: zp ZP_WORD:122 [ div32u16u::quotient_hi#0 ] 
+Uplift Scope [div32u16u] 4: zp ZP_DWORD:57 [ div32u16u::return#2 ] 4: zp ZP_WORD:124 [ div32u16u::quotient_lo#0 ] 1.33: zp ZP_DWORD:126 [ div32u16u::return#0 ] 0.8: zp ZP_WORD:120 [ div32u16u::quotient_hi#0 ] 
 Uplift Scope [print_sword] 9.58: zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 ] 
 Uplift Scope [print_word] 
 
-Uplifting [mul16u] best 25149 combination zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] zp ZP_DWORD:40 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] reg byte a [ mul16u::$1 ] zp ZP_WORD:34 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ] zp ZP_WORD:103 [ mul16u::b#0 ] zp ZP_DWORD:105 [ mul16u::return#2 ] 
-Uplifting [print_str] best 25149 combination zp ZP_WORD:4 [ print_str::str#3 print_str::str#5 print_str::str#0 ] 
-Uplifting [divr16u] best 24959 combination zp ZP_WORD:46 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp ZP_WORD:48 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] zp ZP_WORD:120 [ divr16u::return#2 ] zp ZP_WORD:124 [ divr16u::return#3 ] zp ZP_WORD:44 [ divr16u::divisor#6 ] 
-Uplifting [] best 24959 combination zp ZP_WORD:10 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 ] zp ZP_WORD:134 [ rem16u#1 ] 
-Uplifting [sin16s] best 24959 combination zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] zp ZP_WORD:65 [ sin16s::return#0 ] zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] zp ZP_DWORD:69 [ sin16s::$6 ] zp ZP_WORD:77 [ sin16s::x2#0 ] zp ZP_WORD:85 [ sin16s::x3_6#0 ] zp ZP_WORD:91 [ sin16s::x4#0 ] zp ZP_WORD:95 [ sin16s::x5#0 ] zp ZP_WORD:99 [ sin16s::x5_128#0 ] zp ZP_WORD:81 [ sin16s::x3#0 ] zp ZP_WORD:101 [ sin16s::usinx#1 ] zp ZP_WORD:73 [ sin16s::x1#0 ] zp ZP_WORD:87 [ sin16s::usinx#0 ] zp ZP_BYTE:22 [ sin16s::isUpper#10 ] 
-Uplifting [mul_u16_sel] best 24940 combination zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ] zp ZP_WORD:31 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ] zp ZP_WORD:75 [ mul_u16_sel::return#0 ] zp ZP_WORD:79 [ mul_u16_sel::return#1 ] zp ZP_WORD:83 [ mul_u16_sel::return#10 ] zp ZP_WORD:89 [ mul_u16_sel::return#11 ] zp ZP_WORD:93 [ mul_u16_sel::return#12 ] zp ZP_WORD:97 [ mul_u16_sel::return#13 ] zp ZP_DWORD:109 [ mul_u16_sel::$0 ] zp ZP_DWORD:113 [ mul_u16_sel::$1 ] zp ZP_WORD:117 [ mul_u16_sel::return#14 ] reg byte x [ mul_u16_sel::select#6 ] 
-Uplifting [sin16s_gen] best 24940 combination zp ZP_WORD:67 [ sin16s_gen::$1 ] zp ZP_WORD:20 [ sin16s_gen::i#2 sin16s_gen::i#1 ] zp ZP_DWORD:14 [ sin16s_gen::x#2 sin16s_gen::x#1 ] zp ZP_WORD:18 [ sin16s_gen::sintab#2 sin16s_gen::sintab#1 ] zp ZP_DWORD:61 [ sin16s_gen::step#0 ] 
-Uplifting [print_cls] best 24940 combination zp ZP_WORD:12 [ print_cls::sc#2 print_cls::sc#1 ] 
-Uplifting [main] best 24940 combination zp ZP_WORD:2 [ main::st1#2 main::st1#1 ] zp ZP_WORD:53 [ main::sw#0 ] 
-Uplifting [print_byte] best 24928 combination reg byte x [ print_byte::b#2 print_byte::b#0 print_byte::b#1 ] reg byte a [ print_byte::$0 ] reg byte a [ print_byte::$2 ] 
-Uplifting [print_char] best 24916 combination reg byte a [ print_char::ch#3 print_char::ch#1 print_char::ch#2 ] 
-Uplifting [div32u16u] best 24916 combination zp ZP_DWORD:57 [ div32u16u::return#0 ] zp ZP_WORD:126 [ div32u16u::quotient_lo#0 ] zp ZP_DWORD:128 [ div32u16u::return#1 ] zp ZP_WORD:122 [ div32u16u::quotient_hi#0 ] 
-Uplifting [print_sword] best 24916 combination zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 ] 
-Uplifting [print_word] best 24916 combination 
-Attempting to uplift remaining variables inzp ZP_BYTE:22 [ sin16s::isUpper#10 ]
-Uplifting [sin16s] best 24916 combination zp ZP_BYTE:22 [ sin16s::isUpper#10 ] 
-Coalescing zero page register with common assignment [ zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] ] with [ zp ZP_WORD:101 [ sin16s::usinx#1 ] ] - score: 2
-Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ] ] with [ zp ZP_WORD:81 [ sin16s::x3#0 ] ] - score: 2
-Coalescing zero page register with common assignment [ zp ZP_WORD:46 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] ] with [ zp ZP_WORD:134 [ rem16u#1 ] ] - score: 2
+Uplifting [mul16u] best 25117 combination zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] zp ZP_DWORD:40 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] reg byte a [ mul16u::$1 ] zp ZP_WORD:34 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ] zp ZP_WORD:101 [ mul16u::b#0 ] zp ZP_DWORD:103 [ mul16u::return#2 ] 
+Uplifting [print_str] best 25117 combination zp ZP_WORD:4 [ print_str::str#3 print_str::str#5 print_str::str#0 ] 
+Uplifting [divr16u] best 24927 combination zp ZP_WORD:46 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp ZP_WORD:48 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] zp ZP_WORD:118 [ divr16u::return#2 ] zp ZP_WORD:122 [ divr16u::return#3 ] zp ZP_WORD:44 [ divr16u::divisor#6 ] 
+Uplifting [] best 24927 combination zp ZP_WORD:10 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 ] zp ZP_WORD:132 [ rem16u#1 ] 
+Uplifting [sin16s] best 24927 combination zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] zp ZP_WORD:65 [ sin16s::return#0 ] zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] zp ZP_DWORD:69 [ sin16s::$6 ] zp ZP_WORD:77 [ sin16s::x2#0 ] zp ZP_WORD:85 [ sin16s::x3_6#0 ] zp ZP_WORD:91 [ sin16s::x4#0 ] zp ZP_WORD:95 [ sin16s::x5#0 ] zp ZP_WORD:97 [ sin16s::x5_128#0 ] zp ZP_WORD:81 [ sin16s::x3#0 ] zp ZP_WORD:99 [ sin16s::usinx#1 ] zp ZP_WORD:73 [ sin16s::x1#0 ] zp ZP_WORD:87 [ sin16s::usinx#0 ] zp ZP_BYTE:22 [ sin16s::isUpper#2 ] 
+Uplifting [mul_u16_sel] best 24911 combination zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ] zp ZP_WORD:31 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ] zp ZP_WORD:75 [ mul_u16_sel::return#0 ] zp ZP_WORD:79 [ mul_u16_sel::return#1 ] zp ZP_WORD:83 [ mul_u16_sel::return#2 ] zp ZP_WORD:89 [ mul_u16_sel::return#10 ] zp ZP_WORD:93 [ mul_u16_sel::return#11 ] zp ZP_DWORD:107 [ mul_u16_sel::$0 ] zp ZP_DWORD:111 [ mul_u16_sel::$1 ] zp ZP_WORD:115 [ mul_u16_sel::return#12 ] reg byte x [ mul_u16_sel::select#5 ] 
+Uplifting [sin16s_gen] best 24911 combination zp ZP_WORD:67 [ sin16s_gen::$1 ] zp ZP_WORD:20 [ sin16s_gen::i#2 sin16s_gen::i#1 ] zp ZP_DWORD:14 [ sin16s_gen::x#2 sin16s_gen::x#1 ] zp ZP_WORD:18 [ sin16s_gen::sintab#2 sin16s_gen::sintab#1 ] zp ZP_DWORD:61 [ sin16s_gen::step#0 ] 
+Uplifting [print_cls] best 24911 combination zp ZP_WORD:12 [ print_cls::sc#2 print_cls::sc#1 ] 
+Uplifting [main] best 24911 combination zp ZP_WORD:2 [ main::st1#2 main::st1#1 ] zp ZP_WORD:53 [ main::sw#0 ] 
+Uplifting [print_byte] best 24899 combination reg byte x [ print_byte::b#2 print_byte::b#0 print_byte::b#1 ] reg byte a [ print_byte::$0 ] reg byte a [ print_byte::$2 ] 
+Uplifting [print_char] best 24887 combination reg byte a [ print_char::ch#3 print_char::ch#1 print_char::ch#2 ] 
+Uplifting [div32u16u] best 24887 combination zp ZP_DWORD:57 [ div32u16u::return#2 ] zp ZP_WORD:124 [ div32u16u::quotient_lo#0 ] zp ZP_DWORD:126 [ div32u16u::return#0 ] zp ZP_WORD:120 [ div32u16u::quotient_hi#0 ] 
+Uplifting [print_sword] best 24887 combination zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 ] 
+Uplifting [print_word] best 24887 combination 
+Attempting to uplift remaining variables inzp ZP_BYTE:22 [ sin16s::isUpper#2 ]
+Uplifting [sin16s] best 24887 combination zp ZP_BYTE:22 [ sin16s::isUpper#2 ] 
+Coalescing zero page register with common assignment [ zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] ] with [ zp ZP_WORD:99 [ sin16s::usinx#1 ] ] - score: 2
+Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 ] ] with [ zp ZP_WORD:81 [ sin16s::x3#0 ] ] - score: 2
+Coalescing zero page register with common assignment [ zp ZP_WORD:46 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] ] with [ zp ZP_WORD:132 [ rem16u#1 ] ] - score: 2
 Coalescing zero page register with common assignment [ zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 ] ] with [ zp ZP_WORD:53 [ main::sw#0 ] ] - score: 1
 Coalescing zero page register with common assignment [ zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] ] with [ zp ZP_DWORD:69 [ sin16s::$6 ] ] - score: 1
 Coalescing zero page register with common assignment [ zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 ] ] with [ zp ZP_WORD:65 [ sin16s::return#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 ] ] with [ zp ZP_WORD:77 [ sin16s::x2#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 ] ] with [ zp ZP_WORD:91 [ sin16s::x4#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 ] ] with [ zp ZP_WORD:95 [ sin16s::x5#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:31 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ] ] with [ zp ZP_WORD:103 [ mul16u::b#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] ] with [ zp ZP_DWORD:105 [ mul16u::return#2 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] ] with [ zp ZP_WORD:120 [ divr16u::return#2 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 ] ] with [ zp ZP_WORD:124 [ divr16u::return#3 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_DWORD:57 [ div32u16u::return#0 ] ] with [ zp ZP_DWORD:61 [ sin16s_gen::step#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_DWORD:57 [ div32u16u::return#0 sin16s_gen::step#0 ] ] with [ zp ZP_DWORD:128 [ div32u16u::return#1 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:75 [ mul_u16_sel::return#0 ] ] with [ zp ZP_WORD:117 [ mul_u16_sel::return#14 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:83 [ mul_u16_sel::return#10 ] ] with [ zp ZP_WORD:85 [ sin16s::x3_6#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:97 [ mul_u16_sel::return#13 ] ] with [ zp ZP_WORD:99 [ sin16s::x5_128#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_DWORD:109 [ mul_u16_sel::$0 ] ] with [ zp ZP_DWORD:113 [ mul_u16_sel::$1 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 ] ] with [ zp ZP_WORD:77 [ sin16s::x2#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 ] ] with [ zp ZP_WORD:91 [ sin16s::x4#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:31 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 ] ] with [ zp ZP_WORD:101 [ mul16u::b#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] ] with [ zp ZP_DWORD:103 [ mul16u::return#2 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] ] with [ zp ZP_WORD:118 [ divr16u::return#2 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 ] ] with [ zp ZP_WORD:122 [ divr16u::return#3 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_DWORD:57 [ div32u16u::return#2 ] ] with [ zp ZP_DWORD:61 [ sin16s_gen::step#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_DWORD:57 [ div32u16u::return#2 sin16s_gen::step#0 ] ] with [ zp ZP_DWORD:126 [ div32u16u::return#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:75 [ mul_u16_sel::return#0 ] ] with [ zp ZP_WORD:115 [ mul_u16_sel::return#12 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:83 [ mul_u16_sel::return#2 ] ] with [ zp ZP_WORD:85 [ sin16s::x3_6#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:93 [ mul_u16_sel::return#11 ] ] with [ zp ZP_WORD:95 [ sin16s::x5#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_DWORD:107 [ mul_u16_sel::$0 ] ] with [ zp ZP_DWORD:111 [ mul_u16_sel::$1 ] ] - score: 1
 Coalescing zero page register with common assignment [ zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 ] ] with [ zp ZP_WORD:67 [ sin16s_gen::$1 ] ] - score: 1
 Coalescing zero page register with common assignment [ zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 sin16s_gen::$1 ] ] with [ zp ZP_WORD:87 [ sin16s::usinx#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 sin16s::x5#0 ] ] with [ zp ZP_WORD:79 [ mul_u16_sel::return#1 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 sin16s::x5#0 mul_u16_sel::return#1 ] ] with [ zp ZP_WORD:89 [ mul_u16_sel::return#11 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 sin16s::x5#0 mul_u16_sel::return#1 mul_u16_sel::return#11 ] ] with [ zp ZP_WORD:93 [ mul_u16_sel::return#12 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#2 ] ] with [ zp ZP_DWORD:109 [ mul_u16_sel::$0 mul_u16_sel::$1 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 ] ] with [ zp ZP_WORD:126 [ div32u16u::quotient_lo#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:75 [ mul_u16_sel::return#0 mul_u16_sel::return#14 ] ] with [ zp ZP_WORD:83 [ mul_u16_sel::return#10 sin16s::x3_6#0 ] ] - score: 1
-Coalescing zero page register with common assignment [ zp ZP_WORD:75 [ mul_u16_sel::return#0 mul_u16_sel::return#14 mul_u16_sel::return#10 sin16s::x3_6#0 ] ] with [ zp ZP_WORD:97 [ mul_u16_sel::return#13 sin16s::x5_128#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 ] ] with [ zp ZP_WORD:79 [ mul_u16_sel::return#1 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mul_u16_sel::return#1 ] ] with [ zp ZP_WORD:89 [ mul_u16_sel::return#10 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#2 ] ] with [ zp ZP_DWORD:107 [ mul_u16_sel::$0 mul_u16_sel::$1 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 ] ] with [ zp ZP_WORD:124 [ div32u16u::quotient_lo#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:75 [ mul_u16_sel::return#0 mul_u16_sel::return#12 ] ] with [ zp ZP_WORD:83 [ mul_u16_sel::return#2 sin16s::x3_6#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:75 [ mul_u16_sel::return#0 mul_u16_sel::return#12 mul_u16_sel::return#2 sin16s::x3_6#0 ] ] with [ zp ZP_WORD:93 [ mul_u16_sel::return#11 sin16s::x5#0 ] ] - score: 1
+Coalescing zero page register with common assignment [ zp ZP_WORD:75 [ mul_u16_sel::return#0 mul_u16_sel::return#12 mul_u16_sel::return#2 sin16s::x3_6#0 mul_u16_sel::return#11 sin16s::x5#0 ] ] with [ zp ZP_WORD:97 [ sin16s::x5_128#0 ] ] - score: 1
 Coalescing zero page register [ zp ZP_WORD:2 [ main::st1#2 main::st1#1 ] ] with [ zp ZP_WORD:12 [ print_cls::sc#2 print_cls::sc#1 ] ]
 Coalescing zero page register [ zp ZP_WORD:2 [ main::st1#2 main::st1#1 print_cls::sc#2 print_cls::sc#1 ] ] with [ zp ZP_WORD:18 [ sin16s_gen::sintab#2 sin16s_gen::sintab#1 ] ]
 Coalescing zero page register [ zp ZP_WORD:2 [ main::st1#2 main::st1#1 print_cls::sc#2 print_cls::sc#1 sin16s_gen::sintab#2 sin16s_gen::sintab#1 ] ] with [ zp ZP_WORD:44 [ divr16u::divisor#6 ] ]
@@ -7041,19 +6932,19 @@ Coalescing zero page register [ zp ZP_WORD:4 [ print_str::str#3 print_str::str#5
 Coalescing zero page register [ zp ZP_WORD:4 [ print_str::str#3 print_str::str#5 print_str::str#0 sin16s_gen::i#2 sin16s_gen::i#1 ] ] with [ zp ZP_WORD:46 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 rem16u#1 ] ]
 Coalescing zero page register [ zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 main::sw#0 ] ] with [ zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 sin16s_gen::$1 sin16s::usinx#0 ] ]
 Coalescing zero page register [ zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 main::sw#0 sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 sin16s_gen::$1 sin16s::usinx#0 ] ] with [ zp ZP_WORD:48 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] ]
-Coalescing zero page register [ zp ZP_WORD:10 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 ] ] with [ zp ZP_WORD:29 [ mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 sin16s::x5#0 mul_u16_sel::return#1 mul_u16_sel::return#11 mul_u16_sel::return#12 ] ]
-Coalescing zero page register [ zp ZP_WORD:10 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 sin16s::x5#0 mul_u16_sel::return#1 mul_u16_sel::return#11 mul_u16_sel::return#12 ] ] with [ zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ] ]
+Coalescing zero page register [ zp ZP_WORD:10 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 ] ] with [ zp ZP_WORD:29 [ mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mul_u16_sel::return#1 mul_u16_sel::return#10 ] ]
+Coalescing zero page register [ zp ZP_WORD:10 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mul_u16_sel::return#1 mul_u16_sel::return#10 ] ] with [ zp ZP_WORD:50 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ] ]
 Coalescing zero page register [ zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 sin16s::$6 ] ] with [ zp ZP_DWORD:36 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#2 mul_u16_sel::$0 mul_u16_sel::$1 ] ]
-Coalescing zero page register [ zp ZP_WORD:31 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 ] ] with [ zp ZP_WORD:75 [ mul_u16_sel::return#0 mul_u16_sel::return#14 mul_u16_sel::return#10 sin16s::x3_6#0 mul_u16_sel::return#13 sin16s::x5_128#0 ] ]
-Coalescing zero page register [ zp ZP_WORD:31 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 mul_u16_sel::return#0 mul_u16_sel::return#14 mul_u16_sel::return#10 sin16s::x3_6#0 mul_u16_sel::return#13 sin16s::x5_128#0 ] ] with [ zp ZP_WORD:122 [ div32u16u::quotient_hi#0 ] ]
-Allocated (was zp ZP_WORD:10) zp ZP_WORD:8 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 sin16s::x5#0 mul_u16_sel::return#1 mul_u16_sel::return#11 mul_u16_sel::return#12 divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ]
+Coalescing zero page register [ zp ZP_WORD:31 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 ] ] with [ zp ZP_WORD:75 [ mul_u16_sel::return#0 mul_u16_sel::return#12 mul_u16_sel::return#2 sin16s::x3_6#0 mul_u16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 ] ]
+Coalescing zero page register [ zp ZP_WORD:31 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 mul_u16_sel::return#0 mul_u16_sel::return#12 mul_u16_sel::return#2 sin16s::x3_6#0 mul_u16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 ] ] with [ zp ZP_WORD:120 [ div32u16u::quotient_hi#0 ] ]
+Allocated (was zp ZP_WORD:10) zp ZP_WORD:8 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mul_u16_sel::return#1 mul_u16_sel::return#10 divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ]
 Allocated (was zp ZP_DWORD:14) zp ZP_DWORD:10 [ sin16s_gen::x#2 sin16s_gen::x#1 ]
-Allocated (was zp ZP_BYTE:22) zp ZP_BYTE:14 [ sin16s::isUpper#10 ]
+Allocated (was zp ZP_BYTE:22) zp ZP_BYTE:14 [ sin16s::isUpper#2 ]
 Allocated (was zp ZP_DWORD:23) zp ZP_DWORD:15 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 sin16s::$6 mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#2 mul_u16_sel::$0 mul_u16_sel::$1 ]
-Allocated (was zp ZP_WORD:31) zp ZP_WORD:19 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 mul_u16_sel::return#0 mul_u16_sel::return#14 mul_u16_sel::return#10 sin16s::x3_6#0 mul_u16_sel::return#13 sin16s::x5_128#0 div32u16u::quotient_hi#0 ]
+Allocated (was zp ZP_WORD:31) zp ZP_WORD:19 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 mul_u16_sel::return#0 mul_u16_sel::return#12 mul_u16_sel::return#2 sin16s::x3_6#0 mul_u16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 div32u16u::quotient_hi#0 ]
 Allocated (was zp ZP_WORD:34) zp ZP_WORD:21 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ]
 Allocated (was zp ZP_DWORD:40) zp ZP_DWORD:23 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
-Allocated (was zp ZP_DWORD:57) zp ZP_DWORD:27 [ div32u16u::return#0 sin16s_gen::step#0 div32u16u::return#1 ]
+Allocated (was zp ZP_DWORD:57) zp ZP_DWORD:27 [ div32u16u::return#2 sin16s_gen::step#0 div32u16u::return#0 ]
 Allocated (was zp ZP_WORD:73) zp ZP_WORD:31 [ sin16s::x1#0 ]
 
 ASSEMBLER BEFORE OPTIMIZATION
@@ -7419,17 +7310,17 @@ sin16s_gen: {
     .label sintab = 2
     .label x = $a
     .label i = 4
-  //SEG123 [59] call div32u16u param-assignment [ div32u16u::return#1 ] ( main:2::sin16s_gen:5 [ div32u16u::return#1 ] )
-  //SEG124 [135] phi from sin16s_gen to div32u16u [phi:sin16s_gen->div32u16u]
+  //SEG123 [59] call div32u16u param-assignment [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
+  //SEG124 [132] phi from sin16s_gen to div32u16u [phi:sin16s_gen->div32u16u]
   div32u16u_from_sin16s_gen:
     jsr div32u16u
-  //SEG125 [60] (dword) div32u16u::return#0 ← (dword) div32u16u::return#1 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
-    // (dword) div32u16u::return#0 = (dword) div32u16u::return#1  // register copy zp ZP_DWORD:27
+  //SEG125 [60] (dword) div32u16u::return#2 ← (dword) div32u16u::return#0 [ div32u16u::return#2 ] ( main:2::sin16s_gen:5 [ div32u16u::return#2 ] )
+    // (dword) div32u16u::return#2 = (dword) div32u16u::return#0  // register copy zp ZP_DWORD:27
     jmp b3
   //SEG126 sin16s_gen::@3
   b3:
-  //SEG127 [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#0 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] )
-    // (dword) sin16s_gen::step#0 = (dword) div32u16u::return#0  // register copy zp ZP_DWORD:27
+  //SEG127 [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#2 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] )
+    // (dword) sin16s_gen::step#0 = (dword) div32u16u::return#2  // register copy zp ZP_DWORD:27
   //SEG128 [62] phi from sin16s_gen::@3 to sin16s_gen::@1 [phi:sin16s_gen::@3->sin16s_gen::@1]
   b1_from_b3:
   //SEG129 [62] phi (word) sin16s_gen::i#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s_gen::@3->sin16s_gen::@1#0] -- vwuz1=vbuc1 
@@ -7536,7 +7427,7 @@ sin16s: {
     .label x3_6 = $13
     .label usinx = 6
     .label x4 = 8
-    .label x5 = 8
+    .label x5 = $13
     .label x5_128 = $13
     .label sinx = 6
     .label isUpper = $e
@@ -7576,21 +7467,21 @@ sin16s: {
     sta x+3
   //SEG153 [75] phi from sin16s::@4 to sin16s::@1 [phi:sin16s::@4->sin16s::@1]
   b1_from_b4:
-  //SEG154 [75] phi (byte) sin16s::isUpper#10 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@4->sin16s::@1#0] -- vbuz1=vbuc1 
+  //SEG154 [75] phi (byte) sin16s::isUpper#2 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@4->sin16s::@1#0] -- vbuz1=vbuc1 
     lda #1
     sta isUpper
   //SEG155 [75] phi (dword) sin16s::x#4 = (dword) sin16s::x#1 [phi:sin16s::@4->sin16s::@1#1] -- register_copy 
     jmp b1
   //SEG156 [75] phi from sin16s to sin16s::@1 [phi:sin16s->sin16s::@1]
   b1_from_sin16s:
-  //SEG157 [75] phi (byte) sin16s::isUpper#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s->sin16s::@1#0] -- vbuz1=vbuc1 
+  //SEG157 [75] phi (byte) sin16s::isUpper#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s->sin16s::@1#0] -- vbuz1=vbuc1 
     lda #0
     sta isUpper
   //SEG158 [75] phi (dword) sin16s::x#4 = (dword) sin16s::x#0 [phi:sin16s->sin16s::@1#1] -- register_copy 
     jmp b1
   //SEG159 sin16s::@1
   b1:
-  //SEG160 [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] ) -- vduz1_lt_vduc1_then_la1 
+  //SEG160 [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] ) -- vduz1_lt_vduc1_then_la1 
     lda x+3
     cmp #>PI_HALF_u4f28>>$10
     bcc b2_from_b1
@@ -7610,7 +7501,7 @@ sin16s: {
     jmp b5
   //SEG161 sin16s::@5
   b5:
-  //SEG162 [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#10 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#2 ] ) -- vduz1=vduc1_minus_vduz1 
+  //SEG162 [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#2 ] ) -- vduz1=vduc1_minus_vduz1 
     lda #<PI_u4f28
     sec
     sbc x
@@ -7631,7 +7522,7 @@ sin16s: {
     jmp b2
   //SEG165 sin16s::@2
   b2:
-  //SEG166 [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#10 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::$6 ] ) -- vduz1=vduz1_rol_3 
+  //SEG166 [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#2 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::$6 ] ) -- vduz1=vduz1_rol_3 
     ldy #3
   !:
     asl _6
@@ -7640,55 +7531,55 @@ sin16s: {
     rol _6+3
     dey
     bne !-
-  //SEG167 [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#10 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 ] ) -- vwuz1=_hi_vduz2 
+  //SEG167 [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 ] ) -- vwuz1=_hi_vduz2 
     lda _6+2
     sta x1
     lda _6+3
     sta x1+1
-  //SEG168 [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ) -- vwuz1=vwuz2 
+  //SEG168 [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v1
     lda x1+1
     sta mul_u16_sel.v1+1
-  //SEG169 [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) -- vwuz1=vwuz2 
+  //SEG169 [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG170 [83] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  //SEG171 [116] phi from sin16s::@2 to mul_u16_sel [phi:sin16s::@2->mul_u16_sel]
+  //SEG170 [83] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  //SEG171 [113] phi from sin16s::@2 to mul_u16_sel [phi:sin16s::@2->mul_u16_sel]
   mul_u16_sel_from_b2:
-  //SEG172 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@2->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG172 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@2->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #0
-  //SEG173 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#0 [phi:sin16s::@2->mul_u16_sel#1] -- register_copy 
-  //SEG174 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#0 [phi:sin16s::@2->mul_u16_sel#2] -- register_copy 
+  //SEG173 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#0 [phi:sin16s::@2->mul_u16_sel#1] -- register_copy 
+  //SEG174 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#0 [phi:sin16s::@2->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG175 [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] )
-    // (word) mul_u16_sel::return#0 = (word) mul_u16_sel::return#14  // register copy zp ZP_WORD:19
+  //SEG175 [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] )
+    // (word) mul_u16_sel::return#0 = (word) mul_u16_sel::return#12  // register copy zp ZP_WORD:19
     jmp b8
   //SEG176 sin16s::@8
   b8:
-  //SEG177 [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ) -- vwuz1=vwuz2 
+  //SEG177 [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ) -- vwuz1=vwuz2 
     lda mul_u16_sel.return
     sta x2
     lda mul_u16_sel.return+1
     sta x2+1
-  //SEG178 [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] )
+  //SEG178 [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] )
     // (word) mul_u16_sel::v1#1 = (word) sin16s::x2#0  // register copy zp ZP_WORD:8
-  //SEG179 [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) -- vwuz1=vwuz2 
+  //SEG179 [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG180 [88] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  //SEG181 [116] phi from sin16s::@8 to mul_u16_sel [phi:sin16s::@8->mul_u16_sel]
+  //SEG180 [88] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  //SEG181 [113] phi from sin16s::@8 to mul_u16_sel [phi:sin16s::@8->mul_u16_sel]
   mul_u16_sel_from_b8:
-  //SEG182 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@8->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG182 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@8->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #1
-  //SEG183 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#1 [phi:sin16s::@8->mul_u16_sel#1] -- register_copy 
-  //SEG184 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#1 [phi:sin16s::@8->mul_u16_sel#2] -- register_copy 
+  //SEG183 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#1 [phi:sin16s::@8->mul_u16_sel#1] -- register_copy 
+  //SEG184 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#1 [phi:sin16s::@8->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG185 [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ) -- vwuz1=vwuz2 
+  //SEG185 [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ) -- vwuz1=vwuz2 
     lda mul_u16_sel.return
     sta mul_u16_sel.return_1
     lda mul_u16_sel.return+1
@@ -7696,30 +7587,30 @@ sin16s: {
     jmp b9
   //SEG186 sin16s::@9
   b9:
-  //SEG187 [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] )
+  //SEG187 [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] )
     // (word) sin16s::x3#0 = (word) mul_u16_sel::return#1  // register copy zp ZP_WORD:8
-  //SEG188 [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] )
+  //SEG188 [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] )
     // (word) mul_u16_sel::v1#2 = (word) sin16s::x3#0  // register copy zp ZP_WORD:8
-  //SEG189 [92] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] )
-  //SEG190 [116] phi from sin16s::@9 to mul_u16_sel [phi:sin16s::@9->mul_u16_sel]
+  //SEG189 [92] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] )
+  //SEG190 [113] phi from sin16s::@9 to mul_u16_sel [phi:sin16s::@9->mul_u16_sel]
   mul_u16_sel_from_b9:
-  //SEG191 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@9->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG191 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@9->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #1
-  //SEG192 [116] phi (word) mul_u16_sel::v2#6 = (dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 [phi:sin16s::@9->mul_u16_sel#1] -- vwuz1=vwuc1 
+  //SEG192 [113] phi (word) mul_u16_sel::v2#5 = (dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 [phi:sin16s::@9->mul_u16_sel#1] -- vwuz1=vwuc1 
     lda #<$10000/6
     sta mul_u16_sel.v2
     lda #>$10000/6
     sta mul_u16_sel.v2+1
-  //SEG193 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#2 [phi:sin16s::@9->mul_u16_sel#2] -- register_copy 
+  //SEG193 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#2 [phi:sin16s::@9->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG194 [93] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] )
-    // (word) mul_u16_sel::return#10 = (word) mul_u16_sel::return#14  // register copy zp ZP_WORD:19
+  //SEG194 [93] (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] )
+    // (word) mul_u16_sel::return#2 = (word) mul_u16_sel::return#12  // register copy zp ZP_WORD:19
     jmp b10
   //SEG195 sin16s::@10
   b10:
-  //SEG196 [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] )
-    // (word) sin16s::x3_6#0 = (word) mul_u16_sel::return#10  // register copy zp ZP_WORD:19
-  //SEG197 [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) -- vwuz1=vwuz2_minus_vwuz3 
+  //SEG196 [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] )
+    // (word) sin16s::x3_6#0 = (word) mul_u16_sel::return#2  // register copy zp ZP_WORD:19
+  //SEG197 [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) -- vwuz1=vwuz2_minus_vwuz3 
     lda x1
     sec
     sbc x3_6
@@ -7727,78 +7618,61 @@ sin16s: {
     lda x1+1
     sbc x3_6+1
     sta usinx+1
-  //SEG198 [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] )
+  //SEG198 [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] )
     // (word) mul_u16_sel::v1#3 = (word) sin16s::x3#0  // register copy zp ZP_WORD:8
-  //SEG199 [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) -- vwuz1=vwuz2 
+  //SEG199 [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG200 [98] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG201 [116] phi from sin16s::@10 to mul_u16_sel [phi:sin16s::@10->mul_u16_sel]
+  //SEG200 [98] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  //SEG201 [113] phi from sin16s::@10 to mul_u16_sel [phi:sin16s::@10->mul_u16_sel]
   mul_u16_sel_from_b10:
-  //SEG202 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@10->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG202 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@10->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #0
-  //SEG203 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#3 [phi:sin16s::@10->mul_u16_sel#1] -- register_copy 
-  //SEG204 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#3 [phi:sin16s::@10->mul_u16_sel#2] -- register_copy 
+  //SEG203 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#3 [phi:sin16s::@10->mul_u16_sel#1] -- register_copy 
+  //SEG204 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#3 [phi:sin16s::@10->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG205 [99] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ) -- vwuz1=vwuz2 
+  //SEG205 [99] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ) -- vwuz1=vwuz2 
     lda mul_u16_sel.return
-    sta mul_u16_sel.return_11
+    sta mul_u16_sel.return_10
     lda mul_u16_sel.return+1
-    sta mul_u16_sel.return_11+1
+    sta mul_u16_sel.return_10+1
     jmp b11
   //SEG206 sin16s::@11
   b11:
-  //SEG207 [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] )
-    // (word) sin16s::x4#0 = (word) mul_u16_sel::return#11  // register copy zp ZP_WORD:8
-  //SEG208 [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] )
+  //SEG207 [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] )
+    // (word) sin16s::x4#0 = (word) mul_u16_sel::return#10  // register copy zp ZP_WORD:8
+  //SEG208 [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] )
     // (word) mul_u16_sel::v1#4 = (word) sin16s::x4#0  // register copy zp ZP_WORD:8
-  //SEG209 [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) -- vwuz1=vwuz2 
+  //SEG209 [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG210 [103] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG211 [116] phi from sin16s::@11 to mul_u16_sel [phi:sin16s::@11->mul_u16_sel]
+  //SEG210 [103] call mul_u16_sel param-assignment [ sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  //SEG211 [113] phi from sin16s::@11 to mul_u16_sel [phi:sin16s::@11->mul_u16_sel]
   mul_u16_sel_from_b11:
-  //SEG212 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@11->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG212 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@11->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #0
-  //SEG213 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#4 [phi:sin16s::@11->mul_u16_sel#1] -- register_copy 
-  //SEG214 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#4 [phi:sin16s::@11->mul_u16_sel#2] -- register_copy 
+  //SEG213 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#4 [phi:sin16s::@11->mul_u16_sel#1] -- register_copy 
+  //SEG214 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#4 [phi:sin16s::@11->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG215 [104] (word) mul_u16_sel::return#12 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return
-    sta mul_u16_sel.return_12
-    lda mul_u16_sel.return+1
-    sta mul_u16_sel.return_12+1
+  //SEG215 [104] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] )
+    // (word) mul_u16_sel::return#11 = (word) mul_u16_sel::return#12  // register copy zp ZP_WORD:19
     jmp b12
   //SEG216 sin16s::@12
   b12:
-  //SEG217 [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] )
-    // (word) sin16s::x5#0 = (word) mul_u16_sel::return#12  // register copy zp ZP_WORD:8
-  //SEG218 [106] (word) mul_u16_sel::v1#5 ← (word) sin16s::x5#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] )
-    // (word) mul_u16_sel::v1#5 = (word) sin16s::x5#0  // register copy zp ZP_WORD:8
-  //SEG219 [107] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG220 [116] phi from sin16s::@12 to mul_u16_sel [phi:sin16s::@12->mul_u16_sel]
-  mul_u16_sel_from_b12:
-  //SEG221 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 3 [phi:sin16s::@12->mul_u16_sel#0] -- vbuxx=vbuc1 
-    ldx #3
-  //SEG222 [116] phi (word) mul_u16_sel::v2#6 = (dword/signed dword) 65536/(byte/word/signed word/dword/signed dword) 128 [phi:sin16s::@12->mul_u16_sel#1] -- vwuz1=vwuc1 
-    lda #<$10000/$80
-    sta mul_u16_sel.v2
-    lda #>$10000/$80
-    sta mul_u16_sel.v2+1
-  //SEG223 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#5 [phi:sin16s::@12->mul_u16_sel#2] -- register_copy 
-    jsr mul_u16_sel
-  //SEG224 [108] (word) mul_u16_sel::return#13 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] )
-    // (word) mul_u16_sel::return#13 = (word) mul_u16_sel::return#14  // register copy zp ZP_WORD:19
-    jmp b13
-  //SEG225 sin16s::@13
-  b13:
-  //SEG226 [109] (word) sin16s::x5_128#0 ← (word) mul_u16_sel::return#13 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] )
-    // (word) sin16s::x5_128#0 = (word) mul_u16_sel::return#13  // register copy zp ZP_WORD:19
-  //SEG227 [110] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#10 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#1 ] ) -- vwuz1=vwuz1_plus_vwuz2 
+  //SEG217 [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] )
+    // (word) sin16s::x5#0 = (word) mul_u16_sel::return#11  // register copy zp ZP_WORD:19
+  //SEG218 [106] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) -- vwuz1=vwuz1_ror_4 
+    ldy #4
+  !:
+    lsr x5_128+1
+    ror x5_128
+    dey
+    bne !-
+  //SEG219 [107] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) -- vwuz1=vwuz1_plus_vwuz2 
     lda usinx
     clc
     adc x5_128
@@ -7806,13 +7680,13 @@ sin16s: {
     lda usinx+1
     adc x5_128+1
     sta usinx+1
-  //SEG228 [111] if((byte) sin16s::isUpper#10==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@16 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) -- vbuz1_eq_0_then_la1 
+  //SEG220 [108] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) -- vbuz1_eq_0_then_la1 
     lda isUpper
-    beq b16
+    beq b15
     jmp b6
-  //SEG229 sin16s::@6
+  //SEG221 sin16s::@6
   b6:
-  //SEG230 [112] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) -- vwsz1=_neg_vwsz1 
+  //SEG222 [109] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) -- vwsz1=_neg_vwsz1 
     sec
     lda sinx
     eor #$ff
@@ -7822,25 +7696,25 @@ sin16s: {
     eor #$ff
     adc #0
     sta sinx+1
-  //SEG231 [113] phi from sin16s::@16 sin16s::@6 to sin16s::@3 [phi:sin16s::@16/sin16s::@6->sin16s::@3]
-  b3_from_b16:
+  //SEG223 [110] phi from sin16s::@15 sin16s::@6 to sin16s::@3 [phi:sin16s::@15/sin16s::@6->sin16s::@3]
+  b3_from_b15:
   b3_from_b6:
-  //SEG232 [113] phi (signed word) sin16s::return#1 = (signed word~) sin16s::return#5 [phi:sin16s::@16/sin16s::@6->sin16s::@3#0] -- register_copy 
+  //SEG224 [110] phi (signed word) sin16s::return#1 = (signed word~) sin16s::return#5 [phi:sin16s::@15/sin16s::@6->sin16s::@3#0] -- register_copy 
     jmp b3
-  //SEG233 sin16s::@3
+  //SEG225 sin16s::@3
   b3:
     jmp breturn
-  //SEG234 sin16s::@return
+  //SEG226 sin16s::@return
   breturn:
-  //SEG235 [114] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
+  //SEG227 [111] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
     rts
-  //SEG236 sin16s::@16
-  b16:
-  //SEG237 [115] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] )
+  //SEG228 sin16s::@15
+  b15:
+  //SEG229 [112] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] )
     // (signed word~) sin16s::return#5 = (signed word)(word) sin16s::usinx#1  // register copy zp ZP_WORD:6
-    jmp b3_from_b16
+    jmp b3_from_b15
 }
-//SEG238 mul_u16_sel
+//SEG230 mul_u16_sel
 mul_u16_sel: {
     .label _0 = $f
     .label _1 = $f
@@ -7848,25 +7722,24 @@ mul_u16_sel: {
     .label v2 = $13
     .label return = $13
     .label return_1 = 8
-    .label return_11 = 8
-    .label return_12 = 8
-  //SEG239 [117] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#6 [ mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ) -- vwuz1=vwuz2 
+    .label return_10 = 8
+  //SEG231 [114] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#5 [ mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ) -- vwuz1=vwuz2 
     lda v1
     sta mul16u.a
     lda v1+1
     sta mul16u.a+1
-  //SEG240 [118] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#6 [ mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] )
-    // (word) mul16u::b#0 = (word) mul_u16_sel::v2#6  // register copy zp ZP_WORD:19
-  //SEG241 [119] call mul16u param-assignment [ mul_u16_sel::select#6 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
+  //SEG232 [115] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#5 [ mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] )
+    // (word) mul16u::b#0 = (word) mul_u16_sel::v2#5  // register copy zp ZP_WORD:19
+  //SEG233 [116] call mul16u param-assignment [ mul_u16_sel::select#5 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
     jsr mul16u
-  //SEG242 [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#6 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] )
+  //SEG234 [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] )
     // (dword) mul16u::return#2 = (dword) mul16u::res#2  // register copy zp ZP_DWORD:15
     jmp b2
-  //SEG243 mul_u16_sel::@2
+  //SEG235 mul_u16_sel::@2
   b2:
-  //SEG244 [121] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#6 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] )
+  //SEG236 [118] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#5 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] )
     // (dword~) mul_u16_sel::$0 = (dword) mul16u::return#2  // register copy zp ZP_DWORD:15
-  //SEG245 [122] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#6 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] ) -- vduz1=vduz1_rol_vbuxx 
+  //SEG237 [119] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#5 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::$1 ] ) -- vduz1=vduz1_rol_vbuxx 
     cpx #0
     beq !e+
   !:
@@ -7877,25 +7750,25 @@ mul_u16_sel: {
     dex
     bne !-
   !e:
-  //SEG246 [123] (word) mul_u16_sel::return#14 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] ) -- vwuz1=_hi_vduz2 
+  //SEG238 [120] (word) mul_u16_sel::return#12 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] ) -- vwuz1=_hi_vduz2 
     lda _1+2
     sta return
     lda _1+3
     sta return+1
     jmp breturn
-  //SEG247 mul_u16_sel::@return
+  //SEG239 mul_u16_sel::@return
   breturn:
-  //SEG248 [124] return  [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] )
+  //SEG240 [121] return  [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] )
     rts
 }
-//SEG249 mul16u
+//SEG241 mul16u
 mul16u: {
     .label mb = $17
     .label a = $15
     .label res = $f
     .label b = $13
     .label return = $f
-  //SEG250 [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] ) -- vduz1=_dword_vwuz2 
+  //SEG242 [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) -- vduz1=_dword_vwuz2 
     lda b
     sta mb
     lda b+1
@@ -7903,42 +7776,42 @@ mul16u: {
     lda #0
     sta mb+2
     sta mb+3
-  //SEG251 [126] phi from mul16u to mul16u::@1 [phi:mul16u->mul16u::@1]
+  //SEG243 [123] phi from mul16u to mul16u::@1 [phi:mul16u->mul16u::@1]
   b1_from_mul16u:
-  //SEG252 [126] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#0 [phi:mul16u->mul16u::@1#0] -- register_copy 
-  //SEG253 [126] phi (dword) mul16u::res#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:mul16u->mul16u::@1#1] -- vduz1=vbuc1 
+  //SEG244 [123] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#0 [phi:mul16u->mul16u::@1#0] -- register_copy 
+  //SEG245 [123] phi (dword) mul16u::res#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:mul16u->mul16u::@1#1] -- vduz1=vbuc1 
     lda #0
     sta res
     lda #0
     sta res+1
     sta res+2
     sta res+3
-  //SEG254 [126] phi (word) mul16u::a#2 = (word) mul16u::a#1 [phi:mul16u->mul16u::@1#2] -- register_copy 
+  //SEG246 [123] phi (word) mul16u::a#2 = (word) mul16u::a#1 [phi:mul16u->mul16u::@1#2] -- register_copy 
     jmp b1
-  //SEG255 mul16u::@1
+  //SEG247 mul16u::@1
   b1:
-  //SEG256 [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vwuz1_neq_0_then_la1 
+  //SEG248 [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vwuz1_neq_0_then_la1 
     lda a
     bne b2
     lda a+1
     bne b2
     jmp breturn
-  //SEG257 mul16u::@return
+  //SEG249 mul16u::@return
   breturn:
-  //SEG258 [128] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
+  //SEG250 [125] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
     rts
-  //SEG259 mul16u::@2
+  //SEG251 mul16u::@2
   b2:
-  //SEG260 [129] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) -- vbuaa=vwuz1_band_vbuc1 
+  //SEG252 [126] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) -- vbuaa=vwuz1_band_vbuc1 
     lda a
     and #1
-  //SEG261 [130] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vbuaa_eq_0_then_la1 
+  //SEG253 [127] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vbuaa_eq_0_then_la1 
     cmp #0
     beq b4_from_b2
     jmp b7
-  //SEG262 mul16u::@7
+  //SEG254 mul16u::@7
   b7:
-  //SEG263 [131] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) -- vduz1=vduz1_plus_vduz2 
+  //SEG255 [128] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) -- vduz1=vduz1_plus_vduz2 
     lda res
     clc
     adc mb
@@ -7952,88 +7825,88 @@ mul16u: {
     lda res+3
     adc mb+3
     sta res+3
-  //SEG264 [132] phi from mul16u::@2 mul16u::@7 to mul16u::@4 [phi:mul16u::@2/mul16u::@7->mul16u::@4]
+  //SEG256 [129] phi from mul16u::@2 mul16u::@7 to mul16u::@4 [phi:mul16u::@2/mul16u::@7->mul16u::@4]
   b4_from_b2:
   b4_from_b7:
-  //SEG265 [132] phi (dword) mul16u::res#6 = (dword) mul16u::res#2 [phi:mul16u::@2/mul16u::@7->mul16u::@4#0] -- register_copy 
+  //SEG257 [129] phi (dword) mul16u::res#6 = (dword) mul16u::res#2 [phi:mul16u::@2/mul16u::@7->mul16u::@4#0] -- register_copy 
     jmp b4
-  //SEG266 mul16u::@4
+  //SEG258 mul16u::@4
   b4:
-  //SEG267 [133] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ) -- vwuz1=vwuz1_ror_1 
+  //SEG259 [130] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ) -- vwuz1=vwuz1_ror_1 
     clc
     ror a+1
     ror a
-  //SEG268 [134] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ) -- vduz1=vduz1_rol_1 
+  //SEG260 [131] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ) -- vduz1=vduz1_rol_1 
     asl mb
     rol mb+1
     rol mb+2
     rol mb+3
-  //SEG269 [126] phi from mul16u::@4 to mul16u::@1 [phi:mul16u::@4->mul16u::@1]
+  //SEG261 [123] phi from mul16u::@4 to mul16u::@1 [phi:mul16u::@4->mul16u::@1]
   b1_from_b4:
-  //SEG270 [126] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#1 [phi:mul16u::@4->mul16u::@1#0] -- register_copy 
-  //SEG271 [126] phi (dword) mul16u::res#2 = (dword) mul16u::res#6 [phi:mul16u::@4->mul16u::@1#1] -- register_copy 
-  //SEG272 [126] phi (word) mul16u::a#2 = (word) mul16u::a#0 [phi:mul16u::@4->mul16u::@1#2] -- register_copy 
+  //SEG262 [123] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#1 [phi:mul16u::@4->mul16u::@1#0] -- register_copy 
+  //SEG263 [123] phi (dword) mul16u::res#2 = (dword) mul16u::res#6 [phi:mul16u::@4->mul16u::@1#1] -- register_copy 
+  //SEG264 [123] phi (word) mul16u::a#2 = (word) mul16u::a#0 [phi:mul16u::@4->mul16u::@1#2] -- register_copy 
     jmp b1
 }
-//SEG273 div32u16u
+//SEG265 div32u16u
 div32u16u: {
-    .label return = $1b
     .label quotient_hi = $13
     .label quotient_lo = 8
-  //SEG274 [136] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
-  //SEG275 [145] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
+    .label return = $1b
+  //SEG266 [133] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
+  //SEG267 [142] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
   divr16u_from_div32u16u:
-  //SEG276 [145] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
+  //SEG268 [142] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
     lda #<main.wavelength
     sta divr16u.divisor
     lda #>main.wavelength
     sta divr16u.divisor+1
-  //SEG277 [145] phi (word) divr16u::dividend#5 = >(const dword) PI2_u4f28#0 [phi:div32u16u->divr16u#1] -- vwuz1=vwuc1 
+  //SEG269 [142] phi (word) divr16u::dividend#5 = >(const dword) PI2_u4f28#0 [phi:div32u16u->divr16u#1] -- vwuz1=vwuc1 
     lda #<PI2_u4f28>>16
     sta divr16u.dividend
     lda #>PI2_u4f28>>16
     sta divr16u.dividend+1
-  //SEG278 [145] phi (word) divr16u::rem#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:div32u16u->divr16u#2] -- vwuz1=vbuc1 
+  //SEG270 [142] phi (word) divr16u::rem#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:div32u16u->divr16u#2] -- vwuz1=vbuc1 
     lda #<0
     sta divr16u.rem
     lda #>0
     sta divr16u.rem+1
     jsr divr16u
-  //SEG279 [137] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] )
+  //SEG271 [134] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] )
     // (word) divr16u::return#2 = (word) divr16u::return#0  // register copy zp ZP_WORD:8
     jmp b2
-  //SEG280 div32u16u::@2
+  //SEG272 div32u16u::@2
   b2:
-  //SEG281 [138] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) -- vwuz1=vwuz2 
+  //SEG273 [135] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) -- vwuz1=vwuz2 
     lda divr16u.return
     sta quotient_hi
     lda divr16u.return+1
     sta quotient_hi+1
-  //SEG282 [139] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] )
+  //SEG274 [136] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] )
     // (word) divr16u::rem#4 = (word) rem16u#1  // register copy zp ZP_WORD:4
-  //SEG283 [140] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
-  //SEG284 [145] phi from div32u16u::@2 to divr16u [phi:div32u16u::@2->divr16u]
+  //SEG275 [137] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
+  //SEG276 [142] phi from div32u16u::@2 to divr16u [phi:div32u16u::@2->divr16u]
   divr16u_from_b2:
-  //SEG285 [145] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u::@2->divr16u#0] -- vwuz1=vwuc1 
+  //SEG277 [142] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u::@2->divr16u#0] -- vwuz1=vwuc1 
     lda #<main.wavelength
     sta divr16u.divisor
     lda #>main.wavelength
     sta divr16u.divisor+1
-  //SEG286 [145] phi (word) divr16u::dividend#5 = <(const dword) PI2_u4f28#0 [phi:div32u16u::@2->divr16u#1] -- vwuz1=vwuc1 
+  //SEG278 [142] phi (word) divr16u::dividend#5 = <(const dword) PI2_u4f28#0 [phi:div32u16u::@2->divr16u#1] -- vwuz1=vwuc1 
     lda #<PI2_u4f28&$ffff
     sta divr16u.dividend
     lda #>PI2_u4f28&$ffff
     sta divr16u.dividend+1
-  //SEG287 [145] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:div32u16u::@2->divr16u#2] -- register_copy 
+  //SEG279 [142] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:div32u16u::@2->divr16u#2] -- register_copy 
     jsr divr16u
-  //SEG288 [141] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] )
+  //SEG280 [138] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] )
     // (word) divr16u::return#3 = (word) divr16u::return#0  // register copy zp ZP_WORD:8
     jmp b3
-  //SEG289 div32u16u::@3
+  //SEG281 div32u16u::@3
   b3:
-  //SEG290 [142] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] )
+  //SEG282 [139] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] )
     // (word) div32u16u::quotient_lo#0 = (word) divr16u::return#3  // register copy zp ZP_WORD:8
-  //SEG291 [143] (dword) div32u16u::return#1 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] ) -- vduz1=vwuz2_dword_vwuz3 
+  //SEG283 [140] (dword) div32u16u::return#0 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] ) -- vduz1=vwuz2_dword_vwuz3 
     lda quotient_hi
     sta return+2
     lda quotient_hi+1
@@ -8043,70 +7916,70 @@ div32u16u: {
     lda quotient_lo+1
     sta return+1
     jmp breturn
-  //SEG292 div32u16u::@return
+  //SEG284 div32u16u::@return
   breturn:
-  //SEG293 [144] return  [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] )
+  //SEG285 [141] return  [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] )
     rts
 }
-//SEG294 divr16u
+//SEG286 divr16u
 divr16u: {
     .label rem = 4
     .label dividend = 6
     .label quotient = 8
     .label return = 8
     .label divisor = 2
-  //SEG295 [146] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
+  //SEG287 [143] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
   b1_from_divr16u:
-  //SEG296 [146] phi (byte) divr16u::i#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#0] -- vbuxx=vbuc1 
+  //SEG288 [143] phi (byte) divr16u::i#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#0] -- vbuxx=vbuc1 
     ldx #0
-  //SEG297 [146] phi (word) divr16u::quotient#3 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#1] -- vwuz1=vbuc1 
+  //SEG289 [143] phi (word) divr16u::quotient#3 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#1] -- vwuz1=vbuc1 
     lda #<0
     sta quotient
     lda #>0
     sta quotient+1
-  //SEG298 [146] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#5 [phi:divr16u->divr16u::@1#2] -- register_copy 
-  //SEG299 [146] phi (word) divr16u::rem#5 = (word) divr16u::rem#10 [phi:divr16u->divr16u::@1#3] -- register_copy 
+  //SEG290 [143] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#5 [phi:divr16u->divr16u::@1#2] -- register_copy 
+  //SEG291 [143] phi (word) divr16u::rem#5 = (word) divr16u::rem#10 [phi:divr16u->divr16u::@1#3] -- register_copy 
     jmp b1
-  //SEG300 [146] phi from divr16u::@3 to divr16u::@1 [phi:divr16u::@3->divr16u::@1]
+  //SEG292 [143] phi from divr16u::@3 to divr16u::@1 [phi:divr16u::@3->divr16u::@1]
   b1_from_b3:
-  //SEG301 [146] phi (byte) divr16u::i#2 = (byte) divr16u::i#1 [phi:divr16u::@3->divr16u::@1#0] -- register_copy 
-  //SEG302 [146] phi (word) divr16u::quotient#3 = (word) divr16u::return#0 [phi:divr16u::@3->divr16u::@1#1] -- register_copy 
-  //SEG303 [146] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#0 [phi:divr16u::@3->divr16u::@1#2] -- register_copy 
-  //SEG304 [146] phi (word) divr16u::rem#5 = (word) divr16u::rem#11 [phi:divr16u::@3->divr16u::@1#3] -- register_copy 
+  //SEG293 [143] phi (byte) divr16u::i#2 = (byte) divr16u::i#1 [phi:divr16u::@3->divr16u::@1#0] -- register_copy 
+  //SEG294 [143] phi (word) divr16u::quotient#3 = (word) divr16u::return#0 [phi:divr16u::@3->divr16u::@1#1] -- register_copy 
+  //SEG295 [143] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#0 [phi:divr16u::@3->divr16u::@1#2] -- register_copy 
+  //SEG296 [143] phi (word) divr16u::rem#5 = (word) divr16u::rem#11 [phi:divr16u::@3->divr16u::@1#3] -- register_copy 
     jmp b1
-  //SEG305 divr16u::@1
+  //SEG297 divr16u::@1
   b1:
-  //SEG306 [147] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG298 [144] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vwuz1=vwuz1_rol_1 
     asl rem
     rol rem+1
-  //SEG307 [148] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) -- vbuaa=_hi_vwuz1 
+  //SEG299 [145] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) -- vbuaa=_hi_vwuz1 
     lda dividend+1
-  //SEG308 [149] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) -- vbuaa=vbuaa_band_vbuc1 
+  //SEG300 [146] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) -- vbuaa=vbuaa_band_vbuc1 
     and #$80
-  //SEG309 [150] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vbuaa_eq_0_then_la1 
+  //SEG301 [147] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vbuaa_eq_0_then_la1 
     cmp #0
     beq b2_from_b1
     jmp b4
-  //SEG310 divr16u::@4
+  //SEG302 divr16u::@4
   b4:
-  //SEG311 [151] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) -- vwuz1=vwuz1_bor_vbuc1 
+  //SEG303 [148] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) -- vwuz1=vwuz1_bor_vbuc1 
     lda #1
     ora rem
     sta rem
-  //SEG312 [152] phi from divr16u::@1 divr16u::@4 to divr16u::@2 [phi:divr16u::@1/divr16u::@4->divr16u::@2]
+  //SEG304 [149] phi from divr16u::@1 divr16u::@4 to divr16u::@2 [phi:divr16u::@1/divr16u::@4->divr16u::@2]
   b2_from_b1:
   b2_from_b4:
-  //SEG313 [152] phi (word) divr16u::rem#6 = (word) divr16u::rem#0 [phi:divr16u::@1/divr16u::@4->divr16u::@2#0] -- register_copy 
+  //SEG305 [149] phi (word) divr16u::rem#6 = (word) divr16u::rem#0 [phi:divr16u::@1/divr16u::@4->divr16u::@2#0] -- register_copy 
     jmp b2
-  //SEG314 divr16u::@2
+  //SEG306 divr16u::@2
   b2:
-  //SEG315 [153] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG307 [150] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ) -- vwuz1=vwuz1_rol_1 
     asl dividend
     rol dividend+1
-  //SEG316 [154] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG308 [151] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1=vwuz1_rol_1 
     asl quotient
     rol quotient+1
-  //SEG317 [155] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1_lt_vwuz2_then_la1 
+  //SEG309 [152] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1_lt_vwuz2_then_la1 
     lda rem+1
     cmp divisor+1
     bcc b3_from_b2
@@ -8116,14 +7989,14 @@ divr16u: {
     bcc b3_from_b2
   !:
     jmp b5
-  //SEG318 divr16u::@5
+  //SEG310 divr16u::@5
   b5:
-  //SEG319 [156] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ) -- vwuz1=_inc_vwuz1 
+  //SEG311 [153] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ) -- vwuz1=_inc_vwuz1 
     inc quotient
     bne !+
     inc quotient+1
   !:
-  //SEG320 [157] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) -- vwuz1=vwuz1_minus_vwuz2 
+  //SEG312 [154] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) -- vwuz1=vwuz1_minus_vwuz2 
     lda rem
     sec
     sbc divisor
@@ -8131,28 +8004,28 @@ divr16u: {
     lda rem+1
     sbc divisor+1
     sta rem+1
-  //SEG321 [158] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
+  //SEG313 [155] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
   b3_from_b2:
   b3_from_b5:
-  //SEG322 [158] phi (word) divr16u::return#0 = (word) divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy 
-  //SEG323 [158] phi (word) divr16u::rem#11 = (word) divr16u::rem#6 [phi:divr16u::@2/divr16u::@5->divr16u::@3#1] -- register_copy 
+  //SEG314 [155] phi (word) divr16u::return#0 = (word) divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy 
+  //SEG315 [155] phi (word) divr16u::rem#11 = (word) divr16u::rem#6 [phi:divr16u::@2/divr16u::@5->divr16u::@3#1] -- register_copy 
     jmp b3
-  //SEG324 divr16u::@3
+  //SEG316 divr16u::@3
   b3:
-  //SEG325 [159] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuxx=_inc_vbuxx 
+  //SEG317 [156] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuxx=_inc_vbuxx 
     inx
-  //SEG326 [160] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuxx_neq_vbuc1_then_la1 
+  //SEG318 [157] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuxx_neq_vbuc1_then_la1 
     cpx #$10
     bne b1_from_b3
     jmp b6
-  //SEG327 divr16u::@6
+  //SEG319 divr16u::@6
   b6:
-  //SEG328 [161] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  //SEG320 [158] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
     // (word) rem16u#1 = (word) divr16u::rem#11  // register copy zp ZP_WORD:4
     jmp breturn
-  //SEG329 divr16u::@return
+  //SEG321 divr16u::@return
   breturn:
-  //SEG330 [162] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  //SEG322 [159] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
     rts
 }
 
@@ -8192,7 +8065,6 @@ Removing instruction jmp b9
 Removing instruction jmp b10
 Removing instruction jmp b11
 Removing instruction jmp b12
-Removing instruction jmp b13
 Removing instruction jmp b6
 Removing instruction jmp b3
 Removing instruction jmp breturn
@@ -8236,7 +8108,7 @@ Replacing label b2_from_b1 with b2
 Replacing label b2_from_b1 with b2
 Replacing label b2_from_b1 with b2
 Replacing label b2_from_b1 with b2
-Replacing label b3_from_b16 with b3
+Replacing label b3_from_b15 with b3
 Replacing label b4_from_b2 with b4
 Replacing label b2_from_b1 with b2
 Replacing label b3_from_b2 with b3
@@ -8265,7 +8137,7 @@ Removing instruction b1_from_b1:
 Removing instruction b1_from_b4:
 Removing instruction b2_from_b1:
 Removing instruction b2_from_b5:
-Removing instruction b3_from_b16:
+Removing instruction b3_from_b15:
 Removing instruction b3_from_b6:
 Removing instruction breturn:
 Removing instruction b4_from_b2:
@@ -8318,8 +8190,6 @@ Removing instruction mul_u16_sel_from_b10:
 Removing instruction b11:
 Removing instruction mul_u16_sel_from_b11:
 Removing instruction b12:
-Removing instruction mul_u16_sel_from_b12:
-Removing instruction b13:
 Removing instruction b6:
 Removing instruction b2:
 Removing instruction breturn:
@@ -8338,7 +8208,7 @@ Removing instruction b5:
 Removing instruction b6:
 Removing instruction breturn:
 Succesful ASM optimization Pass5UnusedLabelElimination
-Skipping double jump to b3 in beq b16
+Skipping double jump to b3 in beq b15
 Succesful ASM optimization Pass5DoubleJumpElimination
 Relabelling long label b1_from_sin16s to b4
 Succesful ASM optimization Pass5RelabelLongLabels
@@ -8349,7 +8219,7 @@ Removing instruction jmp b1
 Succesful ASM optimization Pass5NextJumpElimination
 Removing instruction lda #0
 Succesful ASM optimization Pass5UnnecesaryLoadElimination
-Removing instruction b16:
+Removing instruction b15:
 Succesful ASM optimization Pass5UnusedLabelElimination
 Removing unreachable instruction jmp b3
 Succesful ASM optimization Pass5UnreachableCodeElimination
@@ -8388,8 +8258,8 @@ FINAL SYMBOL TABLE
 (word) div32u16u::quotient_lo
 (word) div32u16u::quotient_lo#0 quotient_lo zp ZP_WORD:8 4.0
 (dword) div32u16u::return
-(dword) div32u16u::return#0 return zp ZP_DWORD:27 4.0
-(dword) div32u16u::return#1 return zp ZP_DWORD:27 1.3333333333333333
+(dword) div32u16u::return#0 return zp ZP_DWORD:27 1.3333333333333333
+(dword) div32u16u::return#2 return zp ZP_DWORD:27 4.0
 (word()) divr16u((word) divr16u::dividend , (word) divr16u::divisor , (word) divr16u::rem)
 (byte~) divr16u::$1 reg byte a 22.0
 (byte~) divr16u::$2 reg byte a 22.0
@@ -8477,27 +8347,25 @@ FINAL SYMBOL TABLE
 (word) mul_u16_sel::return
 (word) mul_u16_sel::return#0 return zp ZP_WORD:19 4.0
 (word) mul_u16_sel::return#1 return#1 zp ZP_WORD:8 4.0
-(word) mul_u16_sel::return#10 return zp ZP_WORD:19 4.0
-(word) mul_u16_sel::return#11 return#11 zp ZP_WORD:8 4.0
-(word) mul_u16_sel::return#12 return#12 zp ZP_WORD:8 4.0
-(word) mul_u16_sel::return#13 return zp ZP_WORD:19 4.0
-(word) mul_u16_sel::return#14 return zp ZP_WORD:19 1.75
+(word) mul_u16_sel::return#10 return#10 zp ZP_WORD:8 4.0
+(word) mul_u16_sel::return#11 return zp ZP_WORD:19 4.0
+(word) mul_u16_sel::return#12 return zp ZP_WORD:19 1.714285714285714
+(word) mul_u16_sel::return#2 return zp ZP_WORD:19 4.0
 (byte) mul_u16_sel::select
-(byte) mul_u16_sel::select#6 reg byte x 0.3333333333333333
+(byte) mul_u16_sel::select#5 reg byte x 0.3333333333333333
 (word) mul_u16_sel::v1
 (word) mul_u16_sel::v1#0 v1 zp ZP_WORD:8 2.0
 (word) mul_u16_sel::v1#1 v1 zp ZP_WORD:8 2.0
 (word) mul_u16_sel::v1#2 v1 zp ZP_WORD:8 4.0
 (word) mul_u16_sel::v1#3 v1 zp ZP_WORD:8 2.0
 (word) mul_u16_sel::v1#4 v1 zp ZP_WORD:8 2.0
-(word) mul_u16_sel::v1#5 v1 zp ZP_WORD:8 4.0
-(word) mul_u16_sel::v1#6 v1 zp ZP_WORD:8 14.0
+(word) mul_u16_sel::v1#5 v1 zp ZP_WORD:8 12.0
 (word) mul_u16_sel::v2
 (word) mul_u16_sel::v2#0 v2 zp ZP_WORD:19 4.0
 (word) mul_u16_sel::v2#1 v2 zp ZP_WORD:19 4.0
 (word) mul_u16_sel::v2#3 v2 zp ZP_WORD:19 4.0
 (word) mul_u16_sel::v2#4 v2 zp ZP_WORD:19 4.0
-(word) mul_u16_sel::v2#6 v2 zp ZP_WORD:19 5.0
+(word) mul_u16_sel::v2#5 v2 zp ZP_WORD:19 5.0
 (void()) print_byte((byte) print_byte::b)
 (byte~) print_byte::$0 reg byte a 4.0
 (byte~) print_byte::$2 reg byte a 4.0
@@ -8550,8 +8418,7 @@ FINAL SYMBOL TABLE
 (label) sin16s::@10
 (label) sin16s::@11
 (label) sin16s::@12
-(label) sin16s::@13
-(label) sin16s::@16
+(label) sin16s::@15
 (label) sin16s::@2
 (label) sin16s::@3
 (label) sin16s::@4
@@ -8561,7 +8428,7 @@ FINAL SYMBOL TABLE
 (label) sin16s::@9
 (label) sin16s::@return
 (byte) sin16s::isUpper
-(byte) sin16s::isUpper#10 isUpper zp ZP_BYTE:14 0.05555555555555555
+(byte) sin16s::isUpper#2 isUpper zp ZP_BYTE:14 0.06060606060606061
 (signed word) sin16s::return
 (signed word) sin16s::return#0 return zp ZP_WORD:6 22.0
 (signed word) sin16s::return#1 return zp ZP_WORD:6 5.0
@@ -8569,7 +8436,7 @@ FINAL SYMBOL TABLE
 (signed word) sin16s::sinx
 (signed word) sin16s::sinx#1 sinx zp ZP_WORD:6 4.0
 (word) sin16s::usinx
-(word) sin16s::usinx#0 usinx zp ZP_WORD:6 0.26666666666666666
+(word) sin16s::usinx#0 usinx zp ZP_WORD:6 0.3333333333333333
 (word) sin16s::usinx#1 usinx zp ZP_WORD:6 1.0
 (dword) sin16s::x
 (dword) sin16s::x#0 x zp ZP_DWORD:15 8.5
@@ -8588,7 +8455,7 @@ FINAL SYMBOL TABLE
 (word) sin16s::x4
 (word) sin16s::x4#0 x4 zp ZP_WORD:8 4.0
 (word) sin16s::x5
-(word) sin16s::x5#0 x5 zp ZP_WORD:8 4.0
+(word) sin16s::x5#0 x5 zp ZP_WORD:19 4.0
 (word) sin16s::x5_128
 (word) sin16s::x5_128#0 x5_128 zp ZP_WORD:19 4.0
 (void()) sin16s_gen((signed word*) sin16s_gen::sintab , (word) sin16s_gen::wavelength)
@@ -8615,18 +8482,18 @@ zp ZP_WORD:4 [ print_str::str#3 print_str::str#5 print_str::str#0 sin16s_gen::i#
 zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 main::sw#0 sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 sin16s_gen::$1 sin16s::usinx#0 divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ]
 reg byte x [ print_byte::b#2 print_byte::b#0 print_byte::b#1 ]
 reg byte a [ print_char::ch#3 print_char::ch#1 print_char::ch#2 ]
-zp ZP_WORD:8 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 sin16s::x5#0 mul_u16_sel::return#1 mul_u16_sel::return#11 mul_u16_sel::return#12 divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ]
+zp ZP_WORD:8 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mul_u16_sel::return#1 mul_u16_sel::return#10 divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ]
 zp ZP_DWORD:10 [ sin16s_gen::x#2 sin16s_gen::x#1 ]
-zp ZP_BYTE:14 [ sin16s::isUpper#10 ]
+zp ZP_BYTE:14 [ sin16s::isUpper#2 ]
 zp ZP_DWORD:15 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 sin16s::$6 mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#2 mul_u16_sel::$0 mul_u16_sel::$1 ]
-zp ZP_WORD:19 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 mul_u16_sel::return#0 mul_u16_sel::return#14 mul_u16_sel::return#10 sin16s::x3_6#0 mul_u16_sel::return#13 sin16s::x5_128#0 div32u16u::quotient_hi#0 ]
-reg byte x [ mul_u16_sel::select#6 ]
+zp ZP_WORD:19 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 mul_u16_sel::return#0 mul_u16_sel::return#12 mul_u16_sel::return#2 sin16s::x3_6#0 mul_u16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 div32u16u::quotient_hi#0 ]
+reg byte x [ mul_u16_sel::select#5 ]
 zp ZP_WORD:21 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ]
 zp ZP_DWORD:23 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
 reg byte x [ divr16u::i#2 divr16u::i#1 ]
 reg byte a [ print_byte::$0 ]
 reg byte a [ print_byte::$2 ]
-zp ZP_DWORD:27 [ div32u16u::return#0 sin16s_gen::step#0 div32u16u::return#1 ]
+zp ZP_DWORD:27 [ div32u16u::return#2 sin16s_gen::step#0 div32u16u::return#0 ]
 zp ZP_WORD:31 [ sin16s::x1#0 ]
 reg byte a [ mul16u::$1 ]
 reg byte a [ divr16u::$1 ]
@@ -8634,7 +8501,7 @@ reg byte a [ divr16u::$2 ]
 
 
 FINAL ASSEMBLER
-Score: 20921
+Score: 20907
 
 //SEG0 Basic Upstart
 .pc = $801 "Basic"
@@ -8927,14 +8794,14 @@ sin16s_gen: {
     .label sintab = 2
     .label x = $a
     .label i = 4
-  //SEG123 [59] call div32u16u param-assignment [ div32u16u::return#1 ] ( main:2::sin16s_gen:5 [ div32u16u::return#1 ] )
-  //SEG124 [135] phi from sin16s_gen to div32u16u [phi:sin16s_gen->div32u16u]
+  //SEG123 [59] call div32u16u param-assignment [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
+  //SEG124 [132] phi from sin16s_gen to div32u16u [phi:sin16s_gen->div32u16u]
     jsr div32u16u
-  //SEG125 [60] (dword) div32u16u::return#0 ← (dword) div32u16u::return#1 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5 [ div32u16u::return#0 ] )
-    // (dword) div32u16u::return#0 = (dword) div32u16u::return#1  // register copy zp ZP_DWORD:27
+  //SEG125 [60] (dword) div32u16u::return#2 ← (dword) div32u16u::return#0 [ div32u16u::return#2 ] ( main:2::sin16s_gen:5 [ div32u16u::return#2 ] )
+    // (dword) div32u16u::return#2 = (dword) div32u16u::return#0  // register copy zp ZP_DWORD:27
   //SEG126 sin16s_gen::@3
-  //SEG127 [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#0 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] )
-    // (dword) sin16s_gen::step#0 = (dword) div32u16u::return#0  // register copy zp ZP_DWORD:27
+  //SEG127 [61] (dword) sin16s_gen::step#0 ← (dword) div32u16u::return#2 [ sin16s_gen::step#0 ] ( main:2::sin16s_gen:5 [ sin16s_gen::step#0 ] )
+    // (dword) sin16s_gen::step#0 = (dword) div32u16u::return#2  // register copy zp ZP_DWORD:27
   //SEG128 [62] phi from sin16s_gen::@3 to sin16s_gen::@1 [phi:sin16s_gen::@3->sin16s_gen::@1]
   //SEG129 [62] phi (word) sin16s_gen::i#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s_gen::@3->sin16s_gen::@1#0] -- vwuz1=vbuc1 
     lda #<0
@@ -9031,7 +8898,7 @@ sin16s: {
     .label x3_6 = $13
     .label usinx = 6
     .label x4 = 8
-    .label x5 = 8
+    .label x5 = $13
     .label x5_128 = $13
     .label sinx = 6
     .label isUpper = $e
@@ -9068,20 +8935,20 @@ sin16s: {
     sbc #>PI_u4f28>>$10
     sta x+3
   //SEG153 [75] phi from sin16s::@4 to sin16s::@1 [phi:sin16s::@4->sin16s::@1]
-  //SEG154 [75] phi (byte) sin16s::isUpper#10 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@4->sin16s::@1#0] -- vbuz1=vbuc1 
+  //SEG154 [75] phi (byte) sin16s::isUpper#2 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@4->sin16s::@1#0] -- vbuz1=vbuc1 
     lda #1
     sta isUpper
   //SEG155 [75] phi (dword) sin16s::x#4 = (dword) sin16s::x#1 [phi:sin16s::@4->sin16s::@1#1] -- register_copy 
     jmp b1
   //SEG156 [75] phi from sin16s to sin16s::@1 [phi:sin16s->sin16s::@1]
   b4:
-  //SEG157 [75] phi (byte) sin16s::isUpper#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s->sin16s::@1#0] -- vbuz1=vbuc1 
+  //SEG157 [75] phi (byte) sin16s::isUpper#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s->sin16s::@1#0] -- vbuz1=vbuc1 
     lda #0
     sta isUpper
   //SEG158 [75] phi (dword) sin16s::x#4 = (dword) sin16s::x#0 [phi:sin16s->sin16s::@1#1] -- register_copy 
   //SEG159 sin16s::@1
   b1:
-  //SEG160 [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#10 ] ) -- vduz1_lt_vduc1_then_la1 
+  //SEG160 [76] if((dword) sin16s::x#4<(const dword) PI_HALF_u4f28#0) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::x#4 sin16s::isUpper#2 ] ) -- vduz1_lt_vduc1_then_la1 
     lda x+3
     cmp #>PI_HALF_u4f28>>$10
     bcc b2
@@ -9099,7 +8966,7 @@ sin16s: {
     bcc b2
   !:
   //SEG161 sin16s::@5
-  //SEG162 [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#10 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x#2 ] ) -- vduz1=vduc1_minus_vduz1 
+  //SEG162 [77] (dword) sin16s::x#2 ← (const dword) PI_u4f28#0 - (dword) sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x#2 ] ) -- vduz1=vduc1_minus_vduz1 
     lda #<PI_u4f28
     sec
     sbc x
@@ -9117,7 +8984,7 @@ sin16s: {
   //SEG164 [78] phi (dword) sin16s::x#6 = (dword) sin16s::x#4 [phi:sin16s::@1/sin16s::@5->sin16s::@2#0] -- register_copy 
   //SEG165 sin16s::@2
   b2:
-  //SEG166 [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#10 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::$6 ] ) -- vduz1=vduz1_rol_3 
+  //SEG166 [79] (dword~) sin16s::$6 ← (dword) sin16s::x#6 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ sin16s::isUpper#2 sin16s::$6 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::$6 ] ) -- vduz1=vduz1_rol_3 
     ldy #3
   !:
     asl _6
@@ -9126,77 +8993,77 @@ sin16s: {
     rol _6+3
     dey
     bne !-
-  //SEG167 [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#10 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 ] ) -- vwuz1=_hi_vduz2 
+  //SEG167 [80] (word) sin16s::x1#0 ← > (dword~) sin16s::$6 [ sin16s::isUpper#2 sin16s::x1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 ] ) -- vwuz1=_hi_vduz2 
     lda _6+2
     sta x1
     lda _6+3
     sta x1+1
-  //SEG168 [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 ] ) -- vwuz1=vwuz2 
+  //SEG168 [81] (word) mul_u16_sel::v1#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v1
     lda x1+1
     sta mul_u16_sel.v1+1
-  //SEG169 [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) -- vwuz1=vwuz2 
+  //SEG169 [82] (word) mul_u16_sel::v2#0 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#0 mul_u16_sel::v2#0 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG170 [83] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  //SEG171 [116] phi from sin16s::@2 to mul_u16_sel [phi:sin16s::@2->mul_u16_sel]
-  //SEG172 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@2->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG170 [83] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  //SEG171 [113] phi from sin16s::@2 to mul_u16_sel [phi:sin16s::@2->mul_u16_sel]
+  //SEG172 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@2->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #0
-  //SEG173 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#0 [phi:sin16s::@2->mul_u16_sel#1] -- register_copy 
-  //SEG174 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#0 [phi:sin16s::@2->mul_u16_sel#2] -- register_copy 
+  //SEG173 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#0 [phi:sin16s::@2->mul_u16_sel#1] -- register_copy 
+  //SEG174 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#0 [phi:sin16s::@2->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG175 [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#0 ] )
-    // (word) mul_u16_sel::return#0 = (word) mul_u16_sel::return#14  // register copy zp ZP_WORD:19
+  //SEG175 [84] (word) mul_u16_sel::return#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#0 ] )
+    // (word) mul_u16_sel::return#0 = (word) mul_u16_sel::return#12  // register copy zp ZP_WORD:19
   //SEG176 sin16s::@8
-  //SEG177 [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x2#0 ] ) -- vwuz1=vwuz2 
+  //SEG177 [85] (word) sin16s::x2#0 ← (word) mul_u16_sel::return#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x2#0 ] ) -- vwuz1=vwuz2 
     lda mul_u16_sel.return
     sta x2
     lda mul_u16_sel.return+1
     sta x2+1
-  //SEG178 [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 ] )
+  //SEG178 [86] (word) mul_u16_sel::v1#1 ← (word) sin16s::x2#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 ] )
     // (word) mul_u16_sel::v1#1 = (word) sin16s::x2#0  // register copy zp ZP_WORD:8
-  //SEG179 [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) -- vwuz1=vwuz2 
+  //SEG179 [87] (word) mul_u16_sel::v2#1 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v1#1 mul_u16_sel::v2#1 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG180 [88] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] )
-  //SEG181 [116] phi from sin16s::@8 to mul_u16_sel [phi:sin16s::@8->mul_u16_sel]
-  //SEG182 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@8->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG180 [88] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] )
+  //SEG181 [113] phi from sin16s::@8 to mul_u16_sel [phi:sin16s::@8->mul_u16_sel]
+  //SEG182 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@8->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #1
-  //SEG183 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#1 [phi:sin16s::@8->mul_u16_sel#1] -- register_copy 
-  //SEG184 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#1 [phi:sin16s::@8->mul_u16_sel#2] -- register_copy 
+  //SEG183 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#1 [phi:sin16s::@8->mul_u16_sel#1] -- register_copy 
+  //SEG184 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#1 [phi:sin16s::@8->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG185 [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#1 ] ) -- vwuz1=vwuz2 
+  //SEG185 [89] (word) mul_u16_sel::return#1 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#1 ] ) -- vwuz1=vwuz2 
     lda mul_u16_sel.return
     sta mul_u16_sel.return_1
     lda mul_u16_sel.return+1
     sta mul_u16_sel.return_1+1
   //SEG186 sin16s::@9
-  //SEG187 [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 ] )
+  //SEG187 [90] (word) sin16s::x3#0 ← (word) mul_u16_sel::return#1 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 ] )
     // (word) sin16s::x3#0 = (word) mul_u16_sel::return#1  // register copy zp ZP_WORD:8
-  //SEG188 [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] )
+  //SEG188 [91] (word) mul_u16_sel::v1#2 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v1#2 ] )
     // (word) mul_u16_sel::v1#2 = (word) sin16s::x3#0  // register copy zp ZP_WORD:8
-  //SEG189 [92] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::x3#0 ] )
-  //SEG190 [116] phi from sin16s::@9 to mul_u16_sel [phi:sin16s::@9->mul_u16_sel]
-  //SEG191 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@9->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG189 [92] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::x3#0 ] )
+  //SEG190 [113] phi from sin16s::@9 to mul_u16_sel [phi:sin16s::@9->mul_u16_sel]
+  //SEG191 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 1 [phi:sin16s::@9->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #1
-  //SEG192 [116] phi (word) mul_u16_sel::v2#6 = (dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 [phi:sin16s::@9->mul_u16_sel#1] -- vwuz1=vwuc1 
+  //SEG192 [113] phi (word) mul_u16_sel::v2#5 = (dword/signed dword) 65536/(byte/signed byte/word/signed word/dword/signed dword) 6 [phi:sin16s::@9->mul_u16_sel#1] -- vwuz1=vwuc1 
     lda #<$10000/6
     sta mul_u16_sel.v2
     lda #>$10000/6
     sta mul_u16_sel.v2+1
-  //SEG193 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#2 [phi:sin16s::@9->mul_u16_sel#2] -- register_copy 
+  //SEG193 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#2 [phi:sin16s::@9->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG194 [93] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#10 ] )
-    // (word) mul_u16_sel::return#10 = (word) mul_u16_sel::return#14  // register copy zp ZP_WORD:19
+  //SEG194 [93] (word) mul_u16_sel::return#2 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#2 ] )
+    // (word) mul_u16_sel::return#2 = (word) mul_u16_sel::return#12  // register copy zp ZP_WORD:19
   //SEG195 sin16s::@10
-  //SEG196 [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] )
-    // (word) sin16s::x3_6#0 = (word) mul_u16_sel::return#10  // register copy zp ZP_WORD:19
-  //SEG197 [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) -- vwuz1=vwuz2_minus_vwuz3 
+  //SEG196 [94] (word) sin16s::x3_6#0 ← (word) mul_u16_sel::return#2 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::x3_6#0 ] )
+    // (word) sin16s::x3_6#0 = (word) mul_u16_sel::return#2  // register copy zp ZP_WORD:19
+  //SEG197 [95] (word) sin16s::usinx#0 ← (word) sin16s::x1#0 - (word) sin16s::x3_6#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 sin16s::usinx#0 ] ) -- vwuz1=vwuz2_minus_vwuz3 
     lda x1
     sec
     sbc x3_6
@@ -9204,69 +9071,55 @@ sin16s: {
     lda x1+1
     sbc x3_6+1
     sta usinx+1
-  //SEG198 [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] )
+  //SEG198 [96] (word) mul_u16_sel::v1#3 ← (word) sin16s::x3#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 ] )
     // (word) mul_u16_sel::v1#3 = (word) sin16s::x3#0  // register copy zp ZP_WORD:8
-  //SEG199 [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) -- vwuz1=vwuz2 
+  //SEG199 [97] (word) mul_u16_sel::v2#3 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#3 mul_u16_sel::v2#3 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG200 [98] call mul_u16_sel param-assignment [ sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG201 [116] phi from sin16s::@10 to mul_u16_sel [phi:sin16s::@10->mul_u16_sel]
-  //SEG202 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@10->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG200 [98] call mul_u16_sel param-assignment [ sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  //SEG201 [113] phi from sin16s::@10 to mul_u16_sel [phi:sin16s::@10->mul_u16_sel]
+  //SEG202 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@10->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #0
-  //SEG203 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#3 [phi:sin16s::@10->mul_u16_sel#1] -- register_copy 
-  //SEG204 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#3 [phi:sin16s::@10->mul_u16_sel#2] -- register_copy 
+  //SEG203 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#3 [phi:sin16s::@10->mul_u16_sel#1] -- register_copy 
+  //SEG204 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#3 [phi:sin16s::@10->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG205 [99] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#11 ] ) -- vwuz1=vwuz2 
+  //SEG205 [99] (word) mul_u16_sel::return#10 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#10 ] ) -- vwuz1=vwuz2 
     lda mul_u16_sel.return
-    sta mul_u16_sel.return_11
+    sta mul_u16_sel.return_10
     lda mul_u16_sel.return+1
-    sta mul_u16_sel.return_11+1
+    sta mul_u16_sel.return_10+1
   //SEG206 sin16s::@11
-  //SEG207 [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] )
-    // (word) sin16s::x4#0 = (word) mul_u16_sel::return#11  // register copy zp ZP_WORD:8
-  //SEG208 [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] )
+  //SEG207 [100] (word) sin16s::x4#0 ← (word) mul_u16_sel::return#10 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 sin16s::x4#0 ] )
+    // (word) sin16s::x4#0 = (word) mul_u16_sel::return#10  // register copy zp ZP_WORD:8
+  //SEG208 [101] (word) mul_u16_sel::v1#4 ← (word) sin16s::x4#0 [ sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v1#4 ] )
     // (word) mul_u16_sel::v1#4 = (word) sin16s::x4#0  // register copy zp ZP_WORD:8
-  //SEG209 [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) -- vwuz1=vwuz2 
+  //SEG209 [102] (word) mul_u16_sel::v2#4 ← (word) sin16s::x1#0 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v1#4 mul_u16_sel::v2#4 ] ) -- vwuz1=vwuz2 
     lda x1
     sta mul_u16_sel.v2
     lda x1+1
     sta mul_u16_sel.v2+1
-  //SEG210 [103] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG211 [116] phi from sin16s::@11 to mul_u16_sel [phi:sin16s::@11->mul_u16_sel]
-  //SEG212 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@11->mul_u16_sel#0] -- vbuxx=vbuc1 
+  //SEG210 [103] call mul_u16_sel param-assignment [ sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 mul_u16_sel::return#12 sin16s::usinx#0 ] )
+  //SEG211 [113] phi from sin16s::@11 to mul_u16_sel [phi:sin16s::@11->mul_u16_sel]
+  //SEG212 [113] phi (byte) mul_u16_sel::select#5 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:sin16s::@11->mul_u16_sel#0] -- vbuxx=vbuc1 
     ldx #0
-  //SEG213 [116] phi (word) mul_u16_sel::v2#6 = (word) mul_u16_sel::v2#4 [phi:sin16s::@11->mul_u16_sel#1] -- register_copy 
-  //SEG214 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#4 [phi:sin16s::@11->mul_u16_sel#2] -- register_copy 
+  //SEG213 [113] phi (word) mul_u16_sel::v2#5 = (word) mul_u16_sel::v2#4 [phi:sin16s::@11->mul_u16_sel#1] -- register_copy 
+  //SEG214 [113] phi (word) mul_u16_sel::v1#5 = (word) mul_u16_sel::v1#4 [phi:sin16s::@11->mul_u16_sel#2] -- register_copy 
     jsr mul_u16_sel
-  //SEG215 [104] (word) mul_u16_sel::return#12 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#12 ] ) -- vwuz1=vwuz2 
-    lda mul_u16_sel.return
-    sta mul_u16_sel.return_12
-    lda mul_u16_sel.return+1
-    sta mul_u16_sel.return_12+1
+  //SEG215 [104] (word) mul_u16_sel::return#11 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#11 ] )
+    // (word) mul_u16_sel::return#11 = (word) mul_u16_sel::return#12  // register copy zp ZP_WORD:19
   //SEG216 sin16s::@12
-  //SEG217 [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#12 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5#0 ] )
-    // (word) sin16s::x5#0 = (word) mul_u16_sel::return#12  // register copy zp ZP_WORD:8
-  //SEG218 [106] (word) mul_u16_sel::v1#5 ← (word) sin16s::x5#0 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v1#5 ] )
-    // (word) mul_u16_sel::v1#5 = (word) sin16s::x5#0  // register copy zp ZP_WORD:8
-  //SEG219 [107] call mul_u16_sel param-assignment [ sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 mul_u16_sel::return#14 sin16s::usinx#0 ] )
-  //SEG220 [116] phi from sin16s::@12 to mul_u16_sel [phi:sin16s::@12->mul_u16_sel]
-  //SEG221 [116] phi (byte) mul_u16_sel::select#6 = (byte/signed byte/word/signed word/dword/signed dword) 3 [phi:sin16s::@12->mul_u16_sel#0] -- vbuxx=vbuc1 
-    ldx #3
-  //SEG222 [116] phi (word) mul_u16_sel::v2#6 = (dword/signed dword) 65536/(byte/word/signed word/dword/signed dword) 128 [phi:sin16s::@12->mul_u16_sel#1] -- vwuz1=vwuc1 
-    lda #<$10000/$80
-    sta mul_u16_sel.v2
-    lda #>$10000/$80
-    sta mul_u16_sel.v2+1
-  //SEG223 [116] phi (word) mul_u16_sel::v1#6 = (word) mul_u16_sel::v1#5 [phi:sin16s::@12->mul_u16_sel#2] -- register_copy 
-    jsr mul_u16_sel
-  //SEG224 [108] (word) mul_u16_sel::return#13 ← (word) mul_u16_sel::return#14 [ sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#13 ] )
-    // (word) mul_u16_sel::return#13 = (word) mul_u16_sel::return#14  // register copy zp ZP_WORD:19
-  //SEG225 sin16s::@13
-  //SEG226 [109] (word) sin16s::x5_128#0 ← (word) mul_u16_sel::return#13 [ sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 sin16s::x5_128#0 ] )
-    // (word) sin16s::x5_128#0 = (word) mul_u16_sel::return#13  // register copy zp ZP_WORD:19
-  //SEG227 [110] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#10 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#1 ] ) -- vwuz1=vwuz1_plus_vwuz2 
+  //SEG217 [105] (word) sin16s::x5#0 ← (word) mul_u16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] )
+    // (word) sin16s::x5#0 = (word) mul_u16_sel::return#11  // register copy zp ZP_WORD:19
+  //SEG218 [106] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) -- vwuz1=vwuz1_ror_4 
+    ldy #4
+  !:
+    lsr x5_128+1
+    ror x5_128
+    dey
+    bne !-
+  //SEG219 [107] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) -- vwuz1=vwuz1_plus_vwuz2 
     lda usinx
     clc
     adc x5_128
@@ -9274,11 +9127,11 @@ sin16s: {
     lda usinx+1
     adc x5_128+1
     sta usinx+1
-  //SEG228 [111] if((byte) sin16s::isUpper#10==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@16 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) -- vbuz1_eq_0_then_la1 
+  //SEG220 [108] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) -- vbuz1_eq_0_then_la1 
     lda isUpper
     beq b3
-  //SEG229 sin16s::@6
-  //SEG230 [112] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) -- vwsz1=_neg_vwsz1 
+  //SEG221 sin16s::@6
+  //SEG222 [109] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) -- vwsz1=_neg_vwsz1 
     sec
     lda sinx
     eor #$ff
@@ -9288,18 +9141,18 @@ sin16s: {
     eor #$ff
     adc #0
     sta sinx+1
-  //SEG231 [113] phi from sin16s::@16 sin16s::@6 to sin16s::@3 [phi:sin16s::@16/sin16s::@6->sin16s::@3]
-  //SEG232 [113] phi (signed word) sin16s::return#1 = (signed word~) sin16s::return#5 [phi:sin16s::@16/sin16s::@6->sin16s::@3#0] -- register_copy 
-  //SEG233 sin16s::@3
+  //SEG223 [110] phi from sin16s::@15 sin16s::@6 to sin16s::@3 [phi:sin16s::@15/sin16s::@6->sin16s::@3]
+  //SEG224 [110] phi (signed word) sin16s::return#1 = (signed word~) sin16s::return#5 [phi:sin16s::@15/sin16s::@6->sin16s::@3#0] -- register_copy 
+  //SEG225 sin16s::@3
   b3:
-  //SEG234 sin16s::@return
-  //SEG235 [114] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
+  //SEG226 sin16s::@return
+  //SEG227 [111] return  [ sin16s::return#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#1 ] )
     rts
-  //SEG236 sin16s::@16
-  //SEG237 [115] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] )
+  //SEG228 sin16s::@15
+  //SEG229 [112] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] )
     // (signed word~) sin16s::return#5 = (signed word)(word) sin16s::usinx#1  // register copy zp ZP_WORD:6
 }
-//SEG238 mul_u16_sel
+//SEG230 mul_u16_sel
 mul_u16_sel: {
     .label _0 = $f
     .label _1 = $f
@@ -9307,23 +9160,22 @@ mul_u16_sel: {
     .label v2 = $13
     .label return = $13
     .label return_1 = 8
-    .label return_11 = 8
-    .label return_12 = 8
-  //SEG239 [117] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#6 [ mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::v2#6 mul_u16_sel::select#6 mul16u::a#1 ] ) -- vwuz1=vwuz2 
+    .label return_10 = 8
+  //SEG231 [114] (word) mul16u::a#1 ← (word) mul_u16_sel::v1#5 [ mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::v2#5 mul_u16_sel::select#5 mul16u::a#1 ] ) -- vwuz1=vwuz2 
     lda v1
     sta mul16u.a
     lda v1+1
     sta mul16u.a+1
-  //SEG240 [118] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#6 [ mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::b#0 ] )
-    // (word) mul16u::b#0 = (word) mul_u16_sel::v2#6  // register copy zp ZP_WORD:19
-  //SEG241 [119] call mul16u param-assignment [ mul_u16_sel::select#6 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
+  //SEG232 [115] (word) mul16u::b#0 ← (word) mul_u16_sel::v2#5 [ mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::b#0 ] )
+    // (word) mul16u::b#0 = (word) mul_u16_sel::v2#5  // register copy zp ZP_WORD:19
+  //SEG233 [116] call mul16u param-assignment [ mul_u16_sel::select#5 mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
     jsr mul16u
-  //SEG242 [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#6 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::return#2 ] )
+  //SEG234 [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mul_u16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::return#2 ] )
     // (dword) mul16u::return#2 = (dword) mul16u::res#2  // register copy zp ZP_DWORD:15
-  //SEG243 mul_u16_sel::@2
-  //SEG244 [121] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#6 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul_u16_sel::$0 ] )
+  //SEG235 mul_u16_sel::@2
+  //SEG236 [118] (dword~) mul_u16_sel::$0 ← (dword) mul16u::return#2 [ mul_u16_sel::select#5 mul_u16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul_u16_sel::$0 ] )
     // (dword~) mul_u16_sel::$0 = (dword) mul16u::return#2  // register copy zp ZP_DWORD:15
-  //SEG245 [122] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#6 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::$1 ] ) -- vduz1=vduz1_rol_vbuxx 
+  //SEG237 [119] (dword~) mul_u16_sel::$1 ← (dword~) mul_u16_sel::$0 << (byte) mul_u16_sel::select#5 [ mul_u16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::$1 ] ) -- vduz1=vduz1_rol_vbuxx 
     cpx #0
     beq !e+
   !:
@@ -9334,23 +9186,23 @@ mul_u16_sel: {
     dex
     bne !-
   !e:
-  //SEG246 [123] (word) mul_u16_sel::return#14 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] ) -- vwuz1=_hi_vduz2 
+  //SEG238 [120] (word) mul_u16_sel::return#12 ← > (dword~) mul_u16_sel::$1 [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] ) -- vwuz1=_hi_vduz2 
     lda _1+2
     sta return
     lda _1+3
     sta return+1
-  //SEG247 mul_u16_sel::@return
-  //SEG248 [124] return  [ mul_u16_sel::return#14 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::return#14 ] )
+  //SEG239 mul_u16_sel::@return
+  //SEG240 [121] return  [ mul_u16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::return#12 ] )
     rts
 }
-//SEG249 mul16u
+//SEG241 mul16u
 mul16u: {
     .label mb = $17
     .label a = $15
     .label res = $f
     .label b = $13
     .label return = $f
-  //SEG250 [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#1 mul16u::mb#0 ] ) -- vduz1=_dword_vwuz2 
+  //SEG242 [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) -- vduz1=_dword_vwuz2 
     lda b
     sta mb
     lda b+1
@@ -9358,34 +9210,34 @@ mul16u: {
     lda #0
     sta mb+2
     sta mb+3
-  //SEG251 [126] phi from mul16u to mul16u::@1 [phi:mul16u->mul16u::@1]
-  //SEG252 [126] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#0 [phi:mul16u->mul16u::@1#0] -- register_copy 
-  //SEG253 [126] phi (dword) mul16u::res#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:mul16u->mul16u::@1#1] -- vduz1=vbuc1 
+  //SEG243 [123] phi from mul16u to mul16u::@1 [phi:mul16u->mul16u::@1]
+  //SEG244 [123] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#0 [phi:mul16u->mul16u::@1#0] -- register_copy 
+  //SEG245 [123] phi (dword) mul16u::res#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:mul16u->mul16u::@1#1] -- vduz1=vbuc1 
     sta res
     sta res+1
     sta res+2
     sta res+3
-  //SEG254 [126] phi (word) mul16u::a#2 = (word) mul16u::a#1 [phi:mul16u->mul16u::@1#2] -- register_copy 
-  //SEG255 mul16u::@1
+  //SEG246 [123] phi (word) mul16u::a#2 = (word) mul16u::a#1 [phi:mul16u->mul16u::@1#2] -- register_copy 
+  //SEG247 mul16u::@1
   b1:
-  //SEG256 [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vwuz1_neq_0_then_la1 
+  //SEG248 [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vwuz1_neq_0_then_la1 
     lda a
     bne b2
     lda a+1
     bne b2
-  //SEG257 mul16u::@return
-  //SEG258 [128] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 ] )
+  //SEG249 mul16u::@return
+  //SEG250 [125] return  [ mul16u::res#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 ] )
     rts
-  //SEG259 mul16u::@2
+  //SEG251 mul16u::@2
   b2:
-  //SEG260 [129] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) -- vbuaa=vwuz1_band_vbuc1 
+  //SEG252 [126] (byte~) mul16u::$1 ← (word) mul16u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 mul16u::$1 ] ) -- vbuaa=vwuz1_band_vbuc1 
     lda a
     and #1
-  //SEG261 [130] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vbuaa_eq_0_then_la1 
+  //SEG253 [127] if((byte~) mul16u::$1==(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@4 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) -- vbuaa_eq_0_then_la1 
     cmp #0
     beq b4
-  //SEG262 mul16u::@7
-  //SEG263 [131] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) -- vduz1=vduz1_plus_vduz2 
+  //SEG254 mul16u::@7
+  //SEG255 [128] (dword) mul16u::res#1 ← (dword) mul16u::res#2 + (dword) mul16u::mb#2 [ mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#2 mul16u::mb#2 mul16u::res#1 ] ) -- vduz1=vduz1_plus_vduz2 
     lda res
     clc
     adc mb
@@ -9399,77 +9251,77 @@ mul16u: {
     lda res+3
     adc mb+3
     sta res+3
-  //SEG264 [132] phi from mul16u::@2 mul16u::@7 to mul16u::@4 [phi:mul16u::@2/mul16u::@7->mul16u::@4]
-  //SEG265 [132] phi (dword) mul16u::res#6 = (dword) mul16u::res#2 [phi:mul16u::@2/mul16u::@7->mul16u::@4#0] -- register_copy 
-  //SEG266 mul16u::@4
+  //SEG256 [129] phi from mul16u::@2 mul16u::@7 to mul16u::@4 [phi:mul16u::@2/mul16u::@7->mul16u::@4]
+  //SEG257 [129] phi (dword) mul16u::res#6 = (dword) mul16u::res#2 [phi:mul16u::@2/mul16u::@7->mul16u::@4#0] -- register_copy 
+  //SEG258 mul16u::@4
   b4:
-  //SEG267 [133] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ) -- vwuz1=vwuz1_ror_1 
+  //SEG259 [130] (word) mul16u::a#0 ← (word) mul16u::a#2 >> (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::mb#2 mul16u::a#0 mul16u::res#6 ] ) -- vwuz1=vwuz1_ror_1 
     clc
     ror a+1
     ror a
-  //SEG268 [134] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:107::mul16u:119 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#10 sin16s::usinx#0 mul_u16_sel::select#6 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ) -- vduz1=vduz1_rol_1 
+  //SEG260 [131] (dword) mul16u::mb#1 ← (dword) mul16u::mb#2 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ( main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] main:2::sin16s_gen:5::sin16s:64::mul_u16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mul_u16_sel::select#5 mul16u::a#0 mul16u::res#6 mul16u::mb#1 ] ) -- vduz1=vduz1_rol_1 
     asl mb
     rol mb+1
     rol mb+2
     rol mb+3
-  //SEG269 [126] phi from mul16u::@4 to mul16u::@1 [phi:mul16u::@4->mul16u::@1]
-  //SEG270 [126] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#1 [phi:mul16u::@4->mul16u::@1#0] -- register_copy 
-  //SEG271 [126] phi (dword) mul16u::res#2 = (dword) mul16u::res#6 [phi:mul16u::@4->mul16u::@1#1] -- register_copy 
-  //SEG272 [126] phi (word) mul16u::a#2 = (word) mul16u::a#0 [phi:mul16u::@4->mul16u::@1#2] -- register_copy 
+  //SEG261 [123] phi from mul16u::@4 to mul16u::@1 [phi:mul16u::@4->mul16u::@1]
+  //SEG262 [123] phi (dword) mul16u::mb#2 = (dword) mul16u::mb#1 [phi:mul16u::@4->mul16u::@1#0] -- register_copy 
+  //SEG263 [123] phi (dword) mul16u::res#2 = (dword) mul16u::res#6 [phi:mul16u::@4->mul16u::@1#1] -- register_copy 
+  //SEG264 [123] phi (word) mul16u::a#2 = (word) mul16u::a#0 [phi:mul16u::@4->mul16u::@1#2] -- register_copy 
     jmp b1
 }
-//SEG273 div32u16u
+//SEG265 div32u16u
 div32u16u: {
-    .label return = $1b
     .label quotient_hi = $13
     .label quotient_lo = 8
-  //SEG274 [136] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
-  //SEG275 [145] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
-  //SEG276 [145] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
+    .label return = $1b
+  //SEG266 [133] call divr16u param-assignment [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 rem16u#1 ] )
+  //SEG267 [142] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
+  //SEG268 [142] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
     lda #<main.wavelength
     sta divr16u.divisor
     lda #>main.wavelength
     sta divr16u.divisor+1
-  //SEG277 [145] phi (word) divr16u::dividend#5 = >(const dword) PI2_u4f28#0 [phi:div32u16u->divr16u#1] -- vwuz1=vwuc1 
+  //SEG269 [142] phi (word) divr16u::dividend#5 = >(const dword) PI2_u4f28#0 [phi:div32u16u->divr16u#1] -- vwuz1=vwuc1 
     lda #<PI2_u4f28>>16
     sta divr16u.dividend
     lda #>PI2_u4f28>>16
     sta divr16u.dividend+1
-  //SEG278 [145] phi (word) divr16u::rem#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:div32u16u->divr16u#2] -- vwuz1=vbuc1 
+  //SEG270 [142] phi (word) divr16u::rem#10 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:div32u16u->divr16u#2] -- vwuz1=vbuc1 
     lda #<0
     sta divr16u.rem
     sta divr16u.rem+1
     jsr divr16u
-  //SEG279 [137] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] )
+  //SEG271 [134] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#2 rem16u#1 ] )
     // (word) divr16u::return#2 = (word) divr16u::return#0  // register copy zp ZP_WORD:8
-  //SEG280 div32u16u::@2
-  //SEG281 [138] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) -- vwuz1=vwuz2 
+  //SEG272 div32u16u::@2
+  //SEG273 [135] (word) div32u16u::quotient_hi#0 ← (word) divr16u::return#2 [ div32u16u::quotient_hi#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 rem16u#1 ] ) -- vwuz1=vwuz2 
     lda divr16u.return
     sta quotient_hi
     lda divr16u.return+1
     sta quotient_hi+1
-  //SEG282 [139] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] )
+  //SEG274 [136] (word) divr16u::rem#4 ← (word) rem16u#1 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::rem#4 ] )
     // (word) divr16u::rem#4 = (word) rem16u#1  // register copy zp ZP_WORD:4
-  //SEG283 [140] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
-  //SEG284 [145] phi from div32u16u::@2 to divr16u [phi:div32u16u::@2->divr16u]
-  //SEG285 [145] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u::@2->divr16u#0] -- vwuz1=vwuc1 
+  //SEG275 [137] call divr16u param-assignment [ divr16u::return#0 div32u16u::quotient_hi#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ divr16u::return#0 div32u16u::quotient_hi#0 ] )
+  //SEG276 [142] phi from div32u16u::@2 to divr16u [phi:div32u16u::@2->divr16u]
+  //SEG277 [142] phi (word) divr16u::divisor#6 = (const word) main::wavelength#0 [phi:div32u16u::@2->divr16u#0] -- vwuz1=vwuc1 
     lda #<main.wavelength
     sta divr16u.divisor
     lda #>main.wavelength
     sta divr16u.divisor+1
-  //SEG286 [145] phi (word) divr16u::dividend#5 = <(const dword) PI2_u4f28#0 [phi:div32u16u::@2->divr16u#1] -- vwuz1=vwuc1 
+  //SEG278 [142] phi (word) divr16u::dividend#5 = <(const dword) PI2_u4f28#0 [phi:div32u16u::@2->divr16u#1] -- vwuz1=vwuc1 
     lda #<PI2_u4f28&$ffff
     sta divr16u.dividend
     lda #>PI2_u4f28&$ffff
     sta divr16u.dividend+1
-  //SEG287 [145] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:div32u16u::@2->divr16u#2] -- register_copy 
+  //SEG279 [142] phi (word) divr16u::rem#10 = (word) divr16u::rem#4 [phi:div32u16u::@2->divr16u#2] -- register_copy 
     jsr divr16u
-  //SEG288 [141] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] )
+  //SEG280 [138] (word) divr16u::return#3 ← (word) divr16u::return#0 [ div32u16u::quotient_hi#0 divr16u::return#3 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 divr16u::return#3 ] )
     // (word) divr16u::return#3 = (word) divr16u::return#0  // register copy zp ZP_WORD:8
-  //SEG289 div32u16u::@3
-  //SEG290 [142] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] )
+  //SEG281 div32u16u::@3
+  //SEG282 [139] (word) div32u16u::quotient_lo#0 ← (word) divr16u::return#3 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::quotient_hi#0 div32u16u::quotient_lo#0 ] )
     // (word) div32u16u::quotient_lo#0 = (word) divr16u::return#3  // register copy zp ZP_WORD:8
-  //SEG291 [143] (dword) div32u16u::return#1 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] ) -- vduz1=vwuz2_dword_vwuz3 
+  //SEG283 [140] (dword) div32u16u::return#0 ← (word) div32u16u::quotient_hi#0 dw= (word) div32u16u::quotient_lo#0 [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] ) -- vduz1=vwuz2_dword_vwuz3 
     lda quotient_hi
     sta return+2
     lda quotient_hi+1
@@ -9478,59 +9330,59 @@ div32u16u: {
     sta return
     lda quotient_lo+1
     sta return+1
-  //SEG292 div32u16u::@return
-  //SEG293 [144] return  [ div32u16u::return#1 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#1 ] )
+  //SEG284 div32u16u::@return
+  //SEG285 [141] return  [ div32u16u::return#0 ] ( main:2::sin16s_gen:5::div32u16u:59 [ div32u16u::return#0 ] )
     rts
 }
-//SEG294 divr16u
+//SEG286 divr16u
 divr16u: {
     .label rem = 4
     .label dividend = 6
     .label quotient = 8
     .label return = 8
     .label divisor = 2
-  //SEG295 [146] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
-  //SEG296 [146] phi (byte) divr16u::i#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#0] -- vbuxx=vbuc1 
+  //SEG287 [143] phi from divr16u to divr16u::@1 [phi:divr16u->divr16u::@1]
+  //SEG288 [143] phi (byte) divr16u::i#2 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#0] -- vbuxx=vbuc1 
     ldx #0
-  //SEG297 [146] phi (word) divr16u::quotient#3 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#1] -- vwuz1=vbuc1 
+  //SEG289 [143] phi (word) divr16u::quotient#3 = (byte/signed byte/word/signed word/dword/signed dword) 0 [phi:divr16u->divr16u::@1#1] -- vwuz1=vbuc1 
     txa
     sta quotient
     sta quotient+1
-  //SEG298 [146] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#5 [phi:divr16u->divr16u::@1#2] -- register_copy 
-  //SEG299 [146] phi (word) divr16u::rem#5 = (word) divr16u::rem#10 [phi:divr16u->divr16u::@1#3] -- register_copy 
-  //SEG300 [146] phi from divr16u::@3 to divr16u::@1 [phi:divr16u::@3->divr16u::@1]
-  //SEG301 [146] phi (byte) divr16u::i#2 = (byte) divr16u::i#1 [phi:divr16u::@3->divr16u::@1#0] -- register_copy 
-  //SEG302 [146] phi (word) divr16u::quotient#3 = (word) divr16u::return#0 [phi:divr16u::@3->divr16u::@1#1] -- register_copy 
-  //SEG303 [146] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#0 [phi:divr16u::@3->divr16u::@1#2] -- register_copy 
-  //SEG304 [146] phi (word) divr16u::rem#5 = (word) divr16u::rem#11 [phi:divr16u::@3->divr16u::@1#3] -- register_copy 
-  //SEG305 divr16u::@1
+  //SEG290 [143] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#5 [phi:divr16u->divr16u::@1#2] -- register_copy 
+  //SEG291 [143] phi (word) divr16u::rem#5 = (word) divr16u::rem#10 [phi:divr16u->divr16u::@1#3] -- register_copy 
+  //SEG292 [143] phi from divr16u::@3 to divr16u::@1 [phi:divr16u::@3->divr16u::@1]
+  //SEG293 [143] phi (byte) divr16u::i#2 = (byte) divr16u::i#1 [phi:divr16u::@3->divr16u::@1#0] -- register_copy 
+  //SEG294 [143] phi (word) divr16u::quotient#3 = (word) divr16u::return#0 [phi:divr16u::@3->divr16u::@1#1] -- register_copy 
+  //SEG295 [143] phi (word) divr16u::dividend#3 = (word) divr16u::dividend#0 [phi:divr16u::@3->divr16u::@1#2] -- register_copy 
+  //SEG296 [143] phi (word) divr16u::rem#5 = (word) divr16u::rem#11 [phi:divr16u::@3->divr16u::@1#3] -- register_copy 
+  //SEG297 divr16u::@1
   b1:
-  //SEG306 [147] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG298 [144] (word) divr16u::rem#0 ← (word) divr16u::rem#5 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vwuz1=vwuz1_rol_1 
     asl rem
     rol rem+1
-  //SEG307 [148] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) -- vbuaa=_hi_vwuz1 
+  //SEG299 [145] (byte~) divr16u::$1 ← > (word) divr16u::dividend#3 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$1 ] ) -- vbuaa=_hi_vwuz1 
     lda dividend+1
-  //SEG308 [149] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) -- vbuaa=vbuaa_band_vbuc1 
+  //SEG300 [146] (byte~) divr16u::$2 ← (byte~) divr16u::$1 & (byte/word/signed word/dword/signed dword) 128 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 divr16u::$2 ] ) -- vbuaa=vbuaa_band_vbuc1 
     and #$80
-  //SEG309 [150] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vbuaa_eq_0_then_la1 
+  //SEG301 [147] if((byte~) divr16u::$2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto divr16u::@2 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#0 ] ) -- vbuaa_eq_0_then_la1 
     cmp #0
     beq b2
-  //SEG310 divr16u::@4
-  //SEG311 [151] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) -- vwuz1=vwuz1_bor_vbuc1 
+  //SEG302 divr16u::@4
+  //SEG303 [148] (word) divr16u::rem#1 ← (word) divr16u::rem#0 | (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::dividend#3 divr16u::quotient#3 divr16u::i#2 divr16u::rem#1 ] ) -- vwuz1=vwuz1_bor_vbuc1 
     lda #1
     ora rem
     sta rem
-  //SEG312 [152] phi from divr16u::@1 divr16u::@4 to divr16u::@2 [phi:divr16u::@1/divr16u::@4->divr16u::@2]
-  //SEG313 [152] phi (word) divr16u::rem#6 = (word) divr16u::rem#0 [phi:divr16u::@1/divr16u::@4->divr16u::@2#0] -- register_copy 
-  //SEG314 divr16u::@2
+  //SEG304 [149] phi from divr16u::@1 divr16u::@4 to divr16u::@2 [phi:divr16u::@1/divr16u::@4->divr16u::@2]
+  //SEG305 [149] phi (word) divr16u::rem#6 = (word) divr16u::rem#0 [phi:divr16u::@1/divr16u::@4->divr16u::@2#0] -- register_copy 
+  //SEG306 divr16u::@2
   b2:
-  //SEG315 [153] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG307 [150] (word) divr16u::dividend#0 ← (word) divr16u::dividend#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::quotient#3 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 ] ) -- vwuz1=vwuz1_rol_1 
     asl dividend
     rol dividend+1
-  //SEG316 [154] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1=vwuz1_rol_1 
+  //SEG308 [151] (word) divr16u::quotient#1 ← (word) divr16u::quotient#3 << (byte/signed byte/word/signed word/dword/signed dword) 1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1=vwuz1_rol_1 
     asl quotient
     rol quotient+1
-  //SEG317 [155] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1_lt_vwuz2_then_la1 
+  //SEG309 [152] if((word) divr16u::rem#6<(word) divr16u::divisor#6) goto divr16u::@3 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#1 ] ) -- vwuz1_lt_vwuz2_then_la1 
     lda rem+1
     cmp divisor+1
     bcc b3
@@ -9539,13 +9391,13 @@ divr16u: {
     cmp divisor
     bcc b3
   !:
-  //SEG318 divr16u::@5
-  //SEG319 [156] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ) -- vwuz1=_inc_vwuz1 
+  //SEG310 divr16u::@5
+  //SEG311 [153] (word) divr16u::quotient#2 ← ++ (word) divr16u::quotient#1 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::rem#6 divr16u::quotient#2 ] ) -- vwuz1=_inc_vwuz1 
     inc quotient
     bne !+
     inc quotient+1
   !:
-  //SEG320 [157] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) -- vwuz1=vwuz1_minus_vwuz2 
+  //SEG312 [154] (word) divr16u::rem#2 ← (word) divr16u::rem#6 - (word) divr16u::divisor#6 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::divisor#6 divr16u::i#2 divr16u::dividend#0 divr16u::quotient#2 divr16u::rem#2 ] ) -- vwuz1=vwuz1_minus_vwuz2 
     lda rem
     sec
     sbc divisor
@@ -9553,21 +9405,21 @@ divr16u: {
     lda rem+1
     sbc divisor+1
     sta rem+1
-  //SEG321 [158] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
-  //SEG322 [158] phi (word) divr16u::return#0 = (word) divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy 
-  //SEG323 [158] phi (word) divr16u::rem#11 = (word) divr16u::rem#6 [phi:divr16u::@2/divr16u::@5->divr16u::@3#1] -- register_copy 
-  //SEG324 divr16u::@3
+  //SEG313 [155] phi from divr16u::@2 divr16u::@5 to divr16u::@3 [phi:divr16u::@2/divr16u::@5->divr16u::@3]
+  //SEG314 [155] phi (word) divr16u::return#0 = (word) divr16u::quotient#1 [phi:divr16u::@2/divr16u::@5->divr16u::@3#0] -- register_copy 
+  //SEG315 [155] phi (word) divr16u::rem#11 = (word) divr16u::rem#6 [phi:divr16u::@2/divr16u::@5->divr16u::@3#1] -- register_copy 
+  //SEG316 divr16u::@3
   b3:
-  //SEG325 [159] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuxx=_inc_vbuxx 
+  //SEG317 [156] (byte) divr16u::i#1 ← ++ (byte) divr16u::i#2 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuxx=_inc_vbuxx 
     inx
-  //SEG326 [160] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuxx_neq_vbuc1_then_la1 
+  //SEG318 [157] if((byte) divr16u::i#1!=(byte/signed byte/word/signed word/dword/signed dword) 16) goto divr16u::@1 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 divr16u::divisor#6 divr16u::rem#11 divr16u::dividend#0 divr16u::i#1 ] ) -- vbuxx_neq_vbuc1_then_la1 
     cpx #$10
     bne b1
-  //SEG327 divr16u::@6
-  //SEG328 [161] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  //SEG319 divr16u::@6
+  //SEG320 [158] (word) rem16u#1 ← (word) divr16u::rem#11 [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
     // (word) rem16u#1 = (word) divr16u::rem#11  // register copy zp ZP_WORD:4
-  //SEG329 divr16u::@return
-  //SEG330 [162] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:136 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:140 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
+  //SEG321 divr16u::@return
+  //SEG322 [159] return  [ divr16u::return#0 rem16u#1 ] ( main:2::sin16s_gen:5::div32u16u:59::divr16u:133 [ divr16u::return#0 rem16u#1 ] main:2::sin16s_gen:5::div32u16u:59::divr16u:137 [ div32u16u::quotient_hi#0 divr16u::return#0 rem16u#1 ] )
     rts
 }
 
diff --git a/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.sym b/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.sym
index 7f9c2ca32..59aa569da 100644
--- a/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.sym
+++ b/src/test/java/dk/camelot64/kickc/test/ref/sinusgen.sym
@@ -31,8 +31,8 @@
 (word) div32u16u::quotient_lo
 (word) div32u16u::quotient_lo#0 quotient_lo zp ZP_WORD:8 4.0
 (dword) div32u16u::return
-(dword) div32u16u::return#0 return zp ZP_DWORD:27 4.0
-(dword) div32u16u::return#1 return zp ZP_DWORD:27 1.3333333333333333
+(dword) div32u16u::return#0 return zp ZP_DWORD:27 1.3333333333333333
+(dword) div32u16u::return#2 return zp ZP_DWORD:27 4.0
 (word()) divr16u((word) divr16u::dividend , (word) divr16u::divisor , (word) divr16u::rem)
 (byte~) divr16u::$1 reg byte a 22.0
 (byte~) divr16u::$2 reg byte a 22.0
@@ -120,27 +120,25 @@
 (word) mul_u16_sel::return
 (word) mul_u16_sel::return#0 return zp ZP_WORD:19 4.0
 (word) mul_u16_sel::return#1 return#1 zp ZP_WORD:8 4.0
-(word) mul_u16_sel::return#10 return zp ZP_WORD:19 4.0
-(word) mul_u16_sel::return#11 return#11 zp ZP_WORD:8 4.0
-(word) mul_u16_sel::return#12 return#12 zp ZP_WORD:8 4.0
-(word) mul_u16_sel::return#13 return zp ZP_WORD:19 4.0
-(word) mul_u16_sel::return#14 return zp ZP_WORD:19 1.75
+(word) mul_u16_sel::return#10 return#10 zp ZP_WORD:8 4.0
+(word) mul_u16_sel::return#11 return zp ZP_WORD:19 4.0
+(word) mul_u16_sel::return#12 return zp ZP_WORD:19 1.714285714285714
+(word) mul_u16_sel::return#2 return zp ZP_WORD:19 4.0
 (byte) mul_u16_sel::select
-(byte) mul_u16_sel::select#6 reg byte x 0.3333333333333333
+(byte) mul_u16_sel::select#5 reg byte x 0.3333333333333333
 (word) mul_u16_sel::v1
 (word) mul_u16_sel::v1#0 v1 zp ZP_WORD:8 2.0
 (word) mul_u16_sel::v1#1 v1 zp ZP_WORD:8 2.0
 (word) mul_u16_sel::v1#2 v1 zp ZP_WORD:8 4.0
 (word) mul_u16_sel::v1#3 v1 zp ZP_WORD:8 2.0
 (word) mul_u16_sel::v1#4 v1 zp ZP_WORD:8 2.0
-(word) mul_u16_sel::v1#5 v1 zp ZP_WORD:8 4.0
-(word) mul_u16_sel::v1#6 v1 zp ZP_WORD:8 14.0
+(word) mul_u16_sel::v1#5 v1 zp ZP_WORD:8 12.0
 (word) mul_u16_sel::v2
 (word) mul_u16_sel::v2#0 v2 zp ZP_WORD:19 4.0
 (word) mul_u16_sel::v2#1 v2 zp ZP_WORD:19 4.0
 (word) mul_u16_sel::v2#3 v2 zp ZP_WORD:19 4.0
 (word) mul_u16_sel::v2#4 v2 zp ZP_WORD:19 4.0
-(word) mul_u16_sel::v2#6 v2 zp ZP_WORD:19 5.0
+(word) mul_u16_sel::v2#5 v2 zp ZP_WORD:19 5.0
 (void()) print_byte((byte) print_byte::b)
 (byte~) print_byte::$0 reg byte a 4.0
 (byte~) print_byte::$2 reg byte a 4.0
@@ -193,8 +191,7 @@
 (label) sin16s::@10
 (label) sin16s::@11
 (label) sin16s::@12
-(label) sin16s::@13
-(label) sin16s::@16
+(label) sin16s::@15
 (label) sin16s::@2
 (label) sin16s::@3
 (label) sin16s::@4
@@ -204,7 +201,7 @@
 (label) sin16s::@9
 (label) sin16s::@return
 (byte) sin16s::isUpper
-(byte) sin16s::isUpper#10 isUpper zp ZP_BYTE:14 0.05555555555555555
+(byte) sin16s::isUpper#2 isUpper zp ZP_BYTE:14 0.06060606060606061
 (signed word) sin16s::return
 (signed word) sin16s::return#0 return zp ZP_WORD:6 22.0
 (signed word) sin16s::return#1 return zp ZP_WORD:6 5.0
@@ -212,7 +209,7 @@
 (signed word) sin16s::sinx
 (signed word) sin16s::sinx#1 sinx zp ZP_WORD:6 4.0
 (word) sin16s::usinx
-(word) sin16s::usinx#0 usinx zp ZP_WORD:6 0.26666666666666666
+(word) sin16s::usinx#0 usinx zp ZP_WORD:6 0.3333333333333333
 (word) sin16s::usinx#1 usinx zp ZP_WORD:6 1.0
 (dword) sin16s::x
 (dword) sin16s::x#0 x zp ZP_DWORD:15 8.5
@@ -231,7 +228,7 @@
 (word) sin16s::x4
 (word) sin16s::x4#0 x4 zp ZP_WORD:8 4.0
 (word) sin16s::x5
-(word) sin16s::x5#0 x5 zp ZP_WORD:8 4.0
+(word) sin16s::x5#0 x5 zp ZP_WORD:19 4.0
 (word) sin16s::x5_128
 (word) sin16s::x5_128#0 x5_128 zp ZP_WORD:19 4.0
 (void()) sin16s_gen((signed word*) sin16s_gen::sintab , (word) sin16s_gen::wavelength)
@@ -258,18 +255,18 @@ zp ZP_WORD:4 [ print_str::str#3 print_str::str#5 print_str::str#0 sin16s_gen::i#
 zp ZP_WORD:6 [ print_sword::w#3 print_sword::w#1 print_sword::w#0 main::sw#0 sin16s::return#1 sin16s::return#5 sin16s::sinx#1 sin16s::usinx#1 sin16s::return#0 sin16s_gen::$1 sin16s::usinx#0 divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ]
 reg byte x [ print_byte::b#2 print_byte::b#0 print_byte::b#1 ]
 reg byte a [ print_char::ch#3 print_char::ch#1 print_char::ch#2 ]
-zp ZP_WORD:8 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 mul_u16_sel::v1#6 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#5 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 sin16s::x5#0 mul_u16_sel::return#1 mul_u16_sel::return#11 mul_u16_sel::return#12 divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ]
+zp ZP_WORD:8 [ char_cursor#33 char_cursor#46 char_cursor#43 char_cursor#51 char_cursor#48 char_cursor#49 char_cursor#2 char_cursor#12 char_cursor#1 mul_u16_sel::v1#5 mul_u16_sel::v1#3 mul_u16_sel::v1#4 mul_u16_sel::v1#0 mul_u16_sel::v1#1 mul_u16_sel::v1#2 sin16s::x3#0 sin16s::x2#0 sin16s::x4#0 mul_u16_sel::return#1 mul_u16_sel::return#10 divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 divr16u::return#2 divr16u::return#3 div32u16u::quotient_lo#0 ]
 zp ZP_DWORD:10 [ sin16s_gen::x#2 sin16s_gen::x#1 ]
-zp ZP_BYTE:14 [ sin16s::isUpper#10 ]
+zp ZP_BYTE:14 [ sin16s::isUpper#2 ]
 zp ZP_DWORD:15 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 sin16s::$6 mul16u::res#2 mul16u::res#6 mul16u::res#1 mul16u::return#2 mul_u16_sel::$0 mul_u16_sel::$1 ]
-zp ZP_WORD:19 [ mul_u16_sel::v2#6 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 mul_u16_sel::return#0 mul_u16_sel::return#14 mul_u16_sel::return#10 sin16s::x3_6#0 mul_u16_sel::return#13 sin16s::x5_128#0 div32u16u::quotient_hi#0 ]
-reg byte x [ mul_u16_sel::select#6 ]
+zp ZP_WORD:19 [ mul_u16_sel::v2#5 mul_u16_sel::v2#3 mul_u16_sel::v2#4 mul_u16_sel::v2#0 mul_u16_sel::v2#1 mul16u::b#0 mul_u16_sel::return#0 mul_u16_sel::return#12 mul_u16_sel::return#2 sin16s::x3_6#0 mul_u16_sel::return#11 sin16s::x5#0 sin16s::x5_128#0 div32u16u::quotient_hi#0 ]
+reg byte x [ mul_u16_sel::select#5 ]
 zp ZP_WORD:21 [ mul16u::a#2 mul16u::a#1 mul16u::a#0 ]
 zp ZP_DWORD:23 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ]
 reg byte x [ divr16u::i#2 divr16u::i#1 ]
 reg byte a [ print_byte::$0 ]
 reg byte a [ print_byte::$2 ]
-zp ZP_DWORD:27 [ div32u16u::return#0 sin16s_gen::step#0 div32u16u::return#1 ]
+zp ZP_DWORD:27 [ div32u16u::return#2 sin16s_gen::step#0 div32u16u::return#0 ]
 zp ZP_WORD:31 [ sin16s::x1#0 ]
 reg byte a [ mul16u::$1 ]
 reg byte a [ divr16u::$1 ]