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Added missing fragments

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This commit is contained in:
jespergravgaard 2018-03-22 22:30:16 +01:00
parent 71e4e5d22d
commit 7922d0f21a
16 changed files with 128 additions and 121 deletions
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18
src/main/java/dk/camelot64/kickc/fragment/asm/vduz1=vduz2_rol_vbuyy.asm Normal file
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@ -0,0 +1,18 @@
lda {z2}
sta {z1}
lda {z2}+1
sta {z1}+1
lda {z2}+2
sta {z1}+2
lda {z2}+3
sta {z1}+3
cpy #0
beq !e+
!:
asl {z1}
rol {z1}+1
rol {z1}+2
rol {z1}+3
dey
bne !-
!e:

8
src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz1_rol_vbuxx.asm Normal file
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@ -0,0 +1,8 @@
cpx #0
beq !e+
!:
asl {z1}
rol {z1}+1
dex
bne !-
!e:

8
src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz1_rol_vbuyy.asm Normal file
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@ -0,0 +1,8 @@
cpy #0
beq !e+
!:
asl {z1}
rol {z1}+1
dey
bne !-
!e:

12
src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz2_rol_vbuxx.asm Normal file
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@ -0,0 +1,12 @@
lda {z2}
sta {z1}
lda {z2}+1
sta {z1}+1
cpx #0
beq !e+
!:
asl {z1}
rol {z1}+1
dex
bne !-
!e:

12
src/main/java/dk/camelot64/kickc/fragment/asm/vwuz1=vwuz2_rol_vbuyy.asm Normal file
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@ -0,0 +1,12 @@
lda {z2}
sta {z1}
lda {z2}+1
sta {z1}+1
cpy #0
beq !e+
!:
asl {z1}
rol {z1}+1
dey
bne !-
!e:

2
src/test/java/dk/camelot64/kickc/test/kc/chargen-analysis.kc
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@ -71,7 +71,7 @@ void plot_chargen(byte pos, byte ch, byte shift) {
asm { sei }
byte* chargen = CHARGEN+(word)ch<<3;
if(shift!=0) {
chargen = chargen + $1000;
chargen = chargen + $0800;
}
*PROCPORT = $32;
byte* sc = SCREEN+40+1+mul8u(pos, 10);

4
src/test/java/dk/camelot64/kickc/test/ref/chargen-analysis.asm
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@ -236,10 +236,10 @@ plot_chargen: {
beq b1
clc
lda chargen
adc #<$1000
adc #<$800
sta chargen
lda chargen+1
adc #>$1000
adc #>$800
sta chargen+1
b1:
lda #$32

2
src/test/java/dk/camelot64/kickc/test/ref/chargen-analysis.cfg
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@ -153,7 +153,7 @@ plot_chargen: scope:[plot_chargen] from main::@2 main::@22
[78] if((byte) plot_chargen::shift#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto plot_chargen::@1 [ plot_chargen::pos#2 plot_chargen::chargen#0 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] )
to:plot_chargen::@5
plot_chargen::@5: scope:[plot_chargen] from plot_chargen
[79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 4096 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] )
[79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 2048 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] )
to:plot_chargen::@1
plot_chargen::@1: scope:[plot_chargen] from plot_chargen plot_chargen::@5
[80] (byte*) plot_chargen::chargen#5 ← phi( plot_chargen/(byte*) plot_chargen::chargen#0 plot_chargen::@5/(byte*) plot_chargen::chargen#1 ) [ plot_chargen::pos#2 plot_chargen::chargen#5 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#5 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#5 ] )

32
src/test/java/dk/camelot64/kickc/test/ref/chargen-analysis.log
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@ -72,7 +72,7 @@ void plot_chargen(byte pos, byte ch, byte shift) {
asm { sei }
byte* chargen = CHARGEN+(word)ch<<3;
if(shift!=0) {
chargen = chargen + $1000;
chargen = chargen + $0800;
}
*PROCPORT = $32;
byte* sc = SCREEN+40+1+mul8u(pos, 10);
@ -740,7 +740,7 @@ proc (void()) plot_chargen((byte) plot_chargen::pos , (byte) plot_chargen::ch ,
(boolean~) plot_chargen::$3 ← (byte) plot_chargen::shift != (byte/signed byte/word/signed word/dword/signed dword) 0
(boolean~) plot_chargen::$4 ← ! (boolean~) plot_chargen::$3
if((boolean~) plot_chargen::$4) goto plot_chargen::@1
(byte*~) plot_chargen::$5 ← (byte*) plot_chargen::chargen + (word/signed word/dword/signed dword) 4096
(byte*~) plot_chargen::$5 ← (byte*) plot_chargen::chargen + (word/signed word/dword/signed dword) 2048
(byte*) plot_chargen::chargen ← (byte*~) plot_chargen::$5
plot_chargen::@1:
*((byte*) PROCPORT) ← (byte/signed byte/word/signed word/dword/signed dword) 50
@ -1654,7 +1654,7 @@ plot_chargen::@1: scope:[plot_chargen] from plot_chargen plot_chargen::@5
(byte) plot_chargen::y ← (byte/signed byte/word/signed word/dword/signed dword) 0
to:plot_chargen::@2
plot_chargen::@5: scope:[plot_chargen] from plot_chargen
(byte*~) plot_chargen::$5 ← (byte*) plot_chargen::chargen + (word/signed word/dword/signed dword) 4096
(byte*~) plot_chargen::$5 ← (byte*) plot_chargen::chargen + (word/signed word/dword/signed dword) 2048
(byte*) plot_chargen::chargen ← (byte*~) plot_chargen::$5
to:plot_chargen::@1
plot_chargen::@2: scope:[plot_chargen] from plot_chargen::@1 plot_chargen::@7
@ -2281,7 +2281,7 @@ plot_chargen::@5: scope:[plot_chargen] from plot_chargen
(byte) plot_chargen::pos#4 ← phi( plot_chargen/(byte) plot_chargen::pos#3 )
(byte*) SCREEN#10 ← phi( plot_chargen/(byte*) SCREEN#9 )
(byte*) plot_chargen::chargen#2 ← phi( plot_chargen/(byte*) plot_chargen::chargen#0 )
(byte*~) plot_chargen::$5 ← (byte*) plot_chargen::chargen#2 + (word/signed word/dword/signed dword) 4096
(byte*~) plot_chargen::$5 ← (byte*) plot_chargen::chargen#2 + (word/signed word/dword/signed dword) 2048
(byte*) plot_chargen::chargen#1 ← (byte*~) plot_chargen::$5
to:plot_chargen::@1
plot_chargen::@2: scope:[plot_chargen] from plot_chargen::@7 plot_chargen::@9
@ -3814,7 +3814,7 @@ plot_chargen: scope:[plot_chargen] from main::@2 main::@22
[78] if((byte) plot_chargen::shift#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto plot_chargen::@1 [ plot_chargen::pos#2 plot_chargen::chargen#0 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] )
to:plot_chargen::@5
plot_chargen::@5: scope:[plot_chargen] from plot_chargen
[79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 4096 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] )
[79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 2048 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] )
to:plot_chargen::@1
plot_chargen::@1: scope:[plot_chargen] from plot_chargen plot_chargen::@5
[80] (byte*) plot_chargen::chargen#5 ← phi( plot_chargen/(byte*) plot_chargen::chargen#0 plot_chargen::@5/(byte*) plot_chargen::chargen#1 ) [ plot_chargen::pos#2 plot_chargen::chargen#5 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#5 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#5 ] )
@ -4967,13 +4967,13 @@ plot_chargen: {
jmp b5
//SEG178 plot_chargen::@5
b5:
//SEG179 [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 4096 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) -- pbuz1=pbuz1_plus_vwuc1
//SEG179 [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 2048 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) -- pbuz1=pbuz1_plus_vwuc1
clc
lda chargen
adc #<$1000
adc #<$800
sta chargen
lda chargen+1
adc #>$1000
adc #>$800
sta chargen+1
//SEG180 [80] phi from plot_chargen plot_chargen::@5 to plot_chargen::@1 [phi:plot_chargen/plot_chargen::@5->plot_chargen::@1]
b1_from_plot_chargen:
@ -5327,7 +5327,7 @@ Removing always clobbered register reg byte a as potential for zp ZP_BYTE:6 [ ma
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:7 [ main::ch#2 main::ch#1 ]
Statement [76] (word~) plot_chargen::$1 ← (word~) plot_chargen::$0 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$1 ] ) always clobbers reg byte a
Statement [77] (byte*) plot_chargen::chargen#0 ← (const byte*) CHARGEN#0 + (word~) plot_chargen::$1 [ plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] ) always clobbers reg byte a
Statement [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 4096 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) always clobbers reg byte a
Statement [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 2048 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) always clobbers reg byte a
Statement [81] *((const byte*) PROCPORT#0) ← (byte/signed byte/word/signed word/dword/signed dword) 50 [ plot_chargen::pos#2 plot_chargen::chargen#5 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#5 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#5 ] ) always clobbers reg byte a
Statement [84] (word) mul8u::return#2 ← (word) mul8u::res#2 [ plot_chargen::chargen#5 mul8u::return#2 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::chargen#5 mul8u::return#2 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::chargen#5 mul8u::return#2 ] ) always clobbers reg byte a
Statement [85] (word~) plot_chargen::$8 ← (word) mul8u::return#2 [ plot_chargen::chargen#5 plot_chargen::$8 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::chargen#5 plot_chargen::$8 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::chargen#5 plot_chargen::$8 ] ) always clobbers reg byte a
@ -5363,7 +5363,7 @@ Statement [8] if((byte*) main::sc#1<(const byte*) SCREEN#0+(word/signed word/dwo
Statement [75] (word~) plot_chargen::$0 ← ((word)) (byte) plot_chargen::ch#2 [ plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$0 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$0 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$0 ] ) always clobbers reg byte a
Statement [76] (word~) plot_chargen::$1 ← (word~) plot_chargen::$0 << (byte/signed byte/word/signed word/dword/signed dword) 3 [ plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::$1 ] ) always clobbers reg byte a
Statement [77] (byte*) plot_chargen::chargen#0 ← (const byte*) CHARGEN#0 + (word~) plot_chargen::$1 [ plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::shift#2 plot_chargen::pos#2 plot_chargen::chargen#0 ] ) always clobbers reg byte a
Statement [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 4096 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) always clobbers reg byte a
Statement [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 2048 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) always clobbers reg byte a
Statement [81] *((const byte*) PROCPORT#0) ← (byte/signed byte/word/signed word/dword/signed dword) 50 [ plot_chargen::pos#2 plot_chargen::chargen#5 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#5 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#5 ] ) always clobbers reg byte a
Statement [84] (word) mul8u::return#2 ← (word) mul8u::res#2 [ plot_chargen::chargen#5 mul8u::return#2 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::chargen#5 mul8u::return#2 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::chargen#5 mul8u::return#2 ] ) always clobbers reg byte a
Statement [85] (word~) plot_chargen::$8 ← (word) mul8u::return#2 [ plot_chargen::chargen#5 plot_chargen::$8 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::chargen#5 plot_chargen::$8 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::chargen#5 plot_chargen::$8 ] ) always clobbers reg byte a
@ -6030,13 +6030,13 @@ plot_chargen: {
jmp b5
//SEG178 plot_chargen::@5
b5:
//SEG179 [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 4096 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) -- pbuz1=pbuz1_plus_vwuc1
//SEG179 [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 2048 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) -- pbuz1=pbuz1_plus_vwuc1
clc
lda chargen
adc #<$1000
adc #<$800
sta chargen
lda chargen+1
adc #>$1000
adc #>$800
sta chargen+1
//SEG180 [80] phi from plot_chargen plot_chargen::@5 to plot_chargen::@1 [phi:plot_chargen/plot_chargen::@5->plot_chargen::@1]
b1_from_plot_chargen:
@ -7314,13 +7314,13 @@ plot_chargen: {
cpy #0
beq b1
//SEG178 plot_chargen::@5
//SEG179 [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 4096 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) -- pbuz1=pbuz1_plus_vwuc1
//SEG179 [79] (byte*) plot_chargen::chargen#1 ← (byte*) plot_chargen::chargen#0 + (word/signed word/dword/signed dword) 2048 [ plot_chargen::pos#2 plot_chargen::chargen#1 ] ( main:2::plot_chargen:19 [ main::i#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] main:2::plot_chargen:64 [ main::cur_pos#12 main::shift#10 main::ch#2 plot_chargen::pos#2 plot_chargen::chargen#1 ] ) -- pbuz1=pbuz1_plus_vwuc1
clc
lda chargen
adc #<$1000
adc #<$800
sta chargen
lda chargen+1
adc #>$1000
adc #>$800
sta chargen+1
//SEG180 [80] phi from plot_chargen plot_chargen::@5 to plot_chargen::@1 [phi:plot_chargen/plot_chargen::@5->plot_chargen::@1]
//SEG181 [80] phi (byte*) plot_chargen::chargen#5 = (byte*) plot_chargen::chargen#0 [phi:plot_chargen/plot_chargen::@5->plot_chargen::@1#0] -- register_copy

8
src/test/java/dk/camelot64/kickc/test/ref/sinusgen16.log
View File

@ -6869,8 +6869,7 @@ Removing always clobbered register reg byte a as potential for zp ZP_BYTE:33 [ m
Statement [115] (word) mul16u::b#0 ← (word) mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a
Statement [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#2 ] ) always clobbers reg byte a
Statement [118] (dword~) mulu16_sel::$0 ← (dword) mul16u::return#2 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] ) always clobbers reg byte a
Statement [119] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a reg byte x
Removing always clobbered register reg byte x as potential for zp ZP_BYTE:22 [ sin16s::isUpper#2 ]
Statement [119] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a
Statement [120] (word) mulu16_sel::return#12 ← > (dword~) mulu16_sel::$1 [ mulu16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] ) always clobbers reg byte a
Statement [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a
Statement [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a
@ -6941,14 +6940,13 @@ Statement [104] (word) mulu16_sel::return#11 ← (word) mulu16_sel::return#12 [
Statement [105] (word) sin16s::x5#0 ← (word) mulu16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ) always clobbers reg byte a
Statement [106] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) always clobbers reg byte a reg byte y
Statement [107] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) always clobbers reg byte a
Statement [108] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) always clobbers reg byte a
Statement [109] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) always clobbers reg byte a
Statement [112] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:64 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) always clobbers reg byte a
Statement [114] (word) mul16u::a#1 ← (word) mulu16_sel::v1#5 [ mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] ) always clobbers reg byte a
Statement [115] (word) mul16u::b#0 ← (word) mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a
Statement [117] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#2 ] ) always clobbers reg byte a
Statement [118] (dword~) mulu16_sel::$0 ← (dword) mul16u::return#2 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] ) always clobbers reg byte a
Statement [119] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a reg byte x
Statement [119] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a
Statement [120] (word) mulu16_sel::return#12 ← > (dword~) mulu16_sel::$1 [ mulu16_sel::return#12 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] ) always clobbers reg byte a
Statement [122] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a
Statement [124] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:5::sin16s:64::mulu16_sel:83::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:88::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:92::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:98::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:64::mulu16_sel:103::mul16u:116 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a
@ -6976,7 +6974,7 @@ Potential registers zp ZP_WORD:12 [ print_cls::sc#2 print_cls::sc#1 ] : zp ZP_WO
Potential registers zp ZP_DWORD:14 [ sin16s_gen::x#2 sin16s_gen::x#1 ] : zp ZP_DWORD:14 ,
Potential registers zp ZP_WORD:18 [ sin16s_gen::sintab#2 sin16s_gen::sintab#0 ] : zp ZP_WORD:18 ,
Potential registers zp ZP_WORD:20 [ sin16s_gen::i#2 sin16s_gen::i#1 ] : zp ZP_WORD:20 ,
Potential registers zp ZP_BYTE:22 [ sin16s::isUpper#2 ] : zp ZP_BYTE:22 ,
Potential registers zp ZP_BYTE:22 [ sin16s::isUpper#2 ] : zp ZP_BYTE:22 , reg byte x ,
Potential registers zp ZP_DWORD:23 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] : zp ZP_DWORD:23 ,
Potential registers zp ZP_WORD:27 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] : zp ZP_WORD:27 ,
Potential registers zp ZP_WORD:29 [ mulu16_sel::v1#5 mulu16_sel::v1#3 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 ] : zp ZP_WORD:29 ,

13
src/test/java/dk/camelot64/kickc/test/ref/sinusgen16b.log
View File

@ -8711,9 +8711,7 @@ Removing always clobbered register reg byte a as potential for zp ZP_BYTE:68 [ s
Statement [118] (word) mul16u::b#0 ← (word) mulu16_sel::v2#10 [ mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a
Statement [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mulu16_sel::select#10 mul16u::return#2 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mul16u::return#2 ] ) always clobbers reg byte a
Statement [121] (dword~) mulu16_sel::$0 ← (dword) mul16u::return#2 [ mulu16_sel::select#10 mulu16_sel::$0 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mulu16_sel::$0 ] ) always clobbers reg byte a
Statement [122] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#10 [ mulu16_sel::$1 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a reg byte x
Removing always clobbered register reg byte x as potential for zp ZP_BYTE:25 [ sin16sb::isUpper#2 ]
Removing always clobbered register reg byte x as potential for zp ZP_BYTE:68 [ sin16s::isUpper#2 ]
Statement [122] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#10 [ mulu16_sel::$1 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a
Statement [123] (word) mulu16_sel::return#17 ← > (dword~) mulu16_sel::$1 [ mulu16_sel::return#17 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::return#17 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::return#17 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::return#17 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::return#17 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#17 ] ) always clobbers reg byte a
Statement [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a
Statement [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a
@ -8772,7 +8770,6 @@ Statement [212] (word) mulu16_sel::return#16 ← (word) mulu16_sel::return#17 [
Statement [213] (word) sin16s::x5#0 ← (word) mulu16_sel::return#16 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ) always clobbers reg byte a
Statement [214] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) always clobbers reg byte a reg byte y
Statement [215] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) always clobbers reg byte a
Statement [216] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) always clobbers reg byte a
Statement [217] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) always clobbers reg byte a
Statement [220] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) always clobbers reg byte a
Statement [11] (signed word) main::sw#0 ← *((signed word*) main::st1#2) - *((signed word*) main::st2#2) [ main::st1#2 main::st2#2 char_cursor#49 main::i#2 main::sw#0 ] ( main:2 [ main::st1#2 main::st2#2 char_cursor#49 main::i#2 main::sw#0 ] ) always clobbers reg byte a reg byte y
@ -8826,14 +8823,13 @@ Statement [107] (word) mulu16_sel::return#11 ← (word) mulu16_sel::return#17 [
Statement [108] (word) sin16sb::x5#0 ← (word) mulu16_sel::return#11 [ sin16sb::isUpper#2 sin16sb::usinx#0 sin16sb::x5#0 ] ( main:2::sin16s_genb:7::sin16sb:68 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 sin16sb::x5#0 ] ) always clobbers reg byte a
Statement [109] (word) sin16sb::x5_128#0 ← (word) sin16sb::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16sb::isUpper#2 sin16sb::usinx#0 sin16sb::x5_128#0 ] ( main:2::sin16s_genb:7::sin16sb:68 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 sin16sb::x5_128#0 ] ) always clobbers reg byte a reg byte y
Statement [110] (word) sin16sb::usinx#1 ← (word) sin16sb::usinx#0 + (word) sin16sb::x5_128#0 [ sin16sb::isUpper#2 sin16sb::usinx#1 ] ( main:2::sin16s_genb:7::sin16sb:68 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#1 ] ) always clobbers reg byte a
Statement [111] if((byte) sin16sb::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16sb::@15 [ sin16sb::usinx#1 ] ( main:2::sin16s_genb:7::sin16sb:68 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::usinx#1 ] ) always clobbers reg byte a
Statement [112] (signed word) sin16sb::sinx#1 ← - (signed word)(word) sin16sb::usinx#1 [ sin16sb::sinx#1 ] ( main:2::sin16s_genb:7::sin16sb:68 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::sinx#1 ] ) always clobbers reg byte a
Statement [115] (signed word~) sin16sb::return#5 ← (signed word)(word) sin16sb::usinx#1 [ sin16sb::return#5 ] ( main:2::sin16s_genb:7::sin16sb:68 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::return#5 ] ) always clobbers reg byte a
Statement [117] (word) mul16u::a#1 ← (word) mulu16_sel::v1#10 [ mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v2#10 mulu16_sel::select#10 mul16u::a#1 ] ) always clobbers reg byte a
Statement [118] (word) mul16u::b#0 ← (word) mulu16_sel::v2#10 [ mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a
Statement [120] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mulu16_sel::select#10 mul16u::return#2 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mul16u::return#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mul16u::return#2 ] ) always clobbers reg byte a
Statement [121] (dword~) mulu16_sel::$0 ← (dword) mul16u::return#2 [ mulu16_sel::select#10 mulu16_sel::$0 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mulu16_sel::$0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mulu16_sel::$0 ] ) always clobbers reg byte a
Statement [122] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#10 [ mulu16_sel::$1 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a reg byte x
Statement [122] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#10 [ mulu16_sel::$1 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::$1 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a
Statement [123] (word) mulu16_sel::return#17 ← > (dword~) mulu16_sel::$1 [ mulu16_sel::return#17 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::return#17 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::return#17 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::return#17 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::return#17 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#17 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#17 ] ) always clobbers reg byte a
Statement [125] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a
Statement [127] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:86::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:91::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:95::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::x3#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:101::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::x1#0 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_genb:7::sin16sb:68::mulu16_sel:106::mul16u:119 [ sin16s_genb::step#0 sin16s_genb::x#2 sin16s_genb::sintab#2 sin16s_genb::i#2 sin16sb::isUpper#2 sin16sb::usinx#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:191::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:196::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:200::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:206::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:5::sin16s:172::mulu16_sel:211::mul16u:119 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#10 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a
@ -8890,7 +8886,6 @@ Statement [212] (word) mulu16_sel::return#16 ← (word) mulu16_sel::return#17 [
Statement [213] (word) sin16s::x5#0 ← (word) mulu16_sel::return#16 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ) always clobbers reg byte a
Statement [214] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) always clobbers reg byte a reg byte y
Statement [215] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) always clobbers reg byte a
Statement [216] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) always clobbers reg byte a
Statement [217] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) always clobbers reg byte a
Statement [220] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:5::sin16s:172 [ divr16u::rem#11 sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) always clobbers reg byte a
Potential registers zp ZP_WORD:2 [ main::st1#2 main::st1#1 ] : zp ZP_WORD:2 ,
@ -8905,7 +8900,7 @@ Potential registers zp ZP_WORD:15 [ print_cls::sc#2 print_cls::sc#1 ] : zp ZP_WO
Potential registers zp ZP_DWORD:17 [ sin16s_genb::x#2 sin16s_genb::x#1 ] : zp ZP_DWORD:17 ,
Potential registers zp ZP_WORD:21 [ sin16s_genb::sintab#2 sin16s_genb::sintab#0 ] : zp ZP_WORD:21 ,
Potential registers zp ZP_WORD:23 [ sin16s_genb::i#2 sin16s_genb::i#1 ] : zp ZP_WORD:23 ,
Potential registers zp ZP_BYTE:25 [ sin16sb::isUpper#2 ] : zp ZP_BYTE:25 ,
Potential registers zp ZP_BYTE:25 [ sin16sb::isUpper#2 ] : zp ZP_BYTE:25 , reg byte x ,
Potential registers zp ZP_WORD:26 [ sin16sb::x#6 sin16sb::x#4 sin16sb::x#0 sin16sb::x#1 sin16sb::x#2 ] : zp ZP_WORD:26 ,
Potential registers zp ZP_WORD:28 [ sin16sb::return#1 sin16sb::return#5 sin16sb::sinx#1 ] : zp ZP_WORD:28 ,
Potential registers zp ZP_WORD:30 [ mulu16_sel::v1#10 mulu16_sel::v1#3 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#8 mulu16_sel::v1#9 mulu16_sel::v1#5 mulu16_sel::v1#6 mulu16_sel::v1#7 ] : zp ZP_WORD:30 ,
@ -8924,7 +8919,7 @@ Potential registers zp ZP_BYTE:59 [ divr16u::i#2 divr16u::i#1 ] : zp ZP_BYTE:59
Potential registers zp ZP_DWORD:60 [ sin16s_gen::x#2 sin16s_gen::x#1 ] : zp ZP_DWORD:60 ,
Potential registers zp ZP_WORD:64 [ sin16s_gen::sintab#2 sin16s_gen::sintab#0 ] : zp ZP_WORD:64 ,
Potential registers zp ZP_WORD:66 [ sin16s_gen::i#2 sin16s_gen::i#1 ] : zp ZP_WORD:66 ,
Potential registers zp ZP_BYTE:68 [ sin16s::isUpper#2 ] : zp ZP_BYTE:68 ,
Potential registers zp ZP_BYTE:68 [ sin16s::isUpper#2 ] : zp ZP_BYTE:68 , reg byte x ,
Potential registers zp ZP_DWORD:69 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] : zp ZP_DWORD:69 ,
Potential registers zp ZP_WORD:73 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] : zp ZP_WORD:73 ,
Potential registers zp ZP_WORD:75 [ main::sw#0 ] : zp ZP_WORD:75 ,

30
src/test/java/dk/camelot64/kickc/test/ref/sinusgen8.log
View File

@ -6361,16 +6361,7 @@ Statement [114] (word) mul8u::return#2 ← (word) mul8u::res#2 [ mulu8_sel::sele
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:24 [ mulu8_sel::select#5 ]
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:55 [ sin8s::usinx#0 ]
Statement [115] (word~) mulu8_sel::$0 ← (word) mul8u::return#2 [ mulu8_sel::select#5 mulu8_sel::$0 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] ) always clobbers reg byte a
Potential register analysis [116] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuxx allocation: reg byte x [ mulu8_sel::select#5 ] zp ZP_WORD:66 [ mulu8_sel::$1 ] zp ZP_WORD:64 [ mulu8_sel::$0 ]
Potential register analysis [116] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuyy allocation: reg byte y [ mulu8_sel::select#5 ] zp ZP_WORD:66 [ mulu8_sel::$1 ] zp ZP_WORD:64 [ mulu8_sel::$0 ]
MISSING FRAGMENTS
vwuz1=vwuz2_rol_vbuxx
vwuz1=vwuz2_rol_vbuyy
Statement [116] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a reg byte y
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:17 [ sin8s::isUpper#10 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:48 [ sin8s::x1#0 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:52 [ sin8s::x3#0 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:55 [ sin8s::usinx#0 ]
Statement [116] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a
Statement [117] (byte) mulu8_sel::return#12 ← > (word~) mulu8_sel::$1 [ mulu8_sel::return#12 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::return#12 ] ) always clobbers reg byte a
Statement [119] (word) mul8u::mb#0 ← ((word)) (byte) mul8u::b#0 [ mul8u::a#1 mul8u::mb#0 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] ) always clobbers reg byte a
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:25 [ mul8u::a#2 mul8u::a#1 mul8u::a#0 ]
@ -6409,12 +6400,7 @@ Statement [101] (byte) sin8s::usinx#1 ← (byte) sin8s::usinx#0 + (byte) sin8s::
Statement [106] (signed byte) sin8s::sinx#1 ← - (signed byte)(byte) sin8s::usinx#4 [ sin8s::sinx#1 ] ( main:2::sin8s_gen:5::sin8s:58 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::sinx#1 ] ) always clobbers reg byte a
Statement [114] (word) mul8u::return#2 ← (word) mul8u::res#2 [ mulu8_sel::select#5 mul8u::return#2 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::return#2 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::return#2 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::return#2 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::return#2 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::return#2 ] ) always clobbers reg byte a
Statement [115] (word~) mulu8_sel::$0 ← (word) mul8u::return#2 [ mulu8_sel::select#5 mulu8_sel::$0 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] ) always clobbers reg byte a
Potential register analysis [116] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuxx allocation: reg byte x [ mulu8_sel::select#5 ] zp ZP_WORD:66 [ mulu8_sel::$1 ] zp ZP_WORD:64 [ mulu8_sel::$0 ]
Potential register analysis [116] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuyy allocation: reg byte y [ mulu8_sel::select#5 ] zp ZP_WORD:66 [ mulu8_sel::$1 ] zp ZP_WORD:64 [ mulu8_sel::$0 ]
MISSING FRAGMENTS
vwuz1=vwuz2_rol_vbuxx
vwuz1=vwuz2_rol_vbuyy
Statement [116] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a reg byte y
Statement [116] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a
Statement [117] (byte) mulu8_sel::return#12 ← > (word~) mulu8_sel::$1 [ mulu8_sel::return#12 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::return#12 ] ) always clobbers reg byte a
Statement [119] (word) mul8u::mb#0 ← ((word)) (byte) mul8u::b#0 [ mul8u::a#1 mul8u::mb#0 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] ) always clobbers reg byte a
Statement [123] (byte~) mul8u::$1 ← (byte) mul8u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] ( main:2::sin8s_gen:5::sin8s:58::mulu8_sel:77::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:82::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:86::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:92::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] main:2::sin8s_gen:5::sin8s:58::mulu8_sel:97::mul8u:113 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] ) always clobbers reg byte a
@ -6435,7 +6421,7 @@ Potential registers zp ZP_WORD:9 [ print_cls::sc#2 print_cls::sc#1 ] : zp ZP_WOR
Potential registers zp ZP_WORD:11 [ sin8s_gen::x#2 sin8s_gen::x#1 ] : zp ZP_WORD:11 ,
Potential registers zp ZP_WORD:13 [ sin8s_gen::sintab#2 sin8s_gen::sintab#0 ] : zp ZP_WORD:13 ,
Potential registers zp ZP_WORD:15 [ sin8s_gen::i#2 sin8s_gen::i#1 ] : zp ZP_WORD:15 ,
Potential registers zp ZP_BYTE:17 [ sin8s::isUpper#10 ] : zp ZP_BYTE:17 , reg byte x ,
Potential registers zp ZP_BYTE:17 [ sin8s::isUpper#10 ] : zp ZP_BYTE:17 , reg byte x , reg byte y ,
Potential registers zp ZP_WORD:18 [ sin8s::x#6 sin8s::x#4 sin8s::x#0 sin8s::x#1 sin8s::x#2 ] : zp ZP_WORD:18 ,
Potential registers zp ZP_BYTE:20 [ sin8s::usinx#4 sin8s::usinx#1 sin8s::usinx#2 ] : zp ZP_BYTE:20 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:21 [ sin8s::return#1 sin8s::return#5 sin8s::sinx#1 ] : zp ZP_BYTE:21 , reg byte a , reg byte x , reg byte y ,
@ -6457,14 +6443,14 @@ Potential registers zp ZP_WORD:42 [ sin8s_gen::step#0 ] : zp ZP_WORD:42 ,
Potential registers zp ZP_BYTE:44 [ sin8s::return#0 ] : zp ZP_BYTE:44 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:45 [ sin8s_gen::$1 ] : zp ZP_BYTE:45 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_WORD:46 [ sin8s::$6 ] : zp ZP_WORD:46 ,
Potential registers zp ZP_BYTE:48 [ sin8s::x1#0 ] : zp ZP_BYTE:48 , reg byte x ,
Potential registers zp ZP_BYTE:48 [ sin8s::x1#0 ] : zp ZP_BYTE:48 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:49 [ mulu8_sel::return#0 ] : zp ZP_BYTE:49 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:50 [ sin8s::x2#0 ] : zp ZP_BYTE:50 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:51 [ mulu8_sel::return#1 ] : zp ZP_BYTE:51 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:52 [ sin8s::x3#0 ] : zp ZP_BYTE:52 , reg byte x ,
Potential registers zp ZP_BYTE:52 [ sin8s::x3#0 ] : zp ZP_BYTE:52 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:53 [ mulu8_sel::return#2 ] : zp ZP_BYTE:53 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:54 [ sin8s::x3_6#0 ] : zp ZP_BYTE:54 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:55 [ sin8s::usinx#0 ] : zp ZP_BYTE:55 , reg byte x ,
Potential registers zp ZP_BYTE:55 [ sin8s::usinx#0 ] : zp ZP_BYTE:55 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:56 [ mulu8_sel::return#10 ] : zp ZP_BYTE:56 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:57 [ sin8s::x4#0 ] : zp ZP_BYTE:57 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:58 [ mulu8_sel::return#11 ] : zp ZP_BYTE:58 , reg byte a , reg byte x , reg byte y ,
@ -6500,9 +6486,9 @@ Uplifting [mul8u] best 18977 combination zp ZP_WORD:26 [ mul8u::res#2 mul8u::res
Uplifting [print_str] best 18977 combination zp ZP_WORD:3 [ print_str::str#3 print_str::str#5 print_str::str#0 ]
Uplifting [divr16u] best 18787 combination zp ZP_WORD:30 [ divr16u::rem#4 divr16u::rem#10 divr16u::rem#5 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp ZP_WORD:34 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp ZP_WORD:32 [ divr16u::dividend#2 divr16u::dividend#0 ] zp ZP_WORD:70 [ divr16u::return#2 ]
Uplifting [] best 18787 combination zp ZP_WORD:7 [ char_cursor#27 char_cursor#37 char_cursor#44 char_cursor#41 char_cursor#42 char_cursor#19 char_cursor#10 char_cursor#1 ]
Uplift attempts [sin8s] 10000/1048576 (limiting to 10000)
Uplift attempts [sin8s] 10000/5308416 (limiting to 10000)
Uplifting [sin8s] best 18660 combination zp ZP_WORD:18 [ sin8s::x#6 sin8s::x#4 sin8s::x#0 sin8s::x#1 sin8s::x#2 ] reg byte a [ sin8s::return#0 ] reg byte a [ sin8s::return#1 sin8s::return#5 sin8s::sinx#1 ] reg byte x [ sin8s::usinx#4 sin8s::usinx#1 sin8s::usinx#2 ] zp ZP_WORD:46 [ sin8s::$6 ] reg byte a [ sin8s::x2#0 ] reg byte a [ sin8s::x3_6#0 ] reg byte a [ sin8s::x4#0 ] reg byte a [ sin8s::x5#0 ] zp ZP_BYTE:60 [ sin8s::x5_128#0 ] zp ZP_BYTE:52 [ sin8s::x3#0 ] zp ZP_BYTE:48 [ sin8s::x1#0 ] zp ZP_BYTE:55 [ sin8s::usinx#0 ] zp ZP_BYTE:17 [ sin8s::isUpper#10 ]
Limited combination testing to 10000 combinations of 1048576 possible.
Limited combination testing to 10000 combinations of 5308416 possible.
Uplift attempts [mulu8_sel] 10000/196608 (limiting to 10000)
Uplifting [mulu8_sel] best 18600 combination reg byte x [ mulu8_sel::v1#5 mulu8_sel::v1#1 mulu8_sel::v1#2 mulu8_sel::v1#3 mulu8_sel::v1#4 mulu8_sel::v1#0 ] reg byte y [ mulu8_sel::v2#5 mulu8_sel::v2#1 mulu8_sel::v2#3 mulu8_sel::v2#4 mulu8_sel::v2#0 ] reg byte a [ mulu8_sel::return#0 ] reg byte a [ mulu8_sel::return#1 ] reg byte a [ mulu8_sel::return#2 ] reg byte a [ mulu8_sel::return#10 ] reg byte a [ mulu8_sel::return#11 ] zp ZP_WORD:64 [ mulu8_sel::$0 ] zp ZP_WORD:66 [ mulu8_sel::$1 ] zp ZP_BYTE:68 [ mulu8_sel::return#12 ] zp ZP_BYTE:24 [ mulu8_sel::select#5 ]
Limited combination testing to 10000 combinations of 196608 possible.

38
src/test/java/dk/camelot64/kickc/test/ref/sinusgen8b.log
View File

@ -8860,8 +8860,7 @@ Removing always clobbered register reg byte a as potential for zp ZP_BYTE:30 [ m
Statement [117] (word) mul16u::b#0 ← (word) mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a
Statement [119] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#2 ] ) always clobbers reg byte a
Statement [120] (dword~) mulu16_sel::$0 ← (dword) mul16u::return#2 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] ) always clobbers reg byte a
Statement [121] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a reg byte x
Removing always clobbered register reg byte x as potential for zp ZP_BYTE:19 [ sin16s::isUpper#2 ]
Statement [121] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a
Statement [122] (word) mulu16_sel::return#12 ← > (dword~) mulu16_sel::$1 [ mulu16_sel::return#12 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] ) always clobbers reg byte a
Statement [124] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a
Statement [126] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a
@ -8901,16 +8900,7 @@ Statement [224] (word) mul8u::return#2 ← (word) mul8u::res#2 [ mulu8_sel::sele
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:63 [ mulu8_sel::select#5 ]
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:174 [ sin8s::usinx#0 ]
Statement [225] (word~) mulu8_sel::$0 ← (word) mul8u::return#2 [ mulu8_sel::select#5 mulu8_sel::$0 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] ) always clobbers reg byte a
Potential register analysis [226] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuxx allocation: reg byte x [ mulu8_sel::select#5 ] zp ZP_WORD:185 [ mulu8_sel::$1 ] zp ZP_WORD:183 [ mulu8_sel::$0 ]
Potential register analysis [226] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuyy allocation: reg byte y [ mulu8_sel::select#5 ] zp ZP_WORD:185 [ mulu8_sel::$1 ] zp ZP_WORD:183 [ mulu8_sel::$0 ]
MISSING FRAGMENTS
vwuz1=vwuz2_rol_vbuxx
vwuz1=vwuz2_rol_vbuyy
Statement [226] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a reg byte y
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:56 [ sin8s::isUpper#10 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:167 [ sin8s::x1#0 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:171 [ sin8s::x3#0 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:174 [ sin8s::usinx#0 ]
Statement [226] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a
Statement [227] (byte) mulu8_sel::return#12 ← > (word~) mulu8_sel::$1 [ mulu8_sel::return#12 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::return#12 ] ) always clobbers reg byte a
Statement [229] (word) mul8u::mb#0 ← ((word)) (byte) mul8u::b#0 [ mul8u::a#1 mul8u::mb#0 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] ) always clobbers reg byte a
Removing always clobbered register reg byte a as potential for zp ZP_BYTE:64 [ mul8u::a#2 mul8u::a#1 mul8u::a#0 ]
@ -8969,14 +8959,13 @@ Statement [106] (word) mulu16_sel::return#11 ← (word) mulu16_sel::return#12 [
Statement [107] (word) sin16s::x5#0 ← (word) mulu16_sel::return#11 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ( main:2::sin16s_gen:7::sin16s:66 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5#0 ] ) always clobbers reg byte a
Statement [108] (word) sin16s::x5_128#0 ← (word) sin16s::x5#0 >> (byte/signed byte/word/signed word/dword/signed dword) 4 [ sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ( main:2::sin16s_gen:7::sin16s:66 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 sin16s::x5_128#0 ] ) always clobbers reg byte a reg byte y
Statement [109] (word) sin16s::usinx#1 ← (word) sin16s::usinx#0 + (word) sin16s::x5_128#0 [ sin16s::isUpper#2 sin16s::usinx#1 ] ( main:2::sin16s_gen:7::sin16s:66 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#1 ] ) always clobbers reg byte a
Statement [110] if((byte) sin16s::isUpper#2==(byte/signed byte/word/signed word/dword/signed dword) 0) goto sin16s::@15 [ sin16s::usinx#1 ] ( main:2::sin16s_gen:7::sin16s:66 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::usinx#1 ] ) always clobbers reg byte a
Statement [111] (signed word) sin16s::sinx#1 ← - (signed word)(word) sin16s::usinx#1 [ sin16s::sinx#1 ] ( main:2::sin16s_gen:7::sin16s:66 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::sinx#1 ] ) always clobbers reg byte a
Statement [114] (signed word~) sin16s::return#5 ← (signed word)(word) sin16s::usinx#1 [ sin16s::return#5 ] ( main:2::sin16s_gen:7::sin16s:66 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::return#5 ] ) always clobbers reg byte a
Statement [116] (word) mul16u::a#1 ← (word) mulu16_sel::v1#5 [ mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::v2#5 mulu16_sel::select#5 mul16u::a#1 ] ) always clobbers reg byte a
Statement [117] (word) mul16u::b#0 ← (word) mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::b#0 ] ) always clobbers reg byte a
Statement [119] (dword) mul16u::return#2 ← (dword) mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#2 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#2 ] ) always clobbers reg byte a
Statement [120] (dword~) mulu16_sel::$0 ← (dword) mul16u::return#2 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] ) always clobbers reg byte a
Statement [121] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a reg byte x
Statement [121] (dword~) mulu16_sel::$1 ← (dword~) mulu16_sel::$0 << (byte) mulu16_sel::select#5 [ mulu16_sel::$1 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] ) always clobbers reg byte a
Statement [122] (word) mulu16_sel::return#12 ← > (dword~) mulu16_sel::$1 [ mulu16_sel::return#12 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] ) always clobbers reg byte a
Statement [124] (dword) mul16u::mb#0 ← ((dword)) (word) mul16u::b#0 [ mul16u::a#1 mul16u::mb#0 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::a#1 mul16u::mb#0 ] ) always clobbers reg byte a
Statement [126] if((word) mul16u::a#2!=(byte/signed byte/word/signed word/dword/signed dword) 0) goto mul16u::@2 [ mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ( main:2::sin16s_gen:7::sin16s:66::mulu16_sel:85::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:90::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:94::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:100::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] main:2::sin16s_gen:7::sin16s:66::mulu16_sel:105::mul16u:118 [ sin16s_gen::step#0 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s_gen::i#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::res#2 mul16u::a#2 mul16u::mb#2 ] ) always clobbers reg byte a
@ -9011,12 +9000,7 @@ Statement [211] (byte) sin8s::usinx#1 ← (byte) sin8s::usinx#0 + (byte) sin8s::
Statement [216] (signed byte) sin8s::sinx#1 ← - (signed byte)(byte) sin8s::usinx#4 [ sin8s::sinx#1 ] ( main:2::sin8s_gen:5::sin8s:168 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::sinx#1 ] ) always clobbers reg byte a
Statement [224] (word) mul8u::return#2 ← (word) mul8u::res#2 [ mulu8_sel::select#5 mul8u::return#2 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::return#2 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::return#2 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::return#2 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::return#2 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::return#2 ] ) always clobbers reg byte a
Statement [225] (word~) mulu8_sel::$0 ← (word) mul8u::return#2 [ mulu8_sel::select#5 mulu8_sel::$0 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] ) always clobbers reg byte a
Potential register analysis [226] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuxx allocation: reg byte x [ mulu8_sel::select#5 ] zp ZP_WORD:185 [ mulu8_sel::$1 ] zp ZP_WORD:183 [ mulu8_sel::$0 ]
Potential register analysis [226] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuyy allocation: reg byte y [ mulu8_sel::select#5 ] zp ZP_WORD:185 [ mulu8_sel::$1 ] zp ZP_WORD:183 [ mulu8_sel::$0 ]
MISSING FRAGMENTS
vwuz1=vwuz2_rol_vbuxx
vwuz1=vwuz2_rol_vbuyy
Statement [226] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a reg byte y
Statement [226] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a
Statement [227] (byte) mulu8_sel::return#12 ← > (word~) mulu8_sel::$1 [ mulu8_sel::return#12 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::return#12 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::return#12 ] ) always clobbers reg byte a
Statement [229] (word) mul8u::mb#0 ← ((word)) (byte) mul8u::b#0 [ mul8u::a#1 mul8u::mb#0 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#1 mul8u::mb#0 ] ) always clobbers reg byte a
Statement [233] (byte~) mul8u::$1 ← (byte) mul8u::a#2 & (byte/signed byte/word/signed word/dword/signed dword) 1 [ mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] ( main:2::sin8s_gen:5::sin8s:168::mulu8_sel:187::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:192::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:196::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:202::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] main:2::sin8s_gen:5::sin8s:168::mulu8_sel:207::mul8u:223 [ sin8s_gen::step#0 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s_gen::i#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] ) always clobbers reg byte a
@ -9032,7 +9016,7 @@ Potential registers zp ZP_WORD:9 [ print_cls::sc#2 print_cls::sc#1 ] : zp ZP_WOR
Potential registers zp ZP_DWORD:11 [ sin16s_gen::x#2 sin16s_gen::x#1 ] : zp ZP_DWORD:11 ,
Potential registers zp ZP_WORD:15 [ sin16s_gen::sintab#2 sin16s_gen::sintab#0 ] : zp ZP_WORD:15 ,
Potential registers zp ZP_WORD:17 [ sin16s_gen::i#2 sin16s_gen::i#1 ] : zp ZP_WORD:17 ,
Potential registers zp ZP_BYTE:19 [ sin16s::isUpper#2 ] : zp ZP_BYTE:19 ,
Potential registers zp ZP_BYTE:19 [ sin16s::isUpper#2 ] : zp ZP_BYTE:19 , reg byte x ,
Potential registers zp ZP_DWORD:20 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] : zp ZP_DWORD:20 ,
Potential registers zp ZP_WORD:24 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] : zp ZP_WORD:24 ,
Potential registers zp ZP_WORD:26 [ mulu16_sel::v1#5 mulu16_sel::v1#3 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 ] : zp ZP_WORD:26 ,
@ -9049,7 +9033,7 @@ Potential registers zp ZP_BYTE:49 [ divr16u::i#2 divr16u::i#1 ] : zp ZP_BYTE:49
Potential registers zp ZP_WORD:50 [ sin8s_gen::x#2 sin8s_gen::x#1 ] : zp ZP_WORD:50 ,
Potential registers zp ZP_WORD:52 [ sin8s_gen::sintab#2 sin8s_gen::sintab#0 ] : zp ZP_WORD:52 ,
Potential registers zp ZP_WORD:54 [ sin8s_gen::i#2 sin8s_gen::i#1 ] : zp ZP_WORD:54 ,
Potential registers zp ZP_BYTE:56 [ sin8s::isUpper#10 ] : zp ZP_BYTE:56 , reg byte x ,
Potential registers zp ZP_BYTE:56 [ sin8s::isUpper#10 ] : zp ZP_BYTE:56 , reg byte x , reg byte y ,
Potential registers zp ZP_WORD:57 [ sin8s::x#6 sin8s::x#4 sin8s::x#0 sin8s::x#1 sin8s::x#2 ] : zp ZP_WORD:57 ,
Potential registers zp ZP_BYTE:59 [ sin8s::usinx#4 sin8s::usinx#1 sin8s::usinx#2 ] : zp ZP_BYTE:59 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:60 [ sin8s::return#1 sin8s::return#5 sin8s::sinx#1 ] : zp ZP_BYTE:60 , reg byte a , reg byte x , reg byte y ,
@ -9106,14 +9090,14 @@ Potential registers zp ZP_WORD:161 [ sin8s_gen::step#0 ] : zp ZP_WORD:161 ,
Potential registers zp ZP_BYTE:163 [ sin8s::return#0 ] : zp ZP_BYTE:163 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:164 [ sin8s_gen::$1 ] : zp ZP_BYTE:164 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_WORD:165 [ sin8s::$6 ] : zp ZP_WORD:165 ,
Potential registers zp ZP_BYTE:167 [ sin8s::x1#0 ] : zp ZP_BYTE:167 , reg byte x ,
Potential registers zp ZP_BYTE:167 [ sin8s::x1#0 ] : zp ZP_BYTE:167 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:168 [ mulu8_sel::return#0 ] : zp ZP_BYTE:168 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:169 [ sin8s::x2#0 ] : zp ZP_BYTE:169 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:170 [ mulu8_sel::return#1 ] : zp ZP_BYTE:170 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:171 [ sin8s::x3#0 ] : zp ZP_BYTE:171 , reg byte x ,
Potential registers zp ZP_BYTE:171 [ sin8s::x3#0 ] : zp ZP_BYTE:171 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:172 [ mulu8_sel::return#2 ] : zp ZP_BYTE:172 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:173 [ sin8s::x3_6#0 ] : zp ZP_BYTE:173 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:174 [ sin8s::usinx#0 ] : zp ZP_BYTE:174 , reg byte x ,
Potential registers zp ZP_BYTE:174 [ sin8s::usinx#0 ] : zp ZP_BYTE:174 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:175 [ mulu8_sel::return#10 ] : zp ZP_BYTE:175 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:176 [ sin8s::x4#0 ] : zp ZP_BYTE:176 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:177 [ mulu8_sel::return#11 ] : zp ZP_BYTE:177 , reg byte a , reg byte x , reg byte y ,
@ -9154,9 +9138,9 @@ Uplifting [print_str] best 34981 combination zp ZP_WORD:3 [ print_str::str#3 pri
Uplifting [divr16u] best 34791 combination zp ZP_WORD:43 [ divr16u::rem#6 divr16u::rem#11 divr16u::rem#5 divr16u::rem#10 divr16u::rem#7 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp ZP_WORD:47 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp ZP_WORD:45 [ divr16u::dividend#4 divr16u::dividend#6 divr16u::dividend#0 ] zp ZP_WORD:143 [ divr16u::return#3 ] zp ZP_WORD:147 [ divr16u::return#4 ] zp ZP_WORD:189 [ divr16u::return#2 ] zp ZP_WORD:41 [ divr16u::divisor#7 ]
Uplifting [] best 34791 combination zp ZP_WORD:7 [ char_cursor#27 char_cursor#37 char_cursor#44 char_cursor#41 char_cursor#42 char_cursor#19 char_cursor#10 char_cursor#1 ] zp ZP_WORD:157 [ rem16u#1 ]
Uplifting [main] best 34621 combination zp ZP_WORD:70 [ main::$3 ] zp ZP_WORD:72 [ main::$4 ] zp ZP_WORD:74 [ main::$5 ] zp ZP_WORD:76 [ main::sw#0 ] reg byte x [ main::i#2 main::i#1 ] reg byte a [ main::$6 ] zp ZP_BYTE:79 [ main::sd#0 ] zp ZP_BYTE:69 [ main::sb#0 ]
Uplift attempts [sin8s] 10000/1048576 (limiting to 10000)
Uplift attempts [sin8s] 10000/5308416 (limiting to 10000)
Uplifting [sin8s] best 34494 combination zp ZP_WORD:57 [ sin8s::x#6 sin8s::x#4 sin8s::x#0 sin8s::x#1 sin8s::x#2 ] reg byte a [ sin8s::return#0 ] reg byte a [ sin8s::return#1 sin8s::return#5 sin8s::sinx#1 ] reg byte x [ sin8s::usinx#4 sin8s::usinx#1 sin8s::usinx#2 ] zp ZP_WORD:165 [ sin8s::$6 ] reg byte a [ sin8s::x2#0 ] reg byte a [ sin8s::x3_6#0 ] reg byte a [ sin8s::x4#0 ] reg byte a [ sin8s::x5#0 ] zp ZP_BYTE:179 [ sin8s::x5_128#0 ] zp ZP_BYTE:171 [ sin8s::x3#0 ] zp ZP_BYTE:167 [ sin8s::x1#0 ] zp ZP_BYTE:174 [ sin8s::usinx#0 ] zp ZP_BYTE:56 [ sin8s::isUpper#10 ]
Limited combination testing to 10000 combinations of 1048576 possible.
Limited combination testing to 10000 combinations of 5308416 possible.
Uplifting [sin16s] best 34494 combination zp ZP_DWORD:20 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] zp ZP_WORD:90 [ sin16s::return#0 ] zp ZP_WORD:24 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] zp ZP_DWORD:94 [ sin16s::$6 ] zp ZP_WORD:102 [ sin16s::x2#0 ] zp ZP_WORD:110 [ sin16s::x3_6#0 ] zp ZP_WORD:116 [ sin16s::x4#0 ] zp ZP_WORD:120 [ sin16s::x5#0 ] zp ZP_WORD:122 [ sin16s::x5_128#0 ] zp ZP_WORD:106 [ sin16s::x3#0 ] zp ZP_WORD:124 [ sin16s::usinx#1 ] zp ZP_WORD:98 [ sin16s::x1#0 ] zp ZP_WORD:112 [ sin16s::usinx#0 ] zp ZP_BYTE:19 [ sin16s::isUpper#2 ]
Uplifting [mulu16_sel] best 34478 combination zp ZP_WORD:26 [ mulu16_sel::v1#5 mulu16_sel::v1#3 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 ] zp ZP_WORD:28 [ mulu16_sel::v2#5 mulu16_sel::v2#3 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 ] zp ZP_WORD:100 [ mulu16_sel::return#0 ] zp ZP_WORD:104 [ mulu16_sel::return#1 ] zp ZP_WORD:108 [ mulu16_sel::return#2 ] zp ZP_WORD:114 [ mulu16_sel::return#10 ] zp ZP_WORD:118 [ mulu16_sel::return#11 ] zp ZP_DWORD:132 [ mulu16_sel::$0 ] zp ZP_DWORD:136 [ mulu16_sel::$1 ] zp ZP_WORD:140 [ mulu16_sel::return#12 ] reg byte x [ mulu16_sel::select#5 ]
Uplift attempts [mulu8_sel] 10000/196608 (limiting to 10000)

30
src/test/java/dk/camelot64/kickc/test/ref/sinusgenscale8.log
View File

@ -8477,16 +8477,7 @@ Statement [170] (byte) sin8s::usinx#1 ← (byte) sin8s::usinx#0 + (byte) sin8s::
Statement [175] (signed byte) sin8s::sinx#1 ← - (signed byte)(byte) sin8s::usinx#4 [ sin8s::sinx#1 ] ( main:2::sin8u_table:7::sin8s:36 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::sinx#1 ] ) always clobbers reg byte a
Statement [183] (word) mul8u::return#3 ← (word) mul8u::res#2 [ mulu8_sel::select#5 mul8u::return#3 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::return#3 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::return#3 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::return#3 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::return#3 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::return#3 ] ) always clobbers reg byte a
Statement [184] (word~) mulu8_sel::$0 ← (word) mul8u::return#3 [ mulu8_sel::select#5 mulu8_sel::$0 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] ) always clobbers reg byte a
Potential register analysis [185] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuxx allocation: reg byte x [ mulu8_sel::select#5 ] zp ZP_WORD:85 [ mulu8_sel::$1 ] zp ZP_WORD:83 [ mulu8_sel::$0 ]
Potential register analysis [185] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuyy allocation: reg byte y [ mulu8_sel::select#5 ] zp ZP_WORD:85 [ mulu8_sel::$1 ] zp ZP_WORD:83 [ mulu8_sel::$0 ]
MISSING FRAGMENTS
vwuz1=vwuz2_rol_vbuxx
vwuz1=vwuz2_rol_vbuyy
Statement [185] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a reg byte y
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:29 [ sin8s::isUpper#10 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:68 [ sin8s::x1#0 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:72 [ sin8s::x3#0 ]
Removing always clobbered register reg byte y as potential for zp ZP_BYTE:75 [ sin8s::usinx#0 ]
Statement [185] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a
Statement [186] (byte) mulu8_sel::return#12 ← > (word~) mulu8_sel::$1 [ mulu8_sel::return#12 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::return#12 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::return#12 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::return#12 ] ) always clobbers reg byte a
Statement [190] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 ] ( main:2::sin8u_table:7::div16u:10 [ divr16u::return#2 ] ) always clobbers reg byte a
Statement [191] (word) div16u::return#0 ← (word) divr16u::return#2 [ div16u::return#0 ] ( main:2::sin8u_table:7::div16u:10 [ div16u::return#0 ] ) always clobbers reg byte a
@ -8541,12 +8532,7 @@ Statement [170] (byte) sin8s::usinx#1 ← (byte) sin8s::usinx#0 + (byte) sin8s::
Statement [175] (signed byte) sin8s::sinx#1 ← - (signed byte)(byte) sin8s::usinx#4 [ sin8s::sinx#1 ] ( main:2::sin8u_table:7::sin8s:36 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::sinx#1 ] ) always clobbers reg byte a
Statement [183] (word) mul8u::return#3 ← (word) mul8u::res#2 [ mulu8_sel::select#5 mul8u::return#3 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::return#3 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::return#3 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::return#3 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::return#3 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::return#3 ] ) always clobbers reg byte a
Statement [184] (word~) mulu8_sel::$0 ← (word) mul8u::return#3 [ mulu8_sel::select#5 mulu8_sel::$0 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mulu8_sel::$0 ] ) always clobbers reg byte a
Potential register analysis [185] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuxx allocation: reg byte x [ mulu8_sel::select#5 ] zp ZP_WORD:85 [ mulu8_sel::$1 ] zp ZP_WORD:83 [ mulu8_sel::$0 ]
Potential register analysis [185] mulu8_sel::$1 ← mulu8_sel::$0 << mulu8_sel::select#5 missing fragment vwuz1=vwuz2_rol_vbuyy allocation: reg byte y [ mulu8_sel::select#5 ] zp ZP_WORD:85 [ mulu8_sel::$1 ] zp ZP_WORD:83 [ mulu8_sel::$0 ]
MISSING FRAGMENTS
vwuz1=vwuz2_rol_vbuxx
vwuz1=vwuz2_rol_vbuyy
Statement [185] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a reg byte y
Statement [185] (word~) mulu8_sel::$1 ← (word~) mulu8_sel::$0 << (byte) mulu8_sel::select#5 [ mulu8_sel::$1 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::$1 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::$1 ] ) always clobbers reg byte a
Statement [186] (byte) mulu8_sel::return#12 ← > (word~) mulu8_sel::$1 [ mulu8_sel::return#12 ] ( main:2::sin8u_table:7::sin8s:36::mulu8_sel:146 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:151 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::return#12 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:155 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::return#12 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:161 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::return#12 ] main:2::sin8u_table:7::sin8s:36::mulu8_sel:166 [ sin8u_table::step#0 sin8u_table::x#10 sin8u_table::sintab#2 sin8u_table::i#10 line_cursor#1 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::return#12 ] ) always clobbers reg byte a
Statement [190] (word) divr16u::return#2 ← (word) divr16u::return#0 [ divr16u::return#2 ] ( main:2::sin8u_table:7::div16u:10 [ divr16u::return#2 ] ) always clobbers reg byte a
Statement [191] (word) div16u::return#0 ← (word) divr16u::return#2 [ div16u::return#0 ] ( main:2::sin8u_table:7::div16u:10 [ div16u::return#0 ] ) always clobbers reg byte a
@ -8573,7 +8559,7 @@ Potential registers zp ZP_BYTE:23 [ mul8u::b#2 mul8u::b#1 ] : zp ZP_BYTE:23 , re
Potential registers zp ZP_BYTE:24 [ mul8u::a#3 mul8u::a#6 mul8u::a#8 mul8u::a#2 mul8u::a#0 ] : zp ZP_BYTE:24 , reg byte x , reg byte y ,
Potential registers zp ZP_WORD:25 [ mul8u::res#2 mul8u::res#6 mul8u::res#1 ] : zp ZP_WORD:25 ,
Potential registers zp ZP_WORD:27 [ mul8u::mb#2 mul8u::mb#0 mul8u::mb#1 ] : zp ZP_WORD:27 ,
Potential registers zp ZP_BYTE:29 [ sin8s::isUpper#10 ] : zp ZP_BYTE:29 , reg byte x ,
Potential registers zp ZP_BYTE:29 [ sin8s::isUpper#10 ] : zp ZP_BYTE:29 , reg byte x , reg byte y ,
Potential registers zp ZP_WORD:30 [ sin8s::x#6 sin8s::x#4 sin8s::x#2 sin8s::x#0 sin8s::x#1 ] : zp ZP_WORD:30 ,
Potential registers zp ZP_BYTE:32 [ sin8s::usinx#4 sin8s::usinx#1 sin8s::usinx#2 ] : zp ZP_BYTE:32 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:33 [ sin8s::return#0 sin8s::return#5 sin8s::sinx#1 ] : zp ZP_BYTE:33 , reg byte a , reg byte x , reg byte y ,
@ -8601,14 +8587,14 @@ Potential registers zp ZP_BYTE:63 [ mul8su::$6 ] : zp ZP_BYTE:63 , reg byte a ,
Potential registers zp ZP_BYTE:64 [ mul8su::$10 ] : zp ZP_BYTE:64 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:65 [ mul8u::$1 ] : zp ZP_BYTE:65 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_WORD:66 [ sin8s::$6 ] : zp ZP_WORD:66 ,
Potential registers zp ZP_BYTE:68 [ sin8s::x1#0 ] : zp ZP_BYTE:68 , reg byte x ,
Potential registers zp ZP_BYTE:68 [ sin8s::x1#0 ] : zp ZP_BYTE:68 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:69 [ mulu8_sel::return#0 ] : zp ZP_BYTE:69 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:70 [ sin8s::x2#0 ] : zp ZP_BYTE:70 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:71 [ mulu8_sel::return#1 ] : zp ZP_BYTE:71 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:72 [ sin8s::x3#0 ] : zp ZP_BYTE:72 , reg byte x ,
Potential registers zp ZP_BYTE:72 [ sin8s::x3#0 ] : zp ZP_BYTE:72 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:73 [ mulu8_sel::return#2 ] : zp ZP_BYTE:73 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:74 [ sin8s::x3_6#0 ] : zp ZP_BYTE:74 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:75 [ sin8s::usinx#0 ] : zp ZP_BYTE:75 , reg byte x ,
Potential registers zp ZP_BYTE:75 [ sin8s::usinx#0 ] : zp ZP_BYTE:75 , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:76 [ mulu8_sel::return#10 ] : zp ZP_BYTE:76 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:77 [ sin8s::x4#0 ] : zp ZP_BYTE:77 , reg byte a , reg byte x , reg byte y ,
Potential registers zp ZP_BYTE:78 [ mulu8_sel::return#11 ] : zp ZP_BYTE:78 , reg byte a , reg byte x , reg byte y ,
@ -8646,9 +8632,9 @@ Uplifting [mul8u] best 24241 combination zp ZP_WORD:25 [ mul8u::res#2 mul8u::res
Uplifting [] best 24241 combination zp ZP_WORD:8 [ line_cursor#12 line_cursor#23 line_cursor#1 ] zp ZP_WORD:16 [ char_cursor#92 char_cursor#102 char_cursor#62 char_cursor#97 char_cursor#94 char_cursor#96 char_cursor#17 char_cursor#2 char_cursor#121 char_cursor#1 ]
Uplifting [print_str] best 24241 combination zp ZP_WORD:12 [ print_str::str#10 print_str::str#12 print_str::str#0 ]
Uplifting [divr16u] best 24051 combination zp ZP_WORD:37 [ divr16u::rem#4 divr16u::rem#10 divr16u::rem#5 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp ZP_WORD:41 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp ZP_WORD:39 [ divr16u::dividend#2 divr16u::dividend#0 ] zp ZP_WORD:88 [ divr16u::return#2 ]
Uplift attempts [sin8s] 10000/1048576 (limiting to 10000)
Uplift attempts [sin8s] 10000/5308416 (limiting to 10000)
Uplifting [sin8s] best 23924 combination zp ZP_WORD:30 [ sin8s::x#6 sin8s::x#4 sin8s::x#2 sin8s::x#0 sin8s::x#1 ] reg byte a [ sin8s::return#2 ] reg byte a [ sin8s::return#0 sin8s::return#5 sin8s::sinx#1 ] reg byte x [ sin8s::usinx#4 sin8s::usinx#1 sin8s::usinx#2 ] zp ZP_WORD:66 [ sin8s::$6 ] reg byte a [ sin8s::x2#0 ] reg byte a [ sin8s::x3_6#0 ] reg byte a [ sin8s::x4#0 ] reg byte a [ sin8s::x5#0 ] zp ZP_BYTE:80 [ sin8s::x5_128#0 ] zp ZP_BYTE:72 [ sin8s::x3#0 ] zp ZP_BYTE:68 [ sin8s::x1#0 ] zp ZP_BYTE:75 [ sin8s::usinx#0 ] zp ZP_BYTE:29 [ sin8s::isUpper#10 ]
Limited combination testing to 10000 combinations of 1048576 possible.
Limited combination testing to 10000 combinations of 5308416 possible.
Uplift attempts [mulu8_sel] 10000/196608 (limiting to 10000)
Uplifting [mulu8_sel] best 23864 combination reg byte x [ mulu8_sel::v1#5 mulu8_sel::v1#1 mulu8_sel::v1#2 mulu8_sel::v1#3 mulu8_sel::v1#4 mulu8_sel::v1#0 ] reg byte y [ mulu8_sel::v2#5 mulu8_sel::v2#1 mulu8_sel::v2#3 mulu8_sel::v2#4 mulu8_sel::v2#0 ] reg byte a [ mulu8_sel::return#0 ] reg byte a [ mulu8_sel::return#1 ] reg byte a [ mulu8_sel::return#2 ] reg byte a [ mulu8_sel::return#10 ] reg byte a [ mulu8_sel::return#11 ] zp ZP_WORD:83 [ mulu8_sel::$0 ] zp ZP_WORD:85 [ mulu8_sel::$1 ] zp ZP_BYTE:87 [ mulu8_sel::return#12 ] zp ZP_BYTE:36 [ mulu8_sel::select#5 ]
Limited combination testing to 10000 combinations of 196608 possible.

16
src/test/java/dk/camelot64/kickc/test/ref/test-keyboard-space.log
View File

@ -43,9 +43,9 @@ const byte KEY_DEL = $00;
const byte KEY_RETURN = $01;
const byte KEY_CRSR_RIGHT = $02;
const byte KEY_F7 = $03;
const byte KEY_F5 = $04;
const byte KEY_F1 = $04;
const byte KEY_F3 = $05;
const byte KEY_F1 = $06;
const byte KEY_F5 = $06;
const byte KEY_CRSR_DOWN = $07;
const byte KEY_3 = $08;
const byte KEY_W = $09;
@ -248,9 +248,9 @@ STATEMENTS
(byte) KEY_RETURN ← (byte/signed byte/word/signed word/dword/signed dword) 1
(byte) KEY_CRSR_RIGHT ← (byte/signed byte/word/signed word/dword/signed dword) 2
(byte) KEY_F7 ← (byte/signed byte/word/signed word/dword/signed dword) 3
(byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 4
(byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 4
(byte) KEY_F3 ← (byte/signed byte/word/signed word/dword/signed dword) 5
(byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 6
(byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 6
(byte) KEY_CRSR_DOWN ← (byte/signed byte/word/signed word/dword/signed dword) 7
(byte) KEY_3 ← (byte/signed byte/word/signed word/dword/signed dword) 8
(byte) KEY_W ← (byte/signed byte/word/signed word/dword/signed dword) 9
@ -573,9 +573,9 @@ INITIAL CONTROL FLOW GRAPH
(byte) KEY_RETURN ← (byte/signed byte/word/signed word/dword/signed dword) 1
(byte) KEY_CRSR_RIGHT ← (byte/signed byte/word/signed word/dword/signed dword) 2
(byte) KEY_F7 ← (byte/signed byte/word/signed word/dword/signed dword) 3
(byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 4
(byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 4
(byte) KEY_F3 ← (byte/signed byte/word/signed word/dword/signed dword) 5
(byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 6
(byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 6
(byte) KEY_CRSR_DOWN ← (byte/signed byte/word/signed word/dword/signed dword) 7
(byte) KEY_3 ← (byte/signed byte/word/signed word/dword/signed dword) 8
(byte) KEY_W ← (byte/signed byte/word/signed word/dword/signed dword) 9
@ -764,9 +764,9 @@ Eliminating unused variable (byte) KEY_DEL and assignment [37] (byte) KEY_DEL
Eliminating unused variable (byte) KEY_RETURN and assignment [38] (byte) KEY_RETURN ← (byte/signed byte/word/signed word/dword/signed dword) 1
Eliminating unused variable (byte) KEY_CRSR_RIGHT and assignment [39] (byte) KEY_CRSR_RIGHT ← (byte/signed byte/word/signed word/dword/signed dword) 2
Eliminating unused variable (byte) KEY_F7 and assignment [40] (byte) KEY_F7 ← (byte/signed byte/word/signed word/dword/signed dword) 3
Eliminating unused variable (byte) KEY_F5 and assignment [41] (byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 4
Eliminating unused variable (byte) KEY_F1 and assignment [41] (byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 4
Eliminating unused variable (byte) KEY_F3 and assignment [42] (byte) KEY_F3 ← (byte/signed byte/word/signed word/dword/signed dword) 5
Eliminating unused variable (byte) KEY_F1 and assignment [43] (byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 6
Eliminating unused variable (byte) KEY_F5 and assignment [43] (byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 6
Eliminating unused variable (byte) KEY_CRSR_DOWN and assignment [44] (byte) KEY_CRSR_DOWN ← (byte/signed byte/word/signed word/dword/signed dword) 7
Eliminating unused variable (byte) KEY_LSHIFT and assignment [52] (byte) KEY_LSHIFT ← (byte/signed byte/word/signed word/dword/signed dword) 15
Eliminating unused variable (byte) KEY_HOME and assignment [88] (byte) KEY_HOME ← (byte/signed byte/word/signed word/dword/signed dword) 51

16
src/test/java/dk/camelot64/kickc/test/ref/test-keyboard.log
View File

@ -74,9 +74,9 @@ const byte KEY_DEL = $00;
const byte KEY_RETURN = $01;
const byte KEY_CRSR_RIGHT = $02;
const byte KEY_F7 = $03;
const byte KEY_F5 = $04;
const byte KEY_F1 = $04;
const byte KEY_F3 = $05;
const byte KEY_F1 = $06;
const byte KEY_F5 = $06;
const byte KEY_CRSR_DOWN = $07;
const byte KEY_3 = $08;
const byte KEY_W = $09;
@ -282,9 +282,9 @@ STATEMENTS
(byte) KEY_RETURN ← (byte/signed byte/word/signed word/dword/signed dword) 1
(byte) KEY_CRSR_RIGHT ← (byte/signed byte/word/signed word/dword/signed dword) 2
(byte) KEY_F7 ← (byte/signed byte/word/signed word/dword/signed dword) 3
(byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 4
(byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 4
(byte) KEY_F3 ← (byte/signed byte/word/signed word/dword/signed dword) 5
(byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 6
(byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 6
(byte) KEY_CRSR_DOWN ← (byte/signed byte/word/signed word/dword/signed dword) 7
(byte) KEY_3 ← (byte/signed byte/word/signed word/dword/signed dword) 8
(byte) KEY_W ← (byte/signed byte/word/signed word/dword/signed dword) 9
@ -690,9 +690,9 @@ INITIAL CONTROL FLOW GRAPH
(byte) KEY_RETURN ← (byte/signed byte/word/signed word/dword/signed dword) 1
(byte) KEY_CRSR_RIGHT ← (byte/signed byte/word/signed word/dword/signed dword) 2
(byte) KEY_F7 ← (byte/signed byte/word/signed word/dword/signed dword) 3
(byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 4
(byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 4
(byte) KEY_F3 ← (byte/signed byte/word/signed word/dword/signed dword) 5
(byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 6
(byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 6
(byte) KEY_CRSR_DOWN ← (byte/signed byte/word/signed word/dword/signed dword) 7
(byte) KEY_3 ← (byte/signed byte/word/signed word/dword/signed dword) 8
(byte) KEY_W ← (byte/signed byte/word/signed word/dword/signed dword) 9
@ -954,9 +954,9 @@ Eliminating unused variable (byte) KEY_DEL and assignment [37] (byte) KEY_DEL
Eliminating unused variable (byte) KEY_RETURN and assignment [38] (byte) KEY_RETURN ← (byte/signed byte/word/signed word/dword/signed dword) 1
Eliminating unused variable (byte) KEY_CRSR_RIGHT and assignment [39] (byte) KEY_CRSR_RIGHT ← (byte/signed byte/word/signed word/dword/signed dword) 2
Eliminating unused variable (byte) KEY_F7 and assignment [40] (byte) KEY_F7 ← (byte/signed byte/word/signed word/dword/signed dword) 3
Eliminating unused variable (byte) KEY_F5 and assignment [41] (byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 4
Eliminating unused variable (byte) KEY_F1 and assignment [41] (byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 4
Eliminating unused variable (byte) KEY_F3 and assignment [42] (byte) KEY_F3 ← (byte/signed byte/word/signed word/dword/signed dword) 5
Eliminating unused variable (byte) KEY_F1 and assignment [43] (byte) KEY_F1 ← (byte/signed byte/word/signed word/dword/signed dword) 6
Eliminating unused variable (byte) KEY_F5 and assignment [43] (byte) KEY_F5 ← (byte/signed byte/word/signed word/dword/signed dword) 6
Eliminating unused variable (byte) KEY_CRSR_DOWN and assignment [44] (byte) KEY_CRSR_DOWN ← (byte/signed byte/word/signed word/dword/signed dword) 7
Eliminating unused variable (byte) KEY_LSHIFT and assignment [52] (byte) KEY_LSHIFT ← (byte/signed byte/word/signed word/dword/signed dword) 15
Eliminating unused variable (byte) KEY_HOME and assignment [88] (byte) KEY_HOME ← (byte/signed byte/word/signed word/dword/signed dword) 51