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Made immediate word and relative word addressing modes explicit. Improved opcode-guesser to include search for these modes.

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This commit is contained in:
jespergravgaard 2022-02-09 07:14:19 +01:00
parent 0b4a53ae12
commit 9c28ee4615
5 changed files with 37 additions and 18 deletions
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7
src/main/java/dk/camelot64/cpufamily6502/Cpu65xx.java
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@ -142,9 +142,16 @@ public class Cpu65xx {
// If the ZP-form does not exist use the ABS-variation
cpuOpcode = getOpcode(mnemonic, addressingMode);
}
if(cpuOpcode == null && CpuAddressingMode.IMM.equals(addressingMode)) {
// If the IMM-form does not exist try #imw (immediate word)
cpuOpcode = getOpcode(mnemonic, CpuAddressingMode.IMW);
}
if(cpuOpcode == null && CpuAddressingMode.ABS.equals(addressingMode)) {
// If the ABS-form does not exist try REL
cpuOpcode = getOpcode(mnemonic, CpuAddressingMode.REL);
// If the REL-form does not exist try REW
if(cpuOpcode==null)
cpuOpcode = getOpcode(mnemonic, CpuAddressingMode.REW);
}
return cpuOpcode;
}

16
src/main/java/dk/camelot64/cpufamily6502/CpuAddressingMode.java
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@ -19,6 +19,13 @@ public enum CpuAddressingMode {
*/
IMM("#imm", "%i #%p", 1),
/**
* #imw Immediate Word<br>
* IMMEDIATE WORD ADDRESSING — In immediate word addressing, the operand is contained in the second and third byte
* of the instruction, with no further memory addressing required.
*/
IMW("#imw", "%i #%p", 2),
/**
* zp Zeropage <br>
* ZERO PAGE ADDRESSING — The zero page instructions allow for shorter code and execution times by only fetching the
@ -170,6 +177,15 @@ public enum CpuAddressingMode {
*/
REL("rel", "%i %p", 1),
/**
* Relative Word<br>
* RELATIVE WORD ADDRESSING — Relative addressing is used only with branch instructions and establishes a destination for
* the conditional branch. The second byte of-the instruction becomes the operand which is an “Offset"" added to the
* contents of the program counter when the counter is set at the next instruction. The range
* of the offset is — 32768 to + 32767 bytes from the next instruction."
*/
REW("rew", "%i %p", 2),
/**
* zp,rel Zeropage Test Relative
* ZEROPAGE TEST RELATIVE. It needs two one-byte operands, one for the zero page address that is used for the bit

7
src/main/java/dk/camelot64/cpufamily6502/CpuOpcode.java
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@ -66,18 +66,13 @@ public class CpuOpcode {
return cycles;
}
/** Opcodes that use an extra byte for their operand that the addressing mode reports. This is immediate word and long branches.
* The format of the string is <code>mnemonic + " " + addressingMode</code> */
public static List<String> LONG_MNEMONICS = Arrays.asList("phw #imm", "lbra rel", "lbne rel", "lbeq rel", "lbcc rel", "lbcs rel", "lbmi rel", "lbpl rel", "lbvs rel", "lbvc rel", "lbsr rel" );
/**
* Get the number of bytes the instruction with operands takes up in memory
*
* @return The number of bytes.
*/
public int getBytes() {
final int numBytes = opcode.length + addressingMode.getBytes() + (LONG_MNEMONICS.contains(mnemonic+" "+addressingMode.getName())?1:0);
return numBytes;
return opcode.length + addressingMode.getBytes();
}
/**

22
src/main/java/dk/camelot64/cpufamily6502/cpus/Cpu65CE02.java
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@ -32,45 +32,45 @@ public class Cpu65CE02 extends Cpu65xx {
addOpcode(0x3,"see",CpuAddressingMode.NON,2,"e");
addOpcode(0xB,"tsy",CpuAddressingMode.NON,1,"Ynz");
addOpcode(0x12,"ora",CpuAddressingMode.IZZ,5,"Anz");
addOpcode(0x13,"lbpl",CpuAddressingMode.REL,3,"P");
addOpcode(0x13,"lbpl",CpuAddressingMode.REW,3,"P");
addOpcode(0x1B,"inz",CpuAddressingMode.NON,1,"Znz");
addOpcode(0x22,"jsr",CpuAddressingMode.IND,7,"PS");
addOpcode(0x23,"jsr",CpuAddressingMode.IAX,7,"PS");
addOpcode(0x2B,"tys",CpuAddressingMode.NON,1,"S");
addOpcode(0x32,"and",CpuAddressingMode.IZZ,5,"Anz");
addOpcode(0x33,"lbmi",CpuAddressingMode.REL,3,"P");
addOpcode(0x33,"lbmi",CpuAddressingMode.REW,3,"P");
addOpcode(0x3B,"dez",CpuAddressingMode.NON,1,"Znz");
addOpcode(0x42,"neg",CpuAddressingMode.NON,2,"Anz");
addOpcode(0x43,"asr",CpuAddressingMode.NON,2,"Acnz");
addOpcode(0x44,"asr",CpuAddressingMode.ZP,4,"cnz");
addOpcode(0x4B,"taz",CpuAddressingMode.NON,1,"Znz");
addOpcode(0x52,"eor",CpuAddressingMode.IZZ,5,"Anz");
addOpcode(0x53,"lbvc",CpuAddressingMode.REL,3,"P");
addOpcode(0x53,"lbvc",CpuAddressingMode.REW,3,"P");
addOpcode(0x54,"asr",CpuAddressingMode.ZPX,4,"cnz");
addOpcode(0x5B,"tab",CpuAddressingMode.NON,1,"B");
addOpcode(0x5C,"map",CpuAddressingMode.NON,2,"");
addOpcode(0x62,"rtn",CpuAddressingMode.IMM,7,"P");
addOpcode(0x63,"lbsr",CpuAddressingMode.REL,3,"P");
addOpcode(0x63,"lbsr",CpuAddressingMode.REW,3,"P");
addOpcode(0x6B,"tza",CpuAddressingMode.NON,1,"Anz");
addOpcode(0x72,"adc",CpuAddressingMode.IZZ,5,"Acvnz");
addOpcode(0x73,"lbvs",CpuAddressingMode.REL,3,"P");
addOpcode(0x73,"lbvs",CpuAddressingMode.REW,3,"P");
addOpcode(0x7B,"tba",CpuAddressingMode.NON,1,"Anz");
addOpcode(0x82,"sta",CpuAddressingMode.ISY,6,"");
addOpcode(0x83,"lbra",CpuAddressingMode.REL,3,"P");
addOpcode(0x83,"lbra",CpuAddressingMode.REW,3,"P");
addOpcode(0x8B,"sty",CpuAddressingMode.ABX,4,"");
addOpcode(0x92,"sta",CpuAddressingMode.IZZ,5,"");
addOpcode(0x93,"lbcc",CpuAddressingMode.REL,3,"P");
addOpcode(0x93,"lbcc",CpuAddressingMode.REW,3,"P");
addOpcode(0x9B,"stx",CpuAddressingMode.ABY,4,"");
addOpcode(0xA3,"ldz",CpuAddressingMode.IMM,2,"Znz");
addOpcode(0xAB,"ldz",CpuAddressingMode.ABS,4,"Znz");
addOpcode(0xB2,"lda",CpuAddressingMode.IZZ,5,"Anz");
addOpcode(0xB3,"lbcs",CpuAddressingMode.REL,3,"P");
addOpcode(0xB3,"lbcs",CpuAddressingMode.REW,3,"P");
addOpcode(0xBB,"ldz",CpuAddressingMode.ABX,4,"Znz");
addOpcode(0xC2,"cpz",CpuAddressingMode.IMM,2,"cnz");
addOpcode(0xC3,"dew",CpuAddressingMode.ZP,5,"nz");
addOpcode(0xCB,"asw",CpuAddressingMode.ABS,7,"cnz");
addOpcode(0xD2,"cmp",CpuAddressingMode.IZZ,5,"cnz");
addOpcode(0xD3,"lbne",CpuAddressingMode.REL,3,"P");
addOpcode(0xD3,"lbne",CpuAddressingMode.REW,3,"P");
addOpcode(0xD4,"cpz",CpuAddressingMode.ZP,3,"cnz");
addOpcode(0xDB,"phz",CpuAddressingMode.NON,3,"S");
addOpcode(0xDC,"cpz",CpuAddressingMode.ABS,4,"cnz");
@ -78,8 +78,8 @@ public class Cpu65CE02 extends Cpu65xx {
addOpcode(0xE3,"inw",CpuAddressingMode.ZP,5,"nz");
addOpcode(0xEB,"row",CpuAddressingMode.ABS,6,"cnz");
addOpcode(0xF2,"sbc",CpuAddressingMode.IZZ,5,"Acvnz");
addOpcode(0xF3,"lbeq",CpuAddressingMode.REL,3,"P");
addOpcode(0xF4,"phw",CpuAddressingMode.IMM,5,"S");
addOpcode(0xF3,"lbeq",CpuAddressingMode.REW,3,"P");
addOpcode(0xF4,"phw",CpuAddressingMode.IMW,5,"S");
addOpcode(0xFB,"plz",CpuAddressingMode.NON,3,"ZnzS");
addOpcode(0xFC,"phw",CpuAddressingMode.ABS,7,"S");
addOpcode(0xEA,"eom",CpuAddressingMode.NON,1,"");

3
src/test/java/dk/camelot64/cpufamily6502/TestCpuFamilyKickAssCompatibility.java
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@ -121,7 +121,8 @@ public class TestCpuFamilyKickAssCompatibility {
Map<CpuAddressingMode, List<_65xxArgType>> getKAAddressingModeMap() {
final HashMap<CpuAddressingMode, List<_65xxArgType>> map = new HashMap<>();
map.put(CpuAddressingMode.NON, Collections.singletonList(_65xxArgType.noArgument));
map.put(CpuAddressingMode.IMM, Arrays.asList(_65xxArgType.immediate, _65xxArgType.immediateWord));
map.put(CpuAddressingMode.IMM, Collections.singletonList(_65xxArgType.immediate));
map.put(CpuAddressingMode.IMW, Collections.singletonList(_65xxArgType.immediateWord));
map.put(CpuAddressingMode.ZP, Collections.singletonList(_65xxArgType.zeropage));
map.put(CpuAddressingMode.ZPX, Collections.singletonList(_65xxArgType.zeropageX));
map.put(CpuAddressingMode.ZPY, Collections.singletonList(_65xxArgType.zeropageY));