diff --git a/src/test/ref/bitmap-plot-1.log b/src/test/ref/bitmap-plot-1.log
index f1cfb5e66..3ee5fcb16 100644
--- a/src/test/ref/bitmap-plot-1.log
+++ b/src/test/ref/bitmap-plot-1.log
@@ -3935,34 +3935,34 @@ Uplift Scope [init_irq]
 Uplift Scope [irq] 
 Uplift Scope [__start] 
 
-Uplifting [mul16u] best 27423 combination zp[4]:45 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] zp[4]:49 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] reg byte a [ mul16u::$1 ] zp[2]:43 [ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ] zp[2]:41 [ mul16u::b#2 mul16u::b#1 mul16u::b#0 ] zp[4]:211 [ mul16u::return#0 ] zp[4]:137 [ mul16u::return#3 ] 
-Uplifting [divr16u] best 27233 combination zp[2]:53 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp[2]:57 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp[2]:55 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] zp[2]:160 [ divr16u::return#2 ] zp[2]:164 [ divr16u::return#3 ] 
-Uplifting [mulu16_sel] best 27215 combination zp[2]:60 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ] zp[4]:215 [ mulu16_sel::$0 ] zp[4]:219 [ mulu16_sel::$1 ] zp[2]:62 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ] zp[2]:223 [ mulu16_sel::return#12 ] zp[2]:178 [ mulu16_sel::return#0 ] zp[2]:182 [ mulu16_sel::return#1 ] zp[2]:186 [ mulu16_sel::return#2 ] zp[2]:192 [ mulu16_sel::return#10 ] zp[2]:196 [ mulu16_sel::return#11 ] reg byte x [ mulu16_sel::select#5 ] 
-Uplifting [sin16s] best 27208 combination zp[4]:28 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] zp[2]:32 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] zp[4]:172 [ sin16s::$4 ] zp[2]:180 [ sin16s::x2#0 ] zp[2]:188 [ sin16s::x3_6#0 ] zp[2]:194 [ sin16s::x4#0 ] zp[2]:198 [ sin16s::x5#0 ] zp[2]:200 [ sin16s::x5_128#0 ] zp[2]:184 [ sin16s::x3#0 ] zp[2]:202 [ sin16s::usinx#1 ] zp[2]:176 [ sin16s::x1#0 ] zp[2]:121 [ sin16s::return#0 ] zp[2]:190 [ sin16s::usinx#0 ] reg byte y [ sin16s::isUpper#2 ] 
-Uplifting [mul16s] best 27208 combination zp[4]:23 [ mul16s::m#4 mul16s::m#5 mul16s::m#1 mul16s::m#0 mul16s::m#2 ] zp[2]:141 [ mul16s::$6 ] zp[2]:143 [ mul16s::$11 ] zp[2]:145 [ mul16s::$9 ] zp[2]:147 [ mul16s::$12 ] zp[2]:19 [ mul16s::a#3 mul16s::a#0 ] zp[4]:149 [ mul16s::return#1 ] zp[4]:123 [ mul16s::return#0 ] zp[2]:21 [ mul16s::b#3 mul16s::b#2 mul16s::b#1 ] zp[4]:72 [ mul16s::return#3 ] zp[4]:94 [ mul16s::return#4 ] 
-Uplifting [memset] best 27192 combination zp[2]:39 [ memset::dst#2 memset::dst#4 memset::dst#1 ] zp[2]:204 [ memset::end#0 ] reg byte x [ memset::c#4 ] zp[2]:34 [ memset::num#2 ] zp[2]:36 [ memset::str#3 ] 
-Uplifting [bitmap_init] best 26742 combination zp[2]:17 [ bitmap_init::yoffs#2 bitmap_init::yoffs#4 bitmap_init::yoffs#1 ] reg byte a [ bitmap_init::bits#3 bitmap_init::bits#4 bitmap_init::bits#1 ] reg byte x [ bitmap_init::x#2 bitmap_init::x#1 ] reg byte x [ bitmap_init::y#2 bitmap_init::y#1 ] reg byte a [ bitmap_init::$4 ] zp[1]:135 [ bitmap_init::$5 ] zp[1]:136 [ bitmap_init::$6 ] zp[1]:133 [ bitmap_init::$7 ] 
+Uplifting [mul16u] best 27421 combination zp[4]:45 [ mul16u::res#2 mul16u::res#6 mul16u::res#1 ] zp[4]:49 [ mul16u::mb#2 mul16u::mb#0 mul16u::mb#1 ] reg byte a [ mul16u::$1 ] zp[2]:43 [ mul16u::a#3 mul16u::a#6 mul16u::a#2 mul16u::a#0 mul16u::a#1 ] zp[2]:41 [ mul16u::b#2 mul16u::b#1 mul16u::b#0 ] zp[4]:211 [ mul16u::return#0 ] zp[4]:137 [ mul16u::return#3 ] 
+Uplifting [divr16u] best 27231 combination zp[2]:53 [ divr16u::rem#5 divr16u::rem#10 divr16u::rem#4 divr16u::rem#11 divr16u::rem#6 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp[2]:57 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp[2]:55 [ divr16u::dividend#3 divr16u::dividend#5 divr16u::dividend#0 ] zp[2]:160 [ divr16u::return#2 ] zp[2]:164 [ divr16u::return#3 ] 
+Uplifting [mulu16_sel] best 27213 combination zp[2]:60 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ] zp[4]:215 [ mulu16_sel::$0 ] zp[4]:219 [ mulu16_sel::$1 ] zp[2]:62 [ mulu16_sel::v2#5 mulu16_sel::v2#4 mulu16_sel::v2#0 mulu16_sel::v2#1 mulu16_sel::v2#3 ] zp[2]:223 [ mulu16_sel::return#12 ] zp[2]:178 [ mulu16_sel::return#0 ] zp[2]:182 [ mulu16_sel::return#1 ] zp[2]:186 [ mulu16_sel::return#2 ] zp[2]:192 [ mulu16_sel::return#10 ] zp[2]:196 [ mulu16_sel::return#11 ] reg byte x [ mulu16_sel::select#5 ] 
+Uplifting [sin16s] best 27206 combination zp[4]:28 [ sin16s::x#6 sin16s::x#4 sin16s::x#0 sin16s::x#1 sin16s::x#2 ] zp[2]:32 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] zp[4]:172 [ sin16s::$4 ] zp[2]:180 [ sin16s::x2#0 ] zp[2]:188 [ sin16s::x3_6#0 ] zp[2]:194 [ sin16s::x4#0 ] zp[2]:198 [ sin16s::x5#0 ] zp[2]:200 [ sin16s::x5_128#0 ] zp[2]:184 [ sin16s::x3#0 ] zp[2]:202 [ sin16s::usinx#1 ] zp[2]:176 [ sin16s::x1#0 ] zp[2]:121 [ sin16s::return#0 ] zp[2]:190 [ sin16s::usinx#0 ] reg byte y [ sin16s::isUpper#2 ] 
+Uplifting [mul16s] best 27206 combination zp[4]:23 [ mul16s::m#4 mul16s::m#5 mul16s::m#1 mul16s::m#0 mul16s::m#2 ] zp[2]:141 [ mul16s::$6 ] zp[2]:143 [ mul16s::$11 ] zp[2]:145 [ mul16s::$9 ] zp[2]:147 [ mul16s::$12 ] zp[2]:19 [ mul16s::a#3 mul16s::a#0 ] zp[4]:149 [ mul16s::return#1 ] zp[4]:123 [ mul16s::return#0 ] zp[2]:21 [ mul16s::b#3 mul16s::b#2 mul16s::b#1 ] zp[4]:72 [ mul16s::return#3 ] zp[4]:94 [ mul16s::return#4 ] 
+Uplifting [memset] best 27190 combination zp[2]:39 [ memset::dst#2 memset::dst#4 memset::dst#1 ] zp[2]:204 [ memset::end#0 ] reg byte x [ memset::c#4 ] zp[2]:34 [ memset::num#2 ] zp[2]:36 [ memset::str#3 ] 
+Uplifting [bitmap_init] best 26740 combination zp[2]:17 [ bitmap_init::yoffs#2 bitmap_init::yoffs#4 bitmap_init::yoffs#1 ] reg byte a [ bitmap_init::bits#3 bitmap_init::bits#4 bitmap_init::bits#1 ] reg byte x [ bitmap_init::x#2 bitmap_init::x#1 ] reg byte x [ bitmap_init::y#2 bitmap_init::y#1 ] reg byte a [ bitmap_init::$4 ] zp[1]:135 [ bitmap_init::$5 ] zp[1]:136 [ bitmap_init::$6 ] zp[1]:133 [ bitmap_init::$7 ] 
 Limited combination testing to 100 combinations of 15360 possible.
-Uplifting [bitmap_plot] best 26703 combination reg byte x [ bitmap_plot::y#0 ] zp[2]:155 [ bitmap_plot::$0 ] reg byte x [ bitmap_plot::$1 ] zp[2]:157 [ bitmap_plot::plotter#1 ] zp[2]:153 [ bitmap_plot::plotter#0 ] zp[2]:110 [ bitmap_plot::x#0 ] 
-Uplifting [sin16s_gen2] best 26703 combination zp[2]:6 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] zp[4]:127 [ sin16s_gen2::$6 ] zp[4]:8 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ] zp[2]:131 [ sin16s_gen2::$8 ] zp[2]:12 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ] zp[4]:117 [ sin16s_gen2::step#0 ] 
-Uplifting [div32u16u] best 26703 combination zp[2]:166 [ div32u16u::quotient_lo#0 ] zp[2]:162 [ div32u16u::quotient_hi#0 ] zp[4]:168 [ div32u16u::return#1 ] zp[4]:113 [ div32u16u::return#0 ] 
-Uplifting [main] best 26463 combination zp[2]:4 [ main::idx_y#3 main::idx_y#10 main::idx_y#1 ] zp[2]:66 [ main::$19 ] zp[2]:68 [ main::$21 ] zp[2]:70 [ main::cos_x#0 ] zp[4]:76 [ main::xpos#0 ] zp[4]:80 [ main::$6 ] reg byte alu [ main::$7 ] zp[2]:88 [ main::$20 ] zp[2]:90 [ main::$22 ] zp[2]:92 [ main::sin_y#0 ] zp[4]:98 [ main::ypos#0 ] zp[4]:102 [ main::$10 ] reg byte alu [ main::$11 ] zp[2]:2 [ main::idx_x#3 main::idx_x#10 main::idx_x#1 ] zp[2]:108 [ main::y#0 ] zp[2]:86 [ main::x#0 ] 
-Uplifting [] best 26463 combination zp[2]:209 [ rem16u#14 ] zp[1]:65 [ frame_cnt ] 
-Uplifting [MOS6526_CIA] best 26463 combination 
-Uplifting [MOS6569_VICII] best 26463 combination 
-Uplifting [MOS6581_SID] best 26463 combination 
-Uplifting [bitmap_clear] best 26463 combination 
-Uplifting [init_irq] best 26463 combination 
-Uplifting [irq] best 26463 combination 
-Uplifting [__start] best 26463 combination 
+Uplifting [bitmap_plot] best 26701 combination reg byte x [ bitmap_plot::y#0 ] zp[2]:155 [ bitmap_plot::$0 ] reg byte x [ bitmap_plot::$1 ] zp[2]:157 [ bitmap_plot::plotter#1 ] zp[2]:153 [ bitmap_plot::plotter#0 ] zp[2]:110 [ bitmap_plot::x#0 ] 
+Uplifting [sin16s_gen2] best 26701 combination zp[2]:6 [ sin16s_gen2::i#2 sin16s_gen2::i#1 ] zp[4]:127 [ sin16s_gen2::$6 ] zp[4]:8 [ sin16s_gen2::x#2 sin16s_gen2::x#1 ] zp[2]:131 [ sin16s_gen2::$8 ] zp[2]:12 [ sin16s_gen2::sintab#2 sin16s_gen2::sintab#0 ] zp[4]:117 [ sin16s_gen2::step#0 ] 
+Uplifting [div32u16u] best 26701 combination zp[2]:166 [ div32u16u::quotient_lo#0 ] zp[2]:162 [ div32u16u::quotient_hi#0 ] zp[4]:168 [ div32u16u::return#1 ] zp[4]:113 [ div32u16u::return#0 ] 
+Uplifting [main] best 26461 combination zp[2]:4 [ main::idx_y#3 main::idx_y#10 main::idx_y#1 ] zp[2]:66 [ main::$19 ] zp[2]:68 [ main::$21 ] zp[2]:70 [ main::cos_x#0 ] zp[4]:76 [ main::xpos#0 ] zp[4]:80 [ main::$6 ] reg byte alu [ main::$7 ] zp[2]:88 [ main::$20 ] zp[2]:90 [ main::$22 ] zp[2]:92 [ main::sin_y#0 ] zp[4]:98 [ main::ypos#0 ] zp[4]:102 [ main::$10 ] reg byte alu [ main::$11 ] zp[2]:2 [ main::idx_x#3 main::idx_x#10 main::idx_x#1 ] zp[2]:108 [ main::y#0 ] zp[2]:86 [ main::x#0 ] 
+Uplifting [] best 26461 combination zp[2]:209 [ rem16u#14 ] zp[1]:65 [ frame_cnt ] 
+Uplifting [MOS6526_CIA] best 26461 combination 
+Uplifting [MOS6569_VICII] best 26461 combination 
+Uplifting [MOS6581_SID] best 26461 combination 
+Uplifting [bitmap_clear] best 26461 combination 
+Uplifting [init_irq] best 26461 combination 
+Uplifting [irq] best 26461 combination 
+Uplifting [__start] best 26461 combination 
 Attempting to uplift remaining variables inzp[1]:135 [ bitmap_init::$5 ]
-Uplifting [bitmap_init] best 26403 combination reg byte a [ bitmap_init::$5 ] 
+Uplifting [bitmap_init] best 26401 combination reg byte a [ bitmap_init::$5 ] 
 Attempting to uplift remaining variables inzp[1]:136 [ bitmap_init::$6 ]
-Uplifting [bitmap_init] best 26343 combination reg byte a [ bitmap_init::$6 ] 
+Uplifting [bitmap_init] best 26341 combination reg byte a [ bitmap_init::$6 ] 
 Attempting to uplift remaining variables inzp[1]:133 [ bitmap_init::$7 ]
-Uplifting [bitmap_init] best 26343 combination zp[1]:133 [ bitmap_init::$7 ] 
+Uplifting [bitmap_init] best 26341 combination zp[1]:133 [ bitmap_init::$7 ] 
 Attempting to uplift remaining variables inzp[1]:65 [ frame_cnt ]
-Uplifting [] best 26343 combination zp[1]:65 [ frame_cnt ] 
+Uplifting [] best 26341 combination zp[1]:65 [ frame_cnt ] 
 Coalescing zero page register [ zp[2]:32 [ sin16s::return#1 sin16s::return#5 sin16s::sinx#1 ] ] with [ zp[2]:202 [ sin16s::usinx#1 ] ] - score: 2
 Coalescing zero page register [ zp[2]:60 [ mulu16_sel::v1#5 mulu16_sel::v1#4 mulu16_sel::v1#0 mulu16_sel::v1#1 mulu16_sel::v1#2 mulu16_sel::v1#3 ] ] with [ zp[2]:184 [ sin16s::x3#0 ] ] - score: 2
 Coalescing zero page register [ zp[2]:19 [ mul16s::a#3 mul16s::a#0 ] ] with [ zp[2]:121 [ sin16s::return#0 ] ] - score: 1
@@ -4934,7 +4934,6 @@ bitmap_plot: {
     lda bitmap_plot_bit,x
     ldy #0
     ora (plotter),y
-    ldy #0
     sta (plotter),y
     jmp __breturn
     // bitmap_plot::@return
@@ -5707,7 +5706,6 @@ Removing instruction lda #>0
 Removing instruction lda #>0
 Removing instruction lda #>0
 Removing instruction lda #>0
-Removing instruction ldy #0
 Removing instruction lda #>0
 Removing instruction lda #>0
 Replacing instruction lda #<0 with TXA
diff --git a/src/test/ref/line-anim.log b/src/test/ref/line-anim.log
index 250801dbd..2859a50b0 100644
--- a/src/test/ref/line-anim.log
+++ b/src/test/ref/line-anim.log
@@ -2514,36 +2514,36 @@ Uplift Scope [MOS6569_VICII]
 Uplift Scope [MOS6581_SID] 
 Uplift Scope [] 
 
-Uplifting [divr16u] best 30349 combination zp[2]:27 [ divr16u::rem#4 divr16u::rem#3 divr16u::rem#9 divr16u::rem#5 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp[2]:29 [ divr16u::dividend#2 divr16u::dividend#0 ] zp[2]:81 [ divr16u::divisor#0 ] zp[2]:83 [ divr16u::return#2 ] 
-Uplifting [divr16s] best 30340 combination zp[2]:22 [ divr16s::divisoru#3 divr16s::divisoru#4 divr16s::divisoru#5 ] zp[2]:25 [ divr16s::return#2 divr16s::return#6 divr16s::return#1 ] zp[2]:20 [ divr16s::remu#3 divr16s::remu#7 divr16s::remu#8 ] reg byte y [ divr16s::neg#4 divr16s::neg#2 divr16s::neg#3 ] zp[2]:89 [ divr16s::remu#1 ] zp[2]:62 [ divr16s::rem#0 ] zp[2]:85 [ divr16s::resultu#0 ] zp[2]:87 [ divr16s::divisoru#1 ] zp[2]:60 [ divr16s::divisor#0 ] zp[2]:64 [ divr16s::return#3 ] 
-Uplifting [bitmap_clear] best 29440 combination zp[2]:9 [ bitmap_clear::bitmap#2 bitmap_clear::bitmap#3 bitmap_clear::bitmap#5 bitmap_clear::bitmap#1 ] reg byte x [ bitmap_clear::x#2 bitmap_clear::x#1 ] zp[1]:8 [ bitmap_clear::y#4 bitmap_clear::y#1 ] zp[2]:43 [ bitmap_clear::bitmap#0 ] 
-Uplifting [screen_fill] best 28540 combination zp[2]:13 [ screen_fill::screen#2 screen_fill::screen#3 screen_fill::screen#1 ] reg byte x [ screen_fill::x#2 screen_fill::x#1 ] zp[1]:12 [ screen_fill::y#4 screen_fill::y#1 ] 
-Uplifting [point_init] best 28528 combination zp[2]:18 [ point_init::abs16s2_return#2 point_init::abs16s2_return#5 point_init::abs16s2_return#6 ] zp[2]:16 [ point_init::abs16s1_return#2 point_init::abs16s1_return#5 point_init::abs16s1_return#6 ] zp[2]:50 [ point_init::$18 ] zp[2]:54 [ point_init::$5 ] zp[2]:56 [ point_init::$19 ] zp[2]:58 [ point_init::$6 ] zp[2]:66 [ point_init::x_stepf#0 ] reg byte a [ point_init::$9 ] zp[2]:48 [ point_init::$17 ] reg byte a [ point_init::$10 ] zp[2]:70 [ point_init::abs16s2_return#0 ] zp[2]:72 [ point_init::abs16s1_return#0 ] zp[2]:46 [ point_init::x_diff#1 ] zp[2]:52 [ point_init::y_diff#0 ] zp[1]:34 [ point_init::point_idx#0 ] zp[1]:45 [ point_init::$13 ] 
+Uplifting [divr16u] best 30347 combination zp[2]:27 [ divr16u::rem#4 divr16u::rem#3 divr16u::rem#9 divr16u::rem#5 divr16u::rem#0 divr16u::rem#1 divr16u::rem#2 ] zp[2]:31 [ divr16u::quotient#3 divr16u::return#0 divr16u::quotient#1 divr16u::quotient#2 ] reg byte a [ divr16u::$1 ] reg byte a [ divr16u::$2 ] reg byte x [ divr16u::i#2 divr16u::i#1 ] zp[2]:29 [ divr16u::dividend#2 divr16u::dividend#0 ] zp[2]:81 [ divr16u::divisor#0 ] zp[2]:83 [ divr16u::return#2 ] 
+Uplifting [divr16s] best 30338 combination zp[2]:22 [ divr16s::divisoru#3 divr16s::divisoru#4 divr16s::divisoru#5 ] zp[2]:25 [ divr16s::return#2 divr16s::return#6 divr16s::return#1 ] zp[2]:20 [ divr16s::remu#3 divr16s::remu#7 divr16s::remu#8 ] reg byte y [ divr16s::neg#4 divr16s::neg#2 divr16s::neg#3 ] zp[2]:89 [ divr16s::remu#1 ] zp[2]:62 [ divr16s::rem#0 ] zp[2]:85 [ divr16s::resultu#0 ] zp[2]:87 [ divr16s::divisoru#1 ] zp[2]:60 [ divr16s::divisor#0 ] zp[2]:64 [ divr16s::return#3 ] 
+Uplifting [bitmap_clear] best 29438 combination zp[2]:9 [ bitmap_clear::bitmap#2 bitmap_clear::bitmap#3 bitmap_clear::bitmap#5 bitmap_clear::bitmap#1 ] reg byte x [ bitmap_clear::x#2 bitmap_clear::x#1 ] zp[1]:8 [ bitmap_clear::y#4 bitmap_clear::y#1 ] zp[2]:43 [ bitmap_clear::bitmap#0 ] 
+Uplifting [screen_fill] best 28538 combination zp[2]:13 [ screen_fill::screen#2 screen_fill::screen#3 screen_fill::screen#1 ] reg byte x [ screen_fill::x#2 screen_fill::x#1 ] zp[1]:12 [ screen_fill::y#4 screen_fill::y#1 ] 
+Uplifting [point_init] best 28526 combination zp[2]:18 [ point_init::abs16s2_return#2 point_init::abs16s2_return#5 point_init::abs16s2_return#6 ] zp[2]:16 [ point_init::abs16s1_return#2 point_init::abs16s1_return#5 point_init::abs16s1_return#6 ] zp[2]:50 [ point_init::$18 ] zp[2]:54 [ point_init::$5 ] zp[2]:56 [ point_init::$19 ] zp[2]:58 [ point_init::$6 ] zp[2]:66 [ point_init::x_stepf#0 ] reg byte a [ point_init::$9 ] zp[2]:48 [ point_init::$17 ] reg byte a [ point_init::$10 ] zp[2]:70 [ point_init::abs16s2_return#0 ] zp[2]:72 [ point_init::abs16s1_return#0 ] zp[2]:46 [ point_init::x_diff#1 ] zp[2]:52 [ point_init::y_diff#0 ] zp[1]:34 [ point_init::point_idx#0 ] zp[1]:45 [ point_init::$13 ] 
 Limited combination testing to 100 combinations of 144 possible.
-Uplifting [bitmap_init] best 28078 combination zp[2]:6 [ bitmap_init::yoffs#2 bitmap_init::yoffs#4 bitmap_init::yoffs#1 ] reg byte a [ bitmap_init::bits#3 bitmap_init::bits#4 bitmap_init::bits#1 ] reg byte x [ bitmap_init::x#2 bitmap_init::x#1 ] reg byte x [ bitmap_init::y#2 bitmap_init::y#1 ] reg byte a [ bitmap_init::$4 ] zp[1]:41 [ bitmap_init::$5 ] zp[1]:42 [ bitmap_init::$6 ] zp[1]:39 [ bitmap_init::$7 ] 
+Uplifting [bitmap_init] best 28076 combination zp[2]:6 [ bitmap_init::yoffs#2 bitmap_init::yoffs#4 bitmap_init::yoffs#1 ] reg byte a [ bitmap_init::bits#3 bitmap_init::bits#4 bitmap_init::bits#1 ] reg byte x [ bitmap_init::x#2 bitmap_init::x#1 ] reg byte x [ bitmap_init::y#2 bitmap_init::y#1 ] reg byte a [ bitmap_init::$4 ] zp[1]:41 [ bitmap_init::$5 ] zp[1]:42 [ bitmap_init::$6 ] zp[1]:39 [ bitmap_init::$7 ] 
 Limited combination testing to 100 combinations of 15360 possible.
-Uplifting [bitmap_plot] best 28039 combination reg byte x [ bitmap_plot::y#0 ] zp[2]:76 [ bitmap_plot::$0 ] reg byte x [ bitmap_plot::$1 ] zp[2]:78 [ bitmap_plot::plotter#1 ] zp[2]:74 [ bitmap_plot::plotter#0 ] zp[2]:36 [ bitmap_plot::x#0 ] 
-Uplifting [main] best 27999 combination zp[1]:2 [ main::i#2 main::i#1 ] reg byte a [ main::$10 ] 
-Uplifting [MOS6526_CIA] best 27999 combination 
-Uplifting [MOS6569_VICII] best 27999 combination 
-Uplifting [MOS6581_SID] best 27999 combination 
-Uplifting [] best 27999 combination 
+Uplifting [bitmap_plot] best 28037 combination reg byte x [ bitmap_plot::y#0 ] zp[2]:76 [ bitmap_plot::$0 ] reg byte x [ bitmap_plot::$1 ] zp[2]:78 [ bitmap_plot::plotter#1 ] zp[2]:74 [ bitmap_plot::plotter#0 ] zp[2]:36 [ bitmap_plot::x#0 ] 
+Uplifting [main] best 27997 combination zp[1]:2 [ main::i#2 main::i#1 ] reg byte a [ main::$10 ] 
+Uplifting [MOS6526_CIA] best 27997 combination 
+Uplifting [MOS6569_VICII] best 27997 combination 
+Uplifting [MOS6581_SID] best 27997 combination 
+Uplifting [] best 27997 combination 
 Attempting to uplift remaining variables inzp[1]:41 [ bitmap_init::$5 ]
-Uplifting [bitmap_init] best 27939 combination reg byte a [ bitmap_init::$5 ] 
+Uplifting [bitmap_init] best 27937 combination reg byte a [ bitmap_init::$5 ] 
 Attempting to uplift remaining variables inzp[1]:42 [ bitmap_init::$6 ]
-Uplifting [bitmap_init] best 27879 combination reg byte a [ bitmap_init::$6 ] 
+Uplifting [bitmap_init] best 27877 combination reg byte a [ bitmap_init::$6 ] 
 Attempting to uplift remaining variables inzp[1]:8 [ bitmap_clear::y#4 bitmap_clear::y#1 ]
-Uplifting [bitmap_clear] best 27879 combination zp[1]:8 [ bitmap_clear::y#4 bitmap_clear::y#1 ] 
+Uplifting [bitmap_clear] best 27877 combination zp[1]:8 [ bitmap_clear::y#4 bitmap_clear::y#1 ] 
 Attempting to uplift remaining variables inzp[1]:12 [ screen_fill::y#4 screen_fill::y#1 ]
-Uplifting [screen_fill] best 27879 combination zp[1]:12 [ screen_fill::y#4 screen_fill::y#1 ] 
+Uplifting [screen_fill] best 27877 combination zp[1]:12 [ screen_fill::y#4 screen_fill::y#1 ] 
 Attempting to uplift remaining variables inzp[1]:39 [ bitmap_init::$7 ]
-Uplifting [bitmap_init] best 27879 combination zp[1]:39 [ bitmap_init::$7 ] 
+Uplifting [bitmap_init] best 27877 combination zp[1]:39 [ bitmap_init::$7 ] 
 Attempting to uplift remaining variables inzp[1]:2 [ main::i#2 main::i#1 ]
-Uplifting [main] best 27879 combination zp[1]:2 [ main::i#2 main::i#1 ] 
+Uplifting [main] best 27877 combination zp[1]:2 [ main::i#2 main::i#1 ] 
 Attempting to uplift remaining variables inzp[1]:34 [ point_init::point_idx#0 ]
-Uplifting [point_init] best 27879 combination zp[1]:34 [ point_init::point_idx#0 ] 
+Uplifting [point_init] best 27877 combination zp[1]:34 [ point_init::point_idx#0 ] 
 Attempting to uplift remaining variables inzp[1]:45 [ point_init::$13 ]
-Uplifting [point_init] best 27879 combination zp[1]:45 [ point_init::$13 ] 
+Uplifting [point_init] best 27877 combination zp[1]:45 [ point_init::$13 ] 
 Coalescing zero page register [ zp[2]:25 [ divr16s::return#2 divr16s::return#6 divr16s::return#1 ] ] with [ zp[2]:85 [ divr16s::resultu#0 ] ] - score: 2
 Coalescing zero page register [ zp[1]:2 [ main::i#2 main::i#1 ] ] with [ zp[1]:34 [ point_init::point_idx#0 ] ] - score: 1
 Coalescing zero page register [ zp[2]:9 [ bitmap_clear::bitmap#2 bitmap_clear::bitmap#3 bitmap_clear::bitmap#5 bitmap_clear::bitmap#1 ] ] with [ zp[2]:43 [ bitmap_clear::bitmap#0 ] ] - score: 1
@@ -3250,7 +3250,6 @@ bitmap_plot: {
     lda bitmap_plot_bit,x
     ldy #0
     ora (plotter),y
-    ldy #0
     sta (plotter),y
     jmp __breturn
     // bitmap_plot::@return
@@ -3570,7 +3569,6 @@ Replacing instruction ldy #0 with TAY
 Replacing instruction ldy.z __13 with TAY
 Removing instruction ldy.z point_idx
 Removing instruction ldy.z __13
-Removing instruction ldy #0
 Replacing instruction lda #<0 with TXA
 Removing instruction lda #>0
 Removing instruction lda #<0
diff --git a/src/test/ref/sinusgen8.asm b/src/test/ref/sinusgen8.asm
index 2f7cd6221..a112eed25 100644
--- a/src/test/ref/sinusgen8.asm
+++ b/src/test/ref/sinusgen8.asm
@@ -259,7 +259,7 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // char x1 = >x<<3
+    // char x1 = BYTE1(x<<3)
     lda.z __4+1
     sta.z x1
     // mulu8_sel(x1, x1, 0)
@@ -432,11 +432,11 @@ divr16u: {
     // rem = rem << 1
     asl.z rem
     rol.z rem+1
-    // >dividend
+    // BYTE1(dividend)
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     cmp #0
     beq __b2
     // rem = rem | 1
@@ -499,7 +499,7 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // >mul8u(v1, v2)<<select
+    // BYTE1(mul8u(v1, v2)<<select)
     lda.z __1+1
     // }
     rts
diff --git a/src/test/ref/sinusgen8.log b/src/test/ref/sinusgen8.log
index 9f130e152..94b7bb4ee 100644
--- a/src/test/ref/sinusgen8.log
+++ b/src/test/ref/sinusgen8.log
@@ -2927,7 +2927,7 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // [60] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_hi_vwuz2 
+    // [60] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_byte1_vwuz2 
     lda.z __4+1
     sta.z x1
     // [61] mulu8_sel::v1#0 = sin8s::x1#0 -- vbuxx=vbuz1 
@@ -3225,7 +3225,7 @@ divr16u: {
     // [115] divr16u::rem#0 = divr16u::rem#4 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // [116] divr16u::$1 = > divr16u::dividend#2 -- vbuaa=_hi_vwuz1 
+    // [116] divr16u::$1 = > divr16u::dividend#2 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
     // [117] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
@@ -3323,7 +3323,7 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // [137] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_hi_vwuz1 
+    // [137] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_byte1_vwuz1 
     lda.z __1+1
     jmp __breturn
     // mulu8_sel::@return
@@ -4203,8 +4203,8 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // char x1 = >x<<3
-    // [60] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_hi_vwuz2 
+    // char x1 = BYTE1(x<<3)
+    // [60] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_byte1_vwuz2 
     lda.z __4+1
     sta.z x1
     // mulu8_sel(x1, x1, 0)
@@ -4491,13 +4491,13 @@ divr16u: {
     // [115] divr16u::rem#0 = divr16u::rem#4 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // >dividend
-    // [116] divr16u::$1 = > divr16u::dividend#2 -- vbuaa=_hi_vwuz1 
+    // BYTE1(dividend)
+    // [116] divr16u::$1 = > divr16u::dividend#2 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     // [117] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     // [118] if(divr16u::$2==0) goto divr16u::@2 -- vbuaa_eq_0_then_la1 
     cmp #0
     beq __b2
@@ -4588,8 +4588,8 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // >mul8u(v1, v2)<<select
-    // [137] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_hi_vwuz1 
+    // BYTE1(mul8u(v1, v2)<<select)
+    // [137] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_byte1_vwuz1 
     lda.z __1+1
     // mulu8_sel::@return
     // }
diff --git a/src/test/ref/sinusgen8b.asm b/src/test/ref/sinusgen8b.asm
index 942e515bb..fc2be3e14 100644
--- a/src/test/ref/sinusgen8b.asm
+++ b/src/test/ref/sinusgen8b.asm
@@ -77,9 +77,9 @@ main: {
     sta.z sw+1
     pla
     sta.z sw
-    // >sw
+    // BYTE1(sw)
     lda.z sw+1
-    // signed byte sd = sb-(signed byte)>sw
+    // signed byte sd = sb-(signed byte)BYTE1(sw)
     eor #$ff
     sec
     adc.z sb
@@ -402,7 +402,7 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // char x1 = >x<<3
+    // char x1 = BYTE1(x<<3)
     lda.z __4+1
     sta.z x1
     // mulu8_sel(x1, x1, 0)
@@ -486,7 +486,7 @@ div32u16u: {
     .label return = $1b
     .label quotient_hi = $22
     .label quotient_lo = $2a
-    // divr16u(>dividend, divisor, 0)
+    // divr16u(WORD1(dividend), divisor, 0)
     lda #<PI2_u4f28>>$10
     sta.z divr16u.dividend
     lda #>PI2_u4f28>>$10
@@ -495,20 +495,20 @@ div32u16u: {
     sta.z divr16u.rem
     sta.z divr16u.rem+1
     jsr divr16u
-    // divr16u(>dividend, divisor, 0)
-    // unsigned int quotient_hi = divr16u(>dividend, divisor, 0)
+    // divr16u(WORD1(dividend), divisor, 0)
+    // unsigned int quotient_hi = divr16u(WORD1(dividend), divisor, 0)
     lda.z divr16u.return
     sta.z quotient_hi
     lda.z divr16u.return+1
     sta.z quotient_hi+1
-    // divr16u(<dividend, divisor, rem16u)
+    // divr16u(WORD0(dividend), divisor, rem16u)
     lda #<PI2_u4f28&$ffff
     sta.z divr16u.dividend
     lda #>PI2_u4f28&$ffff
     sta.z divr16u.dividend+1
     jsr divr16u
-    // divr16u(<dividend, divisor, rem16u)
-    // unsigned int quotient_lo = divr16u(<dividend, divisor, rem16u)
+    // divr16u(WORD0(dividend), divisor, rem16u)
+    // unsigned int quotient_lo = divr16u(WORD0(dividend), divisor, rem16u)
     // unsigned long quotient = { quotient_hi, quotient_lo}
     lda.z quotient_hi
     sta.z return+2
@@ -627,7 +627,7 @@ sin16s: {
     rol.z __4+1
     rol.z __4+2
     rol.z __4+3
-    // unsigned int x1 = >x<<3
+    // unsigned int x1 = WORD1(x<<3)
     lda.z __4+2
     sta.z x1
     lda.z __4+3
@@ -821,11 +821,11 @@ divr16u: {
     // rem = rem << 1
     asl.z rem
     rol.z rem+1
-    // >dividend
+    // BYTE1(dividend)
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     cmp #0
     beq __b2
     // rem = rem | 1
@@ -889,7 +889,7 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // >mul8u(v1, v2)<<select
+    // BYTE1(mul8u(v1, v2)<<select)
     lda.z __1+1
     // }
     rts
@@ -921,7 +921,7 @@ mulu16_sel: {
     dex
     bne !-
   !e:
-    // >mul16u(v1, v2)<<select
+    // WORD1(mul16u(v1, v2)<<select)
     lda.z __1+2
     sta.z return
     lda.z __1+3
diff --git a/src/test/ref/sinusgen8b.cfg b/src/test/ref/sinusgen8b.cfg
index dd420bbe0..678a0fc75 100644
--- a/src/test/ref/sinusgen8b.cfg
+++ b/src/test/ref/sinusgen8b.cfg
@@ -280,7 +280,7 @@ sin16s::@5: scope:[sin16s]  from sin16s::@1
 sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
   [134] sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
   [135] sin16s::$4 = sin16s::x#6 << 3
-  [136] sin16s::x1#0 = > sin16s::$4
+  [136] sin16s::x1#0 = _word1_ sin16s::$4
   [137] mulu16_sel::v1#0 = sin16s::x1#0
   [138] mulu16_sel::v2#0 = sin16s::x1#0
   [139] call mulu16_sel 
@@ -377,7 +377,7 @@ print_uchar::@return: scope:[print_uchar]  from print_uchar::@1
 
 word divr16u(word divr16u::dividend , word divr16u::divisor , word divr16u::rem)
 divr16u: scope:[divr16u]  from div16u div32u16u div32u16u::@1
-  [186] divr16u::dividend#6 = phi( div16u/PI2_u4f12, div32u16u/>PI2_u4f28, div32u16u::@1/<PI2_u4f28 )
+  [186] divr16u::dividend#6 = phi( div16u/PI2_u4f12, div32u16u/_word1_PI2_u4f28, div32u16u::@1/_word0_PI2_u4f28 )
   [186] divr16u::rem#11 = phi( div16u/0, div32u16u/0, div32u16u::@1/divr16u::rem#5 )
   to:divr16u::@1
 divr16u::@1: scope:[divr16u]  from divr16u divr16u::@3
@@ -448,7 +448,7 @@ mulu16_sel: scope:[mulu16_sel]  from sin16s::@10 sin16s::@2 sin16s::@7 sin16s::@
 mulu16_sel::@1: scope:[mulu16_sel]  from mulu16_sel
   [218] mulu16_sel::$0 = mul16u::return#0
   [219] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
-  [220] mulu16_sel::return#12 = > mulu16_sel::$1
+  [220] mulu16_sel::return#12 = _word1_ mulu16_sel::$1
   to:mulu16_sel::@return
 mulu16_sel::@return: scope:[mulu16_sel]  from mulu16_sel::@1
   [221] return 
diff --git a/src/test/ref/sinusgen8b.log b/src/test/ref/sinusgen8b.log
index 95457df75..4ced88861 100644
--- a/src/test/ref/sinusgen8b.log
+++ b/src/test/ref/sinusgen8b.log
@@ -153,7 +153,7 @@ sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
   sin16s::isUpper#7 = phi( sin16s::@1/sin16s::isUpper#8, sin16s::@5/sin16s::isUpper#9 )
   sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
   sin16s::$4 = sin16s::x#6 << 3
-  sin16s::$5 = > sin16s::$4
+  sin16s::$5 = _word1_ sin16s::$4
   sin16s::x1#0 = sin16s::$5
   mulu16_sel::v1#0 = sin16s::x1#0
   mulu16_sel::v2#0 = sin16s::x1#0
@@ -397,7 +397,7 @@ mulu16_sel::@1: scope:[mulu16_sel]  from mulu16_sel
   mul16u::return#3 = phi( mulu16_sel/mul16u::return#0 )
   mulu16_sel::$0 = mul16u::return#3
   mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
-  mulu16_sel::$2 = > mulu16_sel::$1
+  mulu16_sel::$2 = _word1_ mulu16_sel::$1
   mulu16_sel::return#5 = mulu16_sel::$2
   to:mulu16_sel::@return
 mulu16_sel::@return: scope:[mulu16_sel]  from mulu16_sel::@1
@@ -540,7 +540,7 @@ div32u16u: scope:[div32u16u]  from sin16s_gen
   rem16u#37 = phi( sin16s_gen/rem16u#32 )
   div32u16u::divisor#1 = phi( sin16s_gen/div32u16u::divisor#0 )
   div32u16u::dividend#1 = phi( sin16s_gen/div32u16u::dividend#0 )
-  div32u16u::$0 = > div32u16u::dividend#1
+  div32u16u::$0 = _word1_ div32u16u::dividend#1
   divr16u::dividend#2 = div32u16u::$0
   divr16u::divisor#1 = div32u16u::divisor#1
   divr16u::rem#4 = 0
@@ -555,7 +555,7 @@ div32u16u::@1: scope:[div32u16u]  from div32u16u
   div32u16u::$1 = divr16u::return#7
   rem16u#8 = rem16u#24
   div32u16u::quotient_hi#0 = div32u16u::$1
-  div32u16u::$2 = < div32u16u::dividend#2
+  div32u16u::$2 = _word0_ div32u16u::dividend#2
   divr16u::dividend#3 = div32u16u::$2
   divr16u::divisor#2 = div32u16u::divisor#2
   divr16u::rem#5 = rem16u#8
@@ -2253,12 +2253,12 @@ Successful SSA optimization PassNCastSimplification
 Finalized unsigned number type (byte) $10
 Finalized unsigned number type (byte) $c0
 Successful SSA optimization PassNFinalizeNumberTypeConversions
-Constant right-side identified [151] divr16u::dividend#2 = > div32u16u::dividend#0
-Constant right-side identified [155] divr16u::dividend#3 = < div32u16u::dividend#0
+Constant right-side identified [151] divr16u::dividend#2 = _word1_ div32u16u::dividend#0
+Constant right-side identified [155] divr16u::dividend#3 = _word0_ div32u16u::dividend#0
 Constant right-side identified [209] memset::end#0 = memset::$4 + memset::num#0
 Successful SSA optimization Pass2ConstantRValueConsolidation
-Constant divr16u::dividend#2 = >div32u16u::dividend#0
-Constant divr16u::dividend#3 = <div32u16u::dividend#0
+Constant divr16u::dividend#2 = _word1_div32u16u::dividend#0
+Constant divr16u::dividend#3 = _word0_div32u16u::dividend#0
 Constant memset::end#0 = memset::$4+memset::num#0
 Successful SSA optimization Pass2ConstantIdentification
 Inlining Noop Cast [62] sin16s::sinx#0 = (signed word)sin16s::usinx#1 keeping sin16s::usinx#1
@@ -2338,8 +2338,8 @@ Constant inlined divr16u::divisor#2 = main::wavelength
 Constant inlined mulu8_sel::select#3 = 0
 Constant inlined sin16s_gen::i#0 = 0
 Constant inlined divr16u::dividend#1 = PI2_u4f12
-Constant inlined divr16u::dividend#2 = >PI2_u4f28
-Constant inlined divr16u::dividend#3 = <PI2_u4f28
+Constant inlined divr16u::dividend#2 = _word1_PI2_u4f28
+Constant inlined divr16u::dividend#3 = _word0_PI2_u4f28
 Constant inlined sin16s_gen::sintab#1 = main::sintabw
 Constant inlined print_char::ch#2 = ' '
 Constant inlined mulu8_sel::v2#2 = sin8s::DIV_6
@@ -2822,7 +2822,7 @@ sin16s::@5: scope:[sin16s]  from sin16s::@1
 sin16s::@2: scope:[sin16s]  from sin16s::@1 sin16s::@5
   [134] sin16s::x#6 = phi( sin16s::@1/sin16s::x#4, sin16s::@5/sin16s::x#2 )
   [135] sin16s::$4 = sin16s::x#6 << 3
-  [136] sin16s::x1#0 = > sin16s::$4
+  [136] sin16s::x1#0 = _word1_ sin16s::$4
   [137] mulu16_sel::v1#0 = sin16s::x1#0
   [138] mulu16_sel::v2#0 = sin16s::x1#0
   [139] call mulu16_sel 
@@ -2919,7 +2919,7 @@ print_uchar::@return: scope:[print_uchar]  from print_uchar::@1
 
 word divr16u(word divr16u::dividend , word divr16u::divisor , word divr16u::rem)
 divr16u: scope:[divr16u]  from div16u div32u16u div32u16u::@1
-  [186] divr16u::dividend#6 = phi( div16u/PI2_u4f12, div32u16u/>PI2_u4f28, div32u16u::@1/<PI2_u4f28 )
+  [186] divr16u::dividend#6 = phi( div16u/PI2_u4f12, div32u16u/_word1_PI2_u4f28, div32u16u::@1/_word0_PI2_u4f28 )
   [186] divr16u::rem#11 = phi( div16u/0, div32u16u/0, div32u16u::@1/divr16u::rem#5 )
   to:divr16u::@1
 divr16u::@1: scope:[divr16u]  from divr16u divr16u::@3
@@ -2990,7 +2990,7 @@ mulu16_sel: scope:[mulu16_sel]  from sin16s::@10 sin16s::@2 sin16s::@7 sin16s::@
 mulu16_sel::@1: scope:[mulu16_sel]  from mulu16_sel
   [218] mulu16_sel::$0 = mul16u::return#0
   [219] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5
-  [220] mulu16_sel::return#12 = > mulu16_sel::$1
+  [220] mulu16_sel::return#12 = _word1_ mulu16_sel::$1
   to:mulu16_sel::@return
 mulu16_sel::@return: scope:[mulu16_sel]  from mulu16_sel::@1
   [221] return 
@@ -3700,7 +3700,7 @@ Statement [132] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 [ sin16s::x#4 sin1
 Removing always clobbered register reg byte a as potential for zp[1]:25 [ sin16s::isUpper#2 ]
 Statement [133] sin16s::x#2 = PI_u4f28 - sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x#2 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
 Statement [135] sin16s::$4 = sin16s::x#6 << 3 [ sin16s::isUpper#2 sin16s::$4 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::$4 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
-Statement [136] sin16s::x1#0 = > sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
+Statement [136] sin16s::x1#0 = _word1_ sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [137] mulu16_sel::v1#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [138] mulu16_sel::v2#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [140] mulu16_sel::return#0 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
@@ -3748,7 +3748,7 @@ Statement [215] mul16u::b#0 = mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#
 Statement [217] mul16u::return#0 = mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#0 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 mul16u::a#0 mul16u::b#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 mul16u::a#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mulu16_sel::v2#5 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 mul16u::a#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
 Statement [218] mulu16_sel::$0 = mul16u::return#0 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [219] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 [ mulu16_sel::$1 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
-Statement [220] mulu16_sel::return#12 = > mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
+Statement [220] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [222] mul8u::mb#0 = (word)mul8u::b#0 [ mul8u::a#0 mul8u::mb#0 ] ( sin8s_gen:1::sin8s:29::mulu8_sel:86::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v2#0 = mulu8_sel::v2#5 mulu8_sel::v1#5 mulu8_sel::v1#0 sin8s::x1#0 mul8u::a#0 mul8u::b#0 } { mulu8_sel::return#0 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:91::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#1 = mulu8_sel::v1#5 sin8s::x2#0 mul8u::a#0 } { mulu8_sel::v2#1 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#1 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:95::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#2 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::return#12 = mulu8_sel::return#2 } { mul8u::b#0 = mulu8_sel::v2#5 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:101::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#3 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::v2#3 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#10 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:106::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#4 = mulu8_sel::v1#5 sin8s::x4#0 mul8u::a#0 } { mulu8_sel::v2#4 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#11 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  ) always clobbers reg byte a 
 Removing always clobbered register reg byte a as potential for zp[1]:52 [ mul8u::a#2 mul8u::a#0 mul8u::a#1 ]
 Statement [226] mul8u::$1 = mul8u::a#2 & 1 [ mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] ( sin8s_gen:1::sin8s:29::mulu8_sel:86::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v2#0 = mulu8_sel::v2#5 mulu8_sel::v1#5 mulu8_sel::v1#0 sin8s::x1#0 mul8u::a#0 mul8u::b#0 } { mulu8_sel::return#0 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:91::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#1 = mulu8_sel::v1#5 sin8s::x2#0 mul8u::a#0 } { mulu8_sel::v2#1 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#1 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:95::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#2 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::return#12 = mulu8_sel::return#2 } { mul8u::b#0 = mulu8_sel::v2#5 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:101::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#3 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::v2#3 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#10 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:106::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#4 = mulu8_sel::v1#5 sin8s::x4#0 mul8u::a#0 } { mulu8_sel::v2#4 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#11 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  ) always clobbers reg byte a 
@@ -3802,7 +3802,7 @@ Statement [130] sin16s::x#1 = sin16s::x#0 - PI_u4f28 [ sin16s::x#1 ] ( sin16s_ge
 Statement [132] if(sin16s::x#4<PI_HALF_u4f28) goto sin16s::@2 [ sin16s::x#4 sin16s::isUpper#2 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::x#4 sin16s::isUpper#2 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
 Statement [133] sin16s::x#2 = PI_u4f28 - sin16s::x#4 [ sin16s::isUpper#2 sin16s::x#2 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x#2 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } }  ) always clobbers reg byte a 
 Statement [135] sin16s::$4 = sin16s::x#6 << 3 [ sin16s::isUpper#2 sin16s::$4 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::$4 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
-Statement [136] sin16s::x1#0 = > sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
+Statement [136] sin16s::x1#0 = _word1_ sin16s::$4 [ sin16s::isUpper#2 sin16s::x1#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [137] mulu16_sel::v1#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [138] mulu16_sel::v2#0 = sin16s::x1#0 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::v1#0 mulu16_sel::v2#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [140] mulu16_sel::return#0 = mulu16_sel::return#12 [ sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] ( sin16s_gen:3::sin16s:44 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
@@ -3844,7 +3844,7 @@ Statement [215] mul16u::b#0 = mulu16_sel::v2#5 [ mulu16_sel::select#5 mul16u::a#
 Statement [217] mul16u::return#0 = mul16u::res#2 [ mulu16_sel::select#5 mul16u::return#0 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 mul16u::a#0 mul16u::b#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 mul16u::a#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } { mul16u::b#0 = mulu16_sel::v2#5 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 mul16u::a#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mul16u::return#0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 mul16u::a#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 mul16u::b#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } { mul16u::return#0 = mul16u::res#2 } }  ) always clobbers reg byte a 
 Statement [218] mulu16_sel::$0 = mul16u::return#0 [ mulu16_sel::select#5 mulu16_sel::$0 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::select#5 mulu16_sel::$0 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [219] mulu16_sel::$1 = mulu16_sel::$0 << mulu16_sel::select#5 [ mulu16_sel::$1 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::$1 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
-Statement [220] mulu16_sel::return#12 = > mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
+Statement [220] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 [ mulu16_sel::return#12 ] ( sin16s_gen:3::sin16s:44::mulu16_sel:139 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v2#0 = mulu16_sel::v2#5 mulu16_sel::v1#5 mulu16_sel::v1#0 sin16s::x1#0 } { mulu16_sel::return#0 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:144 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#1 = mulu16_sel::v1#5 sin16s::x2#0 } { mulu16_sel::v2#1 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#1 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:148 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::x3#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#2 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::return#12 = mulu16_sel::return#2 } }  sin16s_gen:3::sin16s:44::mulu16_sel:154 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::x1#0 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#3 = mulu16_sel::v1#5 sin16s::x3#0 } { mulu16_sel::v2#3 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#10 = mulu16_sel::return#12 } }  sin16s_gen:3::sin16s:44::mulu16_sel:159 [ sin16s_gen::step#0 sin16s_gen::i#2 sin16s_gen::x#2 sin16s_gen::sintab#2 sin16s::isUpper#2 sin16s::usinx#0 mulu16_sel::return#12 ] { { sin16s::x#0 = sin16s_gen::x#2 } { sin16s::return#0 = sin16s::return#1 } { mulu16_sel::v1#4 = mulu16_sel::v1#5 sin16s::x4#0 } { mulu16_sel::v2#4 = mulu16_sel::v2#5 sin16s::x1#0 } { mulu16_sel::return#11 = mulu16_sel::return#12 } }  ) always clobbers reg byte a 
 Statement [222] mul8u::mb#0 = (word)mul8u::b#0 [ mul8u::a#0 mul8u::mb#0 ] ( sin8s_gen:1::sin8s:29::mulu8_sel:86::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v2#0 = mulu8_sel::v2#5 mulu8_sel::v1#5 mulu8_sel::v1#0 sin8s::x1#0 mul8u::a#0 mul8u::b#0 } { mulu8_sel::return#0 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:91::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#1 = mulu8_sel::v1#5 sin8s::x2#0 mul8u::a#0 } { mulu8_sel::v2#1 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#1 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:95::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#2 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::return#12 = mulu8_sel::return#2 } { mul8u::b#0 = mulu8_sel::v2#5 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:101::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#3 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::v2#3 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#10 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:106::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#0 mul8u::mb#0 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#4 = mulu8_sel::v1#5 sin8s::x4#0 mul8u::a#0 } { mulu8_sel::v2#4 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#11 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  ) always clobbers reg byte a 
 Statement [226] mul8u::$1 = mul8u::a#2 & 1 [ mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] ( sin8s_gen:1::sin8s:29::mulu8_sel:86::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v2#0 = mulu8_sel::v2#5 mulu8_sel::v1#5 mulu8_sel::v1#0 sin8s::x1#0 mul8u::a#0 mul8u::b#0 } { mulu8_sel::return#0 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:91::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#1 = mulu8_sel::v1#5 sin8s::x2#0 mul8u::a#0 } { mulu8_sel::v2#1 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#1 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:95::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#2 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::return#12 = mulu8_sel::return#2 } { mul8u::b#0 = mulu8_sel::v2#5 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:101::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#3 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::v2#3 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#10 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:106::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::res#2 mul8u::a#2 mul8u::mb#2 mul8u::$1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#4 = mulu8_sel::v1#5 sin8s::x4#0 mul8u::a#0 } { mulu8_sel::v2#4 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#11 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  ) always clobbers reg byte a 
 Statement [228] mul8u::res#1 = mul8u::res#2 + mul8u::mb#2 [ mul8u::a#2 mul8u::mb#2 mul8u::res#1 ] ( sin8s_gen:1::sin8s:29::mulu8_sel:86::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#2 mul8u::mb#2 mul8u::res#1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v2#0 = mulu8_sel::v2#5 mulu8_sel::v1#5 mulu8_sel::v1#0 sin8s::x1#0 mul8u::a#0 mul8u::b#0 } { mulu8_sel::return#0 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:91::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 mulu8_sel::select#5 mul8u::a#2 mul8u::mb#2 mul8u::res#1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#1 = mulu8_sel::v1#5 sin8s::x2#0 mul8u::a#0 } { mulu8_sel::v2#1 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#1 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:95::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::x3#0 mulu8_sel::select#5 mul8u::a#2 mul8u::mb#2 mul8u::res#1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#2 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::return#12 = mulu8_sel::return#2 } { mul8u::b#0 = mulu8_sel::v2#5 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:101::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::x1#0 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#2 mul8u::mb#2 mul8u::res#1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#3 = mulu8_sel::v1#5 sin8s::x3#0 mul8u::a#0 } { mulu8_sel::v2#3 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#10 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  sin8s_gen:1::sin8s:29::mulu8_sel:106::mul8u:207 [ sin8s_gen::step#0 sin8s_gen::i#2 sin8s_gen::x#2 sin8s_gen::sintab#2 sin8s::isUpper#10 sin8s::usinx#0 mulu8_sel::select#5 mul8u::a#2 mul8u::mb#2 mul8u::res#1 ] { { sin8s::x#0 = sin8s_gen::x#2 } { sin8s::return#0 = sin8s::return#1 } { mulu8_sel::v1#4 = mulu8_sel::v1#5 sin8s::x4#0 mul8u::a#0 } { mulu8_sel::v2#4 = mulu8_sel::v2#5 sin8s::x1#0 mul8u::b#0 } { mulu8_sel::return#11 = mulu8_sel::return#12 } { mul8u::return#0 = mul8u::res#2 } }  ) always clobbers reg byte a 
@@ -4215,7 +4215,7 @@ main: {
     sta.z sw+1
     pla
     sta.z sw
-    // [12] main::$11 = > main::sw#0 -- vbuaa=_hi_vwsz1 
+    // [12] main::$11 = > main::sw#0 -- vbuaa=_byte1_vwsz1 
     lda.z sw+1
     // [13] main::sd#0 = main::sb#0 - (signed byte)main::$11 -- vbsaa=vbsz1_minus_vbsaa 
     eor #$ff
@@ -4709,7 +4709,7 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // [83] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_hi_vwuz2 
+    // [83] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_byte1_vwuz2 
     lda.z __4+1
     sta.z x1
     // [84] mulu8_sel::v1#0 = sin8s::x1#0 -- vbuxx=vbuz1 
@@ -4870,7 +4870,7 @@ div32u16u: {
     // [120] call divr16u 
     // [186] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
   divr16u_from_div32u16u:
-    // [186] phi divr16u::dividend#6 = >PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
+    // [186] phi divr16u::dividend#6 = _word1_PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
     lda #<PI2_u4f28>>$10
     sta.z divr16u.dividend
     lda #>PI2_u4f28>>$10
@@ -4894,7 +4894,7 @@ div32u16u: {
     // [124] call divr16u 
     // [186] phi from div32u16u::@1 to divr16u [phi:div32u16u::@1->divr16u]
   divr16u_from___b1:
-    // [186] phi divr16u::dividend#6 = <PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
+    // [186] phi divr16u::dividend#6 = _word0_PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
     lda #<PI2_u4f28&$ffff
     sta.z divr16u.dividend
     lda #>PI2_u4f28&$ffff
@@ -5049,7 +5049,7 @@ sin16s: {
     rol.z __4+1
     rol.z __4+2
     rol.z __4+3
-    // [136] sin16s::x1#0 = > sin16s::$4 -- vwuz1=_hi_vduz2 
+    // [136] sin16s::x1#0 = _word1_ sin16s::$4 -- vwuz1=_word1_vduz2 
     lda.z __4+2
     sta.z x1
     lda.z __4+3
@@ -5359,7 +5359,7 @@ divr16u: {
     // [188] divr16u::rem#0 = divr16u::rem#6 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // [189] divr16u::$1 = > divr16u::dividend#4 -- vbuaa=_hi_vwuz1 
+    // [189] divr16u::$1 = > divr16u::dividend#4 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
     // [190] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
@@ -5461,7 +5461,7 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // [211] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_hi_vwuz1 
+    // [211] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_byte1_vwuz1 
     lda.z __1+1
     jmp __breturn
     // mulu8_sel::@return
@@ -5504,7 +5504,7 @@ mulu16_sel: {
     dex
     bne !-
   !e:
-    // [220] mulu16_sel::return#12 = > mulu16_sel::$1 -- vwuz1=_hi_vduz2 
+    // [220] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 -- vwuz1=_word1_vduz2 
     lda.z __1+2
     sta.z return
     lda.z __1+3
@@ -6405,10 +6405,10 @@ main: {
     sta.z sw+1
     pla
     sta.z sw
-    // >sw
-    // [12] main::$11 = > main::sw#0 -- vbuaa=_hi_vwsz1 
+    // BYTE1(sw)
+    // [12] main::$11 = > main::sw#0 -- vbuaa=_byte1_vwsz1 
     lda.z sw+1
-    // signed byte sd = sb-(signed byte)>sw
+    // signed byte sd = sb-(signed byte)BYTE1(sw)
     // [13] main::sd#0 = main::sb#0 - (signed byte)main::$11 -- vbsaa=vbsz1_minus_vbsaa 
     eor #$ff
     sec
@@ -6872,8 +6872,8 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // char x1 = >x<<3
-    // [83] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_hi_vwuz2 
+    // char x1 = BYTE1(x<<3)
+    // [83] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_byte1_vwuz2 
     lda.z __4+1
     sta.z x1
     // mulu8_sel(x1, x1, 0)
@@ -7026,10 +7026,10 @@ div32u16u: {
     .label return = $1b
     .label quotient_hi = $22
     .label quotient_lo = $2a
-    // divr16u(>dividend, divisor, 0)
+    // divr16u(WORD1(dividend), divisor, 0)
     // [120] call divr16u 
     // [186] phi from div32u16u to divr16u [phi:div32u16u->divr16u]
-    // [186] phi divr16u::dividend#6 = >PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
+    // [186] phi divr16u::dividend#6 = _word1_PI2_u4f28 [phi:div32u16u->divr16u#0] -- vwuz1=vwuc1 
     lda #<PI2_u4f28>>$10
     sta.z divr16u.dividend
     lda #>PI2_u4f28>>$10
@@ -7039,30 +7039,30 @@ div32u16u: {
     sta.z divr16u.rem
     sta.z divr16u.rem+1
     jsr divr16u
-    // divr16u(>dividend, divisor, 0)
+    // divr16u(WORD1(dividend), divisor, 0)
     // [121] divr16u::return#3 = divr16u::return#0
     // div32u16u::@1
-    // unsigned int quotient_hi = divr16u(>dividend, divisor, 0)
+    // unsigned int quotient_hi = divr16u(WORD1(dividend), divisor, 0)
     // [122] div32u16u::quotient_hi#0 = divr16u::return#3 -- vwuz1=vwuz2 
     lda.z divr16u.return
     sta.z quotient_hi
     lda.z divr16u.return+1
     sta.z quotient_hi+1
-    // divr16u(<dividend, divisor, rem16u)
+    // divr16u(WORD0(dividend), divisor, rem16u)
     // [123] divr16u::rem#5 = rem16u#21
     // [124] call divr16u 
     // [186] phi from div32u16u::@1 to divr16u [phi:div32u16u::@1->divr16u]
-    // [186] phi divr16u::dividend#6 = <PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
+    // [186] phi divr16u::dividend#6 = _word0_PI2_u4f28 [phi:div32u16u::@1->divr16u#0] -- vwuz1=vwuc1 
     lda #<PI2_u4f28&$ffff
     sta.z divr16u.dividend
     lda #>PI2_u4f28&$ffff
     sta.z divr16u.dividend+1
     // [186] phi divr16u::rem#11 = divr16u::rem#5 [phi:div32u16u::@1->divr16u#1] -- register_copy 
     jsr divr16u
-    // divr16u(<dividend, divisor, rem16u)
+    // divr16u(WORD0(dividend), divisor, rem16u)
     // [125] divr16u::return#4 = divr16u::return#0
     // div32u16u::@2
-    // unsigned int quotient_lo = divr16u(<dividend, divisor, rem16u)
+    // unsigned int quotient_lo = divr16u(WORD0(dividend), divisor, rem16u)
     // [126] div32u16u::quotient_lo#0 = divr16u::return#4
     // unsigned long quotient = { quotient_hi, quotient_lo}
     // [127] div32u16u::return#1 = div32u16u::quotient_hi#0 dw= div32u16u::quotient_lo#0 -- vduz1=vwuz2_dword_vwuz3 
@@ -7203,8 +7203,8 @@ sin16s: {
     rol.z __4+1
     rol.z __4+2
     rol.z __4+3
-    // unsigned int x1 = >x<<3
-    // [136] sin16s::x1#0 = > sin16s::$4 -- vwuz1=_hi_vduz2 
+    // unsigned int x1 = WORD1(x<<3)
+    // [136] sin16s::x1#0 = _word1_ sin16s::$4 -- vwuz1=_word1_vduz2 
     lda.z __4+2
     sta.z x1
     lda.z __4+3
@@ -7506,13 +7506,13 @@ divr16u: {
     // [188] divr16u::rem#0 = divr16u::rem#6 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // >dividend
-    // [189] divr16u::$1 = > divr16u::dividend#4 -- vbuaa=_hi_vwuz1 
+    // BYTE1(dividend)
+    // [189] divr16u::$1 = > divr16u::dividend#4 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     // [190] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     // [191] if(divr16u::$2==0) goto divr16u::@2 -- vbuaa_eq_0_then_la1 
     cmp #0
     beq __b2
@@ -7606,8 +7606,8 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // >mul8u(v1, v2)<<select
-    // [211] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_hi_vwuz1 
+    // BYTE1(mul8u(v1, v2)<<select)
+    // [211] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_byte1_vwuz1 
     lda.z __1+1
     // mulu8_sel::@return
     // }
@@ -7649,8 +7649,8 @@ mulu16_sel: {
     dex
     bne !-
   !e:
-    // >mul16u(v1, v2)<<select
-    // [220] mulu16_sel::return#12 = > mulu16_sel::$1 -- vwuz1=_hi_vduz2 
+    // WORD1(mul16u(v1, v2)<<select)
+    // [220] mulu16_sel::return#12 = _word1_ mulu16_sel::$1 -- vwuz1=_word1_vduz2 
     lda.z __1+2
     sta.z return
     lda.z __1+3
diff --git a/src/test/ref/sinusgenscale8.asm b/src/test/ref/sinusgenscale8.asm
index 42288bcb2..496c2bd5d 100644
--- a/src/test/ref/sinusgenscale8.asm
+++ b/src/test/ref/sinusgenscale8.asm
@@ -158,9 +158,9 @@ sin8u_table: {
     tay
     jsr mul8su
     // signed word sinx_sc = mul8su(sinx, amplitude+1)
-    // >sinx_sc
+    // BYTE1(sinx_sc)
     lda.z sinx_sc+1
-    // byte sinx_tr = mid+>sinx_sc
+    // byte sinx_tr = mid+BYTE1(sinx_sc)
     clc
     adc #mid
     sta.z sinx_tr
@@ -328,10 +328,10 @@ print_str: {
 // print_uint(word zp($c) w)
 print_uint: {
     .label w = $c
-    // print_uchar(>w)
+    // print_uchar(BYTE1(w))
     ldx.z w+1
     jsr print_uchar
-    // print_uchar(<w)
+    // print_uchar(BYTE0(w))
     ldx.z w
     jsr print_uchar
     // }
@@ -446,7 +446,7 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // char x1 = >x<<3
+    // char x1 = BYTE1(x<<3)
     lda.z __4+1
     sta.z x1
     // mulu8_sel(x1, x1, 0)
@@ -540,9 +540,9 @@ mul8su: {
     // if(a<0)
     cpy #0
     bpl __b1
-    // >m
+    // BYTE1(m)
     lda.z m+1
-    // >m = (>m)-(char)b
+    // BYTE1(m) = BYTE1(m)-(char)b
     sec
     sbc #b
     sta.z m+1
@@ -630,11 +630,11 @@ divr16u: {
     // rem = rem << 1
     asl.z rem
     rol.z rem+1
-    // >dividend
+    // BYTE1(dividend)
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     cmp #0
     beq __b2
     // rem = rem | 1
@@ -712,7 +712,7 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // >mul8u(v1, v2)<<select
+    // BYTE1(mul8u(v1, v2)<<select)
     lda.z __1+1
     // }
     rts
diff --git a/src/test/ref/sinusgenscale8.cfg b/src/test/ref/sinusgenscale8.cfg
index bc9afc304..10bde0b87 100644
--- a/src/test/ref/sinusgenscale8.cfg
+++ b/src/test/ref/sinusgenscale8.cfg
@@ -322,7 +322,7 @@ mul8su::@3: scope:[mul8su]  from mul8su
 mul8su::@2: scope:[mul8su]  from mul8su::@3
   [152] mul8su::$4 = > mul8su::m#0
   [153] mul8su::$6 = mul8su::$4 - mul8su::b#0
-  [154] mul8su::m#1 = mul8su::m#0 hi= mul8su::$6
+  [154] mul8su::m#1 = mul8su::m#0 byte1= mul8su::$6
   to:mul8su::@1
 mul8su::@1: scope:[mul8su]  from mul8su::@2 mul8su::@3
   [155] mul8su::m#2 = phi( mul8su::@2/mul8su::m#1, mul8su::@3/mul8su::m#0 )
diff --git a/src/test/ref/sinusgenscale8.log b/src/test/ref/sinusgenscale8.log
index a587c0157..750e18926 100644
--- a/src/test/ref/sinusgenscale8.log
+++ b/src/test/ref/sinusgenscale8.log
@@ -334,7 +334,7 @@ mul8su::@2: scope:[mul8su]  from mul8su::@3
   mul8su::$7 = (byte)mul8su::b#2
   mul8su::$5 = mul8su::$4 - mul8su::$7
   mul8su::$6 = mul8su::$5
-  mul8su::m#1 = mul8su::m#3 hi= mul8su::$6
+  mul8su::m#1 = mul8su::m#3 byte1= mul8su::$6
   to:mul8su::@1
 mul8su::@return: scope:[mul8su]  from mul8su::@1
   mul8su::return#3 = phi( mul8su::@1/mul8su::return#0 )
@@ -3007,7 +3007,7 @@ mul8su::@3: scope:[mul8su]  from mul8su
 mul8su::@2: scope:[mul8su]  from mul8su::@3
   [152] mul8su::$4 = > mul8su::m#0
   [153] mul8su::$6 = mul8su::$4 - mul8su::b#0
-  [154] mul8su::m#1 = mul8su::m#0 hi= mul8su::$6
+  [154] mul8su::m#1 = mul8su::m#0 byte1= mul8su::$6
   to:mul8su::@1
 mul8su::@1: scope:[mul8su]  from mul8su::@2 mul8su::@3
   [155] mul8su::m#2 = phi( mul8su::@2/mul8su::m#1, mul8su::@3/mul8su::m#0 )
@@ -4149,7 +4149,7 @@ sin8u_table: {
     // sin8u_table::@15
   __b15:
     // [42] sin8u_table::sinx_sc#0 = (signed word)mul8su::m#2
-    // [43] sin8u_table::$20 = > sin8u_table::sinx_sc#0 -- vbuaa=_hi_vwsz1 
+    // [43] sin8u_table::$20 = > sin8u_table::sinx_sc#0 -- vbuaa=_byte1_vwsz1 
     lda.z sinx_sc+1
     // [44] sin8u_table::sinx_tr#0 = sin8u_table::mid#0 + sin8u_table::$20 -- vbuz1=vbuc1_plus_vbuaa 
     clc
@@ -4436,7 +4436,7 @@ print_str: {
 // print_uint(word zp($c) w)
 print_uint: {
     .label w = $c
-    // [86] print_uchar::b#1 = > print_uint::w#3 -- vbuxx=_hi_vwuz1 
+    // [86] print_uchar::b#1 = > print_uint::w#3 -- vbuxx=_byte1_vwuz1 
     ldx.z w+1
     // [87] call print_uchar 
     // [91] phi from print_uint to print_uchar [phi:print_uint->print_uchar]
@@ -4447,7 +4447,7 @@ print_uint: {
     jmp __b1
     // print_uint::@1
   __b1:
-    // [88] print_uchar::b#2 = < print_uint::w#3 -- vbuxx=_lo_vwuz1 
+    // [88] print_uchar::b#2 = < print_uint::w#3 -- vbuxx=_byte0_vwuz1 
     ldx.z w
     // [89] call print_uchar 
     // [91] phi from print_uint::@1 to print_uchar [phi:print_uint::@1->print_uchar]
@@ -4619,7 +4619,7 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // [111] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_hi_vwuz2 
+    // [111] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_byte1_vwuz2 
     lda.z __4+1
     sta.z x1
     // [112] mulu8_sel::v1#0 = sin8s::x1#0 -- vbuxx=vbuz1 
@@ -4798,12 +4798,12 @@ mul8su: {
     jmp __b2
     // mul8su::@2
   __b2:
-    // [152] mul8su::$4 = > mul8su::m#0 -- vbuaa=_hi_vwuz1 
+    // [152] mul8su::$4 = > mul8su::m#0 -- vbuaa=_byte1_vwuz1 
     lda.z m+1
     // [153] mul8su::$6 = mul8su::$4 - mul8su::b#0 -- vbuaa=vbuaa_minus_vbuc1 
     sec
     sbc #b
-    // [154] mul8su::m#1 = mul8su::m#0 hi= mul8su::$6 -- vwuz1=vwuz1_sethi_vbuaa 
+    // [154] mul8su::m#1 = mul8su::m#0 byte1= mul8su::$6 -- vwuz1=vwuz1_setbyte1_vbuaa 
     sta.z m+1
     // [155] phi from mul8su::@2 mul8su::@3 to mul8su::@1 [phi:mul8su::@2/mul8su::@3->mul8su::@1]
   __b1_from___b2:
@@ -4986,7 +4986,7 @@ divr16u: {
     // [179] divr16u::rem#0 = divr16u::rem#4 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // [180] divr16u::$1 = > divr16u::dividend#2 -- vbuaa=_hi_vwuz1 
+    // [180] divr16u::$1 = > divr16u::dividend#2 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
     // [181] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
@@ -5106,7 +5106,7 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // [205] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_hi_vwuz1 
+    // [205] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_byte1_vwuz1 
     lda.z __1+1
     jmp __breturn
     // mulu8_sel::@return
@@ -6024,10 +6024,10 @@ sin8u_table: {
     // sin8u_table::@15
     // signed word sinx_sc = mul8su(sinx, amplitude+1)
     // [42] sin8u_table::sinx_sc#0 = (signed word)mul8su::m#2
-    // >sinx_sc
-    // [43] sin8u_table::$20 = > sin8u_table::sinx_sc#0 -- vbuaa=_hi_vwsz1 
+    // BYTE1(sinx_sc)
+    // [43] sin8u_table::$20 = > sin8u_table::sinx_sc#0 -- vbuaa=_byte1_vwsz1 
     lda.z sinx_sc+1
-    // byte sinx_tr = mid+>sinx_sc
+    // byte sinx_tr = mid+BYTE1(sinx_sc)
     // [44] sin8u_table::sinx_tr#0 = sin8u_table::mid#0 + sin8u_table::$20 -- vbuz1=vbuc1_plus_vbuaa 
     clc
     adc #mid
@@ -6288,8 +6288,8 @@ print_str: {
 // print_uint(word zp($c) w)
 print_uint: {
     .label w = $c
-    // print_uchar(>w)
-    // [86] print_uchar::b#1 = > print_uint::w#3 -- vbuxx=_hi_vwuz1 
+    // print_uchar(BYTE1(w))
+    // [86] print_uchar::b#1 = > print_uint::w#3 -- vbuxx=_byte1_vwuz1 
     ldx.z w+1
     // [87] call print_uchar 
     // [91] phi from print_uint to print_uchar [phi:print_uint->print_uchar]
@@ -6297,8 +6297,8 @@ print_uint: {
     // [91] phi print_uchar::b#8 = print_uchar::b#1 [phi:print_uint->print_uchar#1] -- register_copy 
     jsr print_uchar
     // print_uint::@1
-    // print_uchar(<w)
-    // [88] print_uchar::b#2 = < print_uint::w#3 -- vbuxx=_lo_vwuz1 
+    // print_uchar(BYTE0(w))
+    // [88] print_uchar::b#2 = < print_uint::w#3 -- vbuxx=_byte0_vwuz1 
     ldx.z w
     // [89] call print_uchar 
     // [91] phi from print_uint::@1 to print_uchar [phi:print_uint::@1->print_uchar]
@@ -6461,8 +6461,8 @@ sin8s: {
     rol.z __4+1
     asl.z __4
     rol.z __4+1
-    // char x1 = >x<<3
-    // [111] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_hi_vwuz2 
+    // char x1 = BYTE1(x<<3)
+    // [111] sin8s::x1#0 = > sin8s::$4 -- vbuz1=_byte1_vwuz2 
     lda.z __4+1
     sta.z x1
     // mulu8_sel(x1, x1, 0)
@@ -6635,14 +6635,14 @@ mul8su: {
     cpy #0
     bpl __b1
     // mul8su::@2
-    // >m
-    // [152] mul8su::$4 = > mul8su::m#0 -- vbuaa=_hi_vwuz1 
+    // BYTE1(m)
+    // [152] mul8su::$4 = > mul8su::m#0 -- vbuaa=_byte1_vwuz1 
     lda.z m+1
-    // >m = (>m)-(char)b
+    // BYTE1(m) = BYTE1(m)-(char)b
     // [153] mul8su::$6 = mul8su::$4 - mul8su::b#0 -- vbuaa=vbuaa_minus_vbuc1 
     sec
     sbc #b
-    // [154] mul8su::m#1 = mul8su::m#0 hi= mul8su::$6 -- vwuz1=vwuz1_sethi_vbuaa 
+    // [154] mul8su::m#1 = mul8su::m#0 byte1= mul8su::$6 -- vwuz1=vwuz1_setbyte1_vbuaa 
     sta.z m+1
     // [155] phi from mul8su::@2 mul8su::@3 to mul8su::@1 [phi:mul8su::@2/mul8su::@3->mul8su::@1]
     // [155] phi mul8su::m#2 = mul8su::m#1 [phi:mul8su::@2/mul8su::@3->mul8su::@1#0] -- register_copy 
@@ -6798,13 +6798,13 @@ divr16u: {
     // [179] divr16u::rem#0 = divr16u::rem#4 << 1 -- vwuz1=vwuz1_rol_1 
     asl.z rem
     rol.z rem+1
-    // >dividend
-    // [180] divr16u::$1 = > divr16u::dividend#2 -- vbuaa=_hi_vwuz1 
+    // BYTE1(dividend)
+    // [180] divr16u::$1 = > divr16u::dividend#2 -- vbuaa=_byte1_vwuz1 
     lda.z dividend+1
-    // >dividend & $80
+    // BYTE1(dividend) & $80
     // [181] divr16u::$2 = divr16u::$1 & $80 -- vbuaa=vbuaa_band_vbuc1 
     and #$80
-    // if( (>dividend & $80) != 0 )
+    // if( (BYTE1(dividend) & $80) != 0 )
     // [182] if(divr16u::$2==0) goto divr16u::@2 -- vbuaa_eq_0_then_la1 
     cmp #0
     beq __b2
@@ -6918,8 +6918,8 @@ mulu8_sel: {
     dey
     bne !-
   !e:
-    // >mul8u(v1, v2)<<select
-    // [205] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_hi_vwuz1 
+    // BYTE1(mul8u(v1, v2)<<select)
+    // [205] mulu8_sel::return#12 = > mulu8_sel::$1 -- vbuaa=_byte1_vwuz1 
     lda.z __1+1
     // mulu8_sel::@return
     // }