Cleaning the code a bit

src/main/fragment/cache/fragment-cache-wdc65c02.asm

@@ -2870,3 +2870,322 @@ sta {z1}
 lda {z1}+1
 adc {z2}+1
 sta {z1}+1
+//FRAGMENT _deref_pbuz1=vbuc1
+lda #{c1}
+ldy #0
+sta ({z1}),y
+//FRAGMENT pbuc1_derefidx_vbuaa=vbuc2
+tay
+lda #{c2}
+sta {c1},y
+//FRAGMENT pbuc1_derefidx_vbuyy=vbuc2
+lda #{c2}
+sta {c1},y
+//FRAGMENT vwuz1_eq_vwuc1_then_la1
+lda {z1}
+cmp #<{c1}
+bne !+
+lda {z1}+1
+cmp #>{c1}
+beq {la1}
+!:
+//FRAGMENT _deref_pbuz1=_deref_pbuz1_bor_vbuz2
+lda {z2}
+ldy #0
+ora ({z1}),y
+ldy #0
+sta ({z1}),y
+//FRAGMENT _deref_pbuz1=_deref_pbuz1_bor_vbuxx
+txa
+ldy #0
+ora ({z1}),y
+ldy #0
+sta ({z1}),y
+//FRAGMENT vduz1=vwuc1
+NO_SYNTHESIS
+//FRAGMENT vduz1=vwsc1
+NO_SYNTHESIS
+//FRAGMENT vbuz1=vbuz1_plus_vbuc1
+lda #{c1}
+clc
+adc {z1}
+sta {z1}
+//FRAGMENT vwuz1=_inc_vwuz2
+clc
+lda {z2}
+adc #1
+sta {z1}
+lda {z2}+1
+adc #0
+sta {z1}+1
+//FRAGMENT vwuz1=vwuz2_band_vbuc1
+lda #{c1}
+and {z2}
+sta {z1}
+lda #0
+sta {z1}+1
+//FRAGMENT pbuz1_neq_pbuc1_then_la1
+lda {z1}+1
+cmp #>{c1}
+bne {la1}
+lda {z1}
+cmp #<{c1}
+bne {la1}
+//FRAGMENT _deref_pbuc1=_deref_pbuz1
+ldy #0
+lda ({z1}),y
+sta {c1}
+//FRAGMENT vduz1=_deref_pduc1
+lda {c1}
+sta {z1}
+lda {c1}+1
+sta {z1}+1
+lda {c1}+2
+sta {z1}+2
+lda {c1}+3
+sta {z1}+3
+//FRAGMENT vwuz1=vwuc1_rol_vbuz2
+ldy {z2}
+lda #<{c1}
+sta {z1}
+lda #>{c1}+1
+sta {z1}+1
+cpy #0
+beq !e+
+!:
+asl {z1}
+rol {z1}+1
+dey
+bne !-
+!e:
+//FRAGMENT vduz1=vduz2_plus_vwuz3
+lda {z2}
+clc
+adc {z3}
+sta {z1}
+lda {z2}+1
+adc {z3}+1
+sta {z1}+1
+lda {z2}+2
+adc #0
+sta {z1}+2
+lda {z2}+3
+adc #0
+sta {z1}+3
+//FRAGMENT vduz1=vduz2_plus_vbuz3
+lda {z3}
+clc
+adc {z2}
+sta {z1}
+lda {z2}+1
+adc #0
+sta {z1}+1
+lda {z2}+2
+adc #0
+sta {z1}+2
+lda {z2}+3
+adc #0
+sta {z1}+3
+//FRAGMENT vbuxx=vbuxx_plus_vbuc1
+txa
+clc
+adc #{c1}
+tax
+//FRAGMENT vbuyy=vbuyy_plus_vbuc1
+tya
+clc
+adc #{c1}
+tay
+//FRAGMENT vbuaa_eq_vbuc1_then_la1
+cmp #{c1}
+beq {la1}
+//FRAGMENT vbuaa_neq_vbuc1_then_la1
+cmp #{c1}
+bne {la1}
+//FRAGMENT vwuz1=vwuc1_rol_vbuaa
+tay
+lda #<{c1}
+sta {z1}
+lda #>{c1}+1
+sta {z1}+1
+cpy #0
+beq !e+
+!:
+asl {z1}
+rol {z1}+1
+dey
+bne !-
+!e:
+//FRAGMENT vwuz1=vwuc1_rol_vbuxx
+lda #<{c1}
+sta {z1}
+lda #>{c1}+1
+sta {z1}+1
+cpx #0
+beq !e+
+!:
+asl {z1}
+rol {z1}+1
+dex
+bne !-
+!e:
+//FRAGMENT vwuz1=vwuc1_rol_vbuyy
+lda #<{c1}
+sta {z1}
+lda #>{c1}+1
+sta {z1}+1
+cpy #0
+beq !e+
+!:
+asl {z1}
+rol {z1}+1
+dey
+bne !-
+!e:
+//FRAGMENT vbuz1=vbuaa_bor_vbuyy
+sty $ff
+ora $ff
+sta {z1}
+//FRAGMENT vbuaa=vbuaa_bor_vbuyy
+sty $ff
+ora $ff
+//FRAGMENT vbuxx=vbuaa_bor_vbuyy
+sty $ff
+ora $ff
+tax
+//FRAGMENT vbuyy=vbuaa_bor_vbuyy
+sty $ff
+ora $ff
+tay
+//FRAGMENT vbuyy=vbuxx_bor_vbuz1
+txa
+ora {z1}
+tay
+//FRAGMENT vbuyy=vbuyy_bor_vbuz1
+tya
+ora {z1}
+tay
+//FRAGMENT vwuz1=_word_vbuyy
+tya
+sta {z1}
+lda #0
+sta {z1}+1
+//FRAGMENT vwuz1=vwuz2_rol_vbuxx
+lda {z2}
+sta {z1}
+lda {z2}+1
+sta {z1}+1
+cpx #0
+beq !e+
+!:
+asl {z1}
+rol {z1}+1
+dex
+bne !-
+!e:
+//FRAGMENT vwuz1=vwuz2_rol_vbuyy
+lda {z2}
+sta {z1}
+lda {z2}+1
+sta {z1}+1
+cpy #0
+beq !e+
+!:
+asl {z1}
+rol {z1}+1
+dey
+bne !-
+!e:
+//FRAGMENT vduz1=vduz2_plus_vbuaa
+clc
+adc {z2}
+sta {z1}
+lda {z2}+1
+adc #0
+sta {z1}+1
+lda {z2}+2
+adc #0
+sta {z1}+2
+lda {z2}+3
+adc #0
+sta {z1}+3
+//FRAGMENT vduz1=vduz2_plus_vbuxx
+txa
+clc
+adc {z2}
+sta {z1}
+lda {z2}+1
+adc #0
+sta {z1}+1
+lda {z2}+2
+adc #0
+sta {z1}+2
+lda {z2}+3
+adc #0
+sta {z1}+3
+//FRAGMENT vduz1=vduz2_plus_vbuyy
+tya
+clc
+adc {z2}
+sta {z1}
+lda {z2}+1
+adc #0
+sta {z1}+1
+lda {z2}+2
+adc #0
+sta {z1}+2
+lda {z2}+3
+adc #0
+sta {z1}+3
+//FRAGMENT vbuz1=vbuaa_bor_vbuc1
+ora #{c1}
+sta {z1}
+//FRAGMENT vbuz1=vbuyy_bor_vbuc1
+tya
+ora #{c1}
+sta {z1}
+//FRAGMENT vbuaa=vbuyy_bor_vbuc1
+tya
+ora #{c1}
+//FRAGMENT vbuxx=vbuaa_bor_vbuc1
+ora #{c1}
+tax
+//FRAGMENT vbuxx=vbuyy_bor_vbuc1
+tya
+ora #{c1}
+tax
+//FRAGMENT vbuyy=vbuaa_bor_vbuc1
+ora #{c1}
+tay
+//FRAGMENT vbuaa=_inc_vbuaa
+inc
+//FRAGMENT vbuyy_lt_vbuz1_then_la1
+cpy {z1}
+bcc {la1}
+//FRAGMENT vbuyy=_deref_pbuc1
+ldy {c1}
+//FRAGMENT vbuyy_eq_vbuc1_then_la1
+cpy #{c1}
+beq {la1}
+//FRAGMENT vwuz1=vwuz1_band_vbuc1
+lda #{c1}
+and {z1}
+sta {z1}
+lda #0
+sta {z1}+1
+//FRAGMENT vduz1=vduz1_plus_vbuaa
+clc
+adc {z1}
+sta {z1}
+lda {z1}+1
+adc #0
+sta {z1}+1
+lda {z1}+2
+adc #0
+sta {z1}+2
+lda {z1}+3
+adc #0
+sta {z1}+3
+//FRAGMENT vbuz1=vbuaa_bor_vbuz1
+ora {z1}
+sta {z1}

src/test/kc/examples/cx16/dword.c

@@ -1,15 +0,0 @@
-
-#include <conio.h>
-#include <printf.h>
-
-dword test_address[2] = {0,0};
-
-void method(char layer, dword dw1, dword dw2) {
-    test_address[layer] = dw1;
-    printf("test = %x\n",test_address[layer]);
-}
-
-void main() {
-    method(1,0x0002,0x12000);
-    method(2,0x0001,0x12000);
-}

src/test/kc/examples/cx16/dword_low_hi.c

@@ -1,12 +0,0 @@
-
-
-#include <printf.h>
-
-void main() {
-dword value = 0xff446677;
-clrscr();
-printf("77 = %x\n", <(<(value)) );
-printf("66 = %x\n", >(<(value)) );
-printf("44 = %x\n", <(>(value)) );
-printf("ff = %x\n", >(>(value)) );
-}

src/test/kc/examples/cx16/dword_word.c

@@ -1,13 +0,0 @@
-
-
-#include <printf.h>
-
-void main() {
-word value = 0xf801;
-dword dw_value[2] = {0,0};
-for(word t:0..1) {
-    dw_value[t] = 0xf800;
-}
-clrscr();
-printf("f801 = %x\n", dw_value[1] );
-}

src/test/kc/examples/cx16/tilemap_1bpp_8_x_8_16_color.c

@@ -3,12 +3,6 @@
 
 // Author: Sven Van de Velde
 
-// The default layer of the CX16 is layer 1, but the tiles are written on layer 0.
-// The CX16 starts in tile map mode, 1BPP in 16 color mode, and uses 8x8 tiles.
-
-// An explanation is given how this mode is organized, and how the tiles display and coloring works.
-// Pälette offsets are explained also.
-
 #include <veralib.h>
 #include <printf.h>
 

src/test/kc/examples/cx16/tilemap_1bpp_8_x_8_256_color.c

@@ -3,12 +3,6 @@
 
 // Author: Sven Van de Velde
 
-// The default layer of the CX16 is layer 1, but the tiles are written on layer 0.
-// The CX16 starts in tile map mode, 1BPP in 16 color mode, and uses 8x8 tiles.
-
-// An explanation is given how this mode is organized, and how the tiles display and coloring works.
-// Pälette offsets are explained also.
-
 #include <veralib.h>
 #include <printf.h>
 

src/test/kc/examples/cx16/tilemap_2bpp_16_x_16.c

@@ -3,12 +3,6 @@
 
 // Author: Sven Van de Velde
 
-// The default layer of the CX16 is layer 1, but the tiles are written on layer 0.
-// The CX16 starts in tile map mode, 2BPP in 4 color mode, and uses 16x16 tiles.
-
-// An explanation is given how this mode is organized, and how the tiles display and coloring works.
-// Pälette offsets are explained also.
-
 #include <veralib.h>
 #include <printf.h>
 

src/test/kc/examples/cx16/tilemap_2bpp_8_x_8.c

@@ -3,12 +3,6 @@
 
 // Author: Sven Van de Velde
 
-// The default layer of the CX16 is layer 1, but the tiles are written on layer 0.
-// The CX16 starts in tile map mode, 2BPP in 4 color mode, and uses 8x8 tiles.
-
-// An explanation is given how this mode is organized, and how the tiles display and coloring works.
-// Pälette offsets are explained also.
-
 #include <veralib.h>
 #include <printf.h>
 

src/test/kc/examples/cx16/tilemap_4bpp_16_x_16.c

@@ -3,12 +3,6 @@
 
 // Author: Sven Van de Velde
 
-// The default layer of the CX16 is layer 1, but the tiles are written on layer 0.
-// The CX16 starts in tile map mode, 2BPP in 4 color mode, and uses 16x16 tiles.
-
-// An explanation is given how this mode is organized, and how the tiles display and coloring works.
-// Pälette offsets are explained also.
-
 #include <veralib.h>
 #include <printf.h>
 

src/test/kc/examples/cx16/tilemap_4bpp_8_x_8.c

@@ -2,12 +2,7 @@
 // Demonstrates the usage of the VERA tile map modes and layering.
 
 // Author: Sven Van de Velde
-
+µ
-// The default layer of the CX16 is layer 1, but the tiles are written on layer 0.
-
-// An explanation is given how this mode is organized, and how the tiles display and coloring works.
-// Pälette offsets are explained also.
-
 #include <veralib.h>
 #include <printf.h>
 

src/test/kc/examples/cx16/tilemap_8bpp_16_x_16.c

@@ -3,11 +3,6 @@
 
 // Author: Sven Van de Velde
 
-// The default layer of the CX16 is layer 1, but the tiles are written on layer 0.
-
-// An explanation is given how this mode is organized, and how the tiles display and coloring works.
-// Pälette offsets are explained also.
-
 #include <conio.h>
 #include <printf.h>
 
@@ -45,20 +40,7 @@ void main() {
     // We also will need to realign for layer 1 the map base from 0x00000 to 0x10000.
     // This is now all easily done with a few statements in the new kickc vera lib ...
 
-    // Copy block of memory (from VRAM to VRAM)
-    // Copies the values from the location pointed by src to the location pointed by dest.
-    // The method uses the VERA access ports 0 and 1 to copy data from and to in VRAM.
-    // - src_bank:  64K VRAM bank number to copy from (0/1).
-    // - src: pointer to the location to copy from. Note that the address is a 16 bit value!
-    // - src_increment: the increment indicator, VERA needs this because addressing increment is automated by VERA at each access.
-    // - dest_bank:  64K VRAM bank number to copy to (0/1).
-    // - dest: pointer to the location to copy to. Note that the address is a 16 bit value!
-    // - dest_increment: the increment indicator, VERA needs this because addressing increment is automated by VERA at each access.
-    // - num: The number of bytes to copy
-    // void memcpy_in_vram(char dest_bank, void *dest, char dest_increment, char src_bank, void *src, char src_increment, unsigned int num );
     memcpy_in_vram(1, 0xF000, VERA_INC_1, 0, 0xF800, VERA_INC_1, 256*8); // We copy the 128 character set of 8 bytes each.
-
-
     vera_layer_mode_tile(1, 0x10000, 0x1F000, 128, 64, 8, 8, 1);
 
     screenlayer(1);

src/test/kc/examples/cx16/tilemap_8bpp_8_x_8.c

@@ -3,11 +3,6 @@
 
 // Author: Sven Van de Velde
 
-// The default layer of the CX16 is layer 1, but the tiles are written on layer 0.
-
-// An explanation is given how this mode is organized, and how the tiles display and coloring works.
-// Pälette offsets are explained also.
-
 #include <veralib.h>
 #include <printf.h>