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mirror of https://github.com/irmen/ksim65.git synced 2025-04-05 07:37:30 +00:00
This commit is contained in:
Irmen de Jong 2020-01-27 23:44:56 +01:00
parent 0a9e8b293d
commit 2410ca48f9
7 changed files with 54 additions and 51 deletions

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@ -316,40 +316,39 @@ class Cia(val number: Int, startAddress: Address, endAddress: Address, val cpu:
) hostKeyPresses.clear()
// try to remap the keys a bit so a modern PC keyboard maps better to the keys of the C64
when {
event.keyChar == '@' -> {
when (event.keyChar) {
'@' -> {
unregister(KeyEvent.VK_SHIFT)
register(event.id, HostKeyPress(KeyEvent.VK_AT))
}
event.keyChar == '^' -> {
'^' -> {
unregister(KeyEvent.VK_SHIFT)
register(event.id, HostKeyPress(KeyEvent.VK_CIRCUMFLEX))
}
event.keyChar == '*' -> {
'*' -> {
unregister(KeyEvent.VK_SHIFT)
register(event.id, HostKeyPress(KeyEvent.VK_ASTERISK))
}
event.keyChar == '+' -> {
'+' -> {
unregister(KeyEvent.VK_SHIFT)
register(event.id, HostKeyPress(KeyEvent.VK_PLUS))
}
event.keyChar == ':' -> {
':' -> {
unregister(KeyEvent.VK_SHIFT)
register(event.id, HostKeyPress(KeyEvent.VK_COLON))
}
event.keyChar == '~' -> {
'~' -> {
unregister(KeyEvent.VK_SHIFT)
register(event.id, HostKeyPress(KeyEvent.VK_DEAD_TILDE))
}
event.keyChar == '&' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_6))
event.keyChar == '(' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_8))
event.keyChar == ')' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_9))
event.keyChar == '[' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_COLON))
event.keyChar == ']' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_SEMICOLON))
event.keyChar == '"' -> register(event.id, HostKeyPress(KeyEvent.VK_2))
event.keyChar == '\'' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_7))
else ->
// F2 = shift+F1
'&' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_6))
'(' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_8))
')' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_9))
'[' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_COLON))
']' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_SEMICOLON))
'"' -> register(event.id, HostKeyPress(KeyEvent.VK_2))
'\'' -> register(event.id, shift, HostKeyPress(KeyEvent.VK_7))
else -> // F2 = shift+F1
// F4 = shift+F3
// F6 = shift+F5
// F8 = shift+F7

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@ -82,7 +82,7 @@ internal class Screen(private val chargenData: ByteArray, val ram: MemoryCompone
renderBorder()
}
// scale and draw the image to the window, and simulate a slight scanline effect
// scale and draw the image to the window, and simulate a slight scan-line effect
windowG2d.setRenderingHint(RenderingHints.KEY_INTERPOLATION, RenderingHints.VALUE_INTERPOLATION_BILINEAR)
windowG2d.drawImage(fullscreenImage, 0, 0, (fullscreenImage.width*ScreenDefs.PIXEL_SCALING).toInt(),
(fullscreenImage.height*ScreenDefs.ASPECT_RATIO*ScreenDefs.PIXEL_SCALING).toInt(), null)
@ -238,26 +238,37 @@ internal class Screen(private val chargenData: ByteArray, val ram: MemoryCompone
// If the address is different, the vic takes charset data from RAM instead.
// TODO: currently custom charsets taken from RAM aren't supported
val shifted = charsetAddr and 0x0800 != 0
var cached = coloredCharacterImageCache[Triple(char, color, shifted)]
if (cached == null) {
cached = if (shifted) shiftedCharacters[char] else normalCharacters[char]
val colored = fullscreenG2d.deviceConfiguration.createCompatibleImage(8, 8, BufferedImage.BITMASK)
val sourceRaster = cached.raster
val coloredRaster = colored.raster
val pixelArray = IntArray(4)
val charImage = getCharImage(char, color, shifted)
fullscreenG2d.drawImage(charImage, x*8+ScreenDefs.BORDER_SIZE, y*8+ScreenDefs.BORDER_SIZE, null)
}
private fun getCharImage(char: Int, color: Int, shifted: Boolean): BufferedImage {
val key = Triple(char, color, shifted)
fun makeCachedImage(): BufferedImage {
val monoImg = if (shifted) shiftedCharacters[char] else normalCharacters[char]
val coloredImg = fullscreenG2d.deviceConfiguration.createCompatibleImage(8, 8, BufferedImage.BITMASK)
val srcPixel = IntArray(4)
val rgbs = IntArray(4)
val javaColor = ScreenDefs.colorPalette[color]
val coloredPixel = listOf(javaColor.red, javaColor.green, javaColor.blue, javaColor.alpha).toIntArray()
rgbs[0] = javaColor.red
rgbs[1] = javaColor.green
rgbs[2] = javaColor.blue
rgbs[3] = javaColor.alpha
val sourceRaster = monoImg.raster
val coloredRaster = coloredImg.raster
for (pixelY in 0..7) {
for (pixelX in 0..7) {
val source = sourceRaster.getPixel(pixelX, pixelY, pixelArray)
val source = sourceRaster.getPixel(pixelX, pixelY, srcPixel)
if (source[0] != 0) {
coloredRaster.setPixel(pixelX, pixelY, coloredPixel)
coloredRaster.setPixel(pixelX, pixelY, rgbs)
}
}
}
coloredCharacterImageCache[Triple(char, color, shifted)] = colored
cached = colored
coloredCharacterImageCache[key] = coloredImg
return coloredImg
}
fullscreenG2d.drawImage(cached, x*8+ScreenDefs.BORDER_SIZE, y*8+ScreenDefs.BORDER_SIZE, null)
return coloredCharacterImageCache[key] ?: makeCachedImage()
}
}

View File

@ -252,7 +252,7 @@ class C64Machine(title: String) : IVirtualMachine {
}
}
fun main(args: Array<String>) {
fun main() {
val machine = C64Machine("virtual Commodore-64 - using KSim65 v${Version.version}")
machine.start()
}

View File

@ -67,7 +67,7 @@ class EhBasicMachine(title: String) {
}
}
fun main(args: Array<String>) {
fun main() {
val machine = EhBasicMachine("KSim65 demo virtual machine - using ksim65 v${Version.version}")
machine.start()
}

View File

@ -93,7 +93,7 @@ class VirtualMachine(title: String) : IVirtualMachine {
}
}
fun main(args: Array<String>) {
fun main() {
val machine = VirtualMachine("KSim65 demo virtual machine - using ksim65 v${Version.version}")
machine.start()
}

View File

@ -637,7 +637,7 @@ class Cpu65C02 : Cpu6502() {
pushStack(regP)
regP.I = true // interrupts are now disabled
regP.D = false // this is different from NMOS 6502
regPC = readWord(if (nmi) Cpu6502.NMI_vector else Cpu6502.IRQ_vector)
regPC = readWord(if (nmi) NMI_vector else IRQ_vector)
pendingInterrupt = null
}

View File

@ -108,21 +108,20 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
val address = parseNumber(parts[0])
val mnemonic = parts[1].toLowerCase()
when {
parts.size == 2 -> {
when (parts.size) {
2 -> {
// implied or acc
var instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Imp)]
if (instruction == null) instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Acc)]
if (instruction == null) return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
bus.write(address, instruction.toShort())
}
parts.size == 3 -> {
3 -> {
val arg = parts[2]
when {
arg.startsWith('#') -> {
// immediate
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Imm)] ?: return IVirtualMachine.MonitorCmdResult(
"?invalid instruction", command, false)
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Imm)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
bus.write(address, instruction.toShort())
bus.write(address+1, parseNumber(arg.substring(1), true).toShort())
}
@ -133,8 +132,7 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
} catch (x: NumberFormatException) {
return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
}
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.IzX)] ?: return IVirtualMachine.MonitorCmdResult(
"?invalid instruction", command, false)
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.IzX)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
bus.write(address, instruction.toShort())
bus.write(address+1, indAddress.toShort())
}
@ -145,8 +143,7 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
} catch (x: NumberFormatException) {
return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
}
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.IzY)] ?: return IVirtualMachine.MonitorCmdResult(
"?invalid instruction", command, false)
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.IzY)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
bus.write(address, instruction.toShort())
bus.write(address+1, indAddress.toShort())
}
@ -164,8 +161,7 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
bus.write(address+1, indAddress.toShort())
} else {
val instruction =
instructions[Pair(mnemonic, Cpu6502.AddrMode.AbsX)] ?: return IVirtualMachine.MonitorCmdResult(
"?invalid instruction", command, false)
instructions[Pair(mnemonic, Cpu6502.AddrMode.AbsX)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
bus.write(address, instruction.toShort())
bus.write(address+1, (indAddress and 255).toShort())
bus.write(address+2, (indAddress ushr 8).toShort())
@ -185,8 +181,7 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
bus.write(address+1, indAddress.toShort())
} else {
val instruction =
instructions[Pair(mnemonic, Cpu6502.AddrMode.AbsY)] ?: return IVirtualMachine.MonitorCmdResult(
"?invalid instruction", command, false)
instructions[Pair(mnemonic, Cpu6502.AddrMode.AbsY)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
bus.write(address, instruction.toShort())
bus.write(address+1, (indAddress and 255).toShort())
bus.write(address+2, (indAddress ushr 8).toShort())
@ -199,8 +194,7 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
} catch (x: NumberFormatException) {
return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
}
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Ind)] ?: return IVirtualMachine.MonitorCmdResult(
"?invalid instruction", command, false)
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Ind)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
bus.write(address, instruction.toShort())
bus.write(address+1, (indAddress and 255).toShort())
bus.write(address+2, (indAddress ushr 8).toShort())
@ -230,8 +224,7 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
bus.write(address+1, absAddress.toShort())
} else {
val absInstr =
instructions[Pair(mnemonic, Cpu6502.AddrMode.Abs)] ?: return IVirtualMachine.MonitorCmdResult(
"?invalid instruction", command, false)
instructions[Pair(mnemonic, Cpu6502.AddrMode.Abs)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
bus.write(address, absInstr.toShort())
bus.write(address+1, (absAddress and 255).toShort())
bus.write(address+2, (absAddress ushr 8).toShort())