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ksim65
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This commit is contained in:
Irmen de Jong 2019-09-11 02:17:59 +02:00
commit 764710ea12
316 changed files with 50914 additions and 0 deletions
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.gitignore vendored Normal file
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# Ignore Gradle project-specific cache directory
.gradle
# Ignore Gradle build output directory
build/
.idea/workspace.xml
.idea/misc.xml
.idea/discord.xml

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<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="masterDetails">
<states>
<state key="ProjectJDKs.UI">
<settings>
<last-edited>Python 3.7 (py3)</last-edited>
<splitter-proportions>
<option name="proportions">
<list>
<option value="0.2" />
</list>
</option>
</splitter-proportions>
</settings>
</state>
</states>
</component>
</project>

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# Project exclude paths
/.

13
.idea/codeStyles/Project.xml Normal file
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<component name="ProjectCodeStyleConfiguration">
<code_scheme name="Project" version="173">
<JetCodeStyleSettings>
<option name="CODE_STYLE_DEFAULTS" value="KOTLIN_OFFICIAL" />
</JetCodeStyleSettings>
<MarkdownNavigatorCodeStyleSettings>
<option name="RIGHT_MARGIN" value="72" />
</MarkdownNavigatorCodeStyleSettings>
<codeStyleSettings language="kotlin">
<option name="CODE_STYLE_DEFAULTS" value="KOTLIN_OFFICIAL" />
</codeStyleSettings>
</code_scheme>
</component>

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.idea/codeStyles/codeStyleConfig.xml Normal file
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<component name="ProjectCodeStyleConfiguration">
<state>
<option name="USE_PER_PROJECT_SETTINGS" value="true" />
</state>
</component>

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.idea/gradle.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="GradleMigrationSettings" migrationVersion="1" />
<component name="GradleSettings">
<option name="linkedExternalProjectsSettings">
<GradleProjectSettings>
<option name="delegatedBuild" value="true" />
<option name="testRunner" value="PLATFORM" />
<option name="distributionType" value="DEFAULT_WRAPPED" />
<option name="externalProjectPath" value="$PROJECT_DIR$" />
<option name="gradleHome" value="/usr/share/java/gradle" />
<option name="modules">
<set>
<option value="$PROJECT_DIR$" />
</set>
</option>
<option name="useAutoImport" value="true" />
<option name="useQualifiedModuleNames" value="true" />
</GradleProjectSettings>
</option>
</component>
</project>

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<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="VcsDirectoryMappings">
<mapping directory="$PROJECT_DIR$" vcs="Git" />
</component>
</project>

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build.gradle.kts Normal file
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import org.jetbrains.dokka.gradle.DokkaTask
import org.jetbrains.kotlin.gradle.tasks.KotlinCompile
plugins {
// Apply the Kotlin JVM plugin to add support for Kotlin on the JVM.
id("org.jetbrains.kotlin.jvm").version("1.3.50")
id("com.gradle.build-scan").version("2.4.2")
id("org.jetbrains.dokka").version("0.9.18")
}
repositories {
// Use jcenter for resolving dependencies.
// You can declare any Maven/Ivy/file repository here.
jcenter()
}
dependencies {
// Use the Kotlin JDK 8 standard library.
implementation("org.jetbrains.kotlin:kotlin-stdlib-jdk8")
// Use the Kotlin test library.
testImplementation("org.jetbrains.kotlin:kotlin-test")
// Use the Kotlin JUnit5 integration.
testImplementation("org.jetbrains.kotlin:kotlin-test-junit5")
testImplementation("org.junit.jupiter:junit-jupiter-api:5.1.0")
testRuntimeOnly("org.junit.jupiter:junit-jupiter-engine:5.1.0")
}
//buildScan {
// termsOfServiceUrl = "https://gradle.com/terms-of-service"
// termsOfServiceAgree="yes"
// publishOnFailure()
//}
tasks.named<Test>("test") {
// Enable JUnit 5 (Gradle 4.6+).
useJUnitPlatform()
// Always run tests, even when nothing changed.
dependsOn("cleanTest")
// Show test results.
testLogging.events("failed")
// parallel tests.
systemProperties["junit.jupiter.execution.parallel.enabled"] = true
systemProperties["junit.jupiter.execution.parallel.mode.default"] = "concurrent"
maxParallelForks = Runtime.getRuntime().availableProcessors() / 2
}
tasks.withType<KotlinCompile>().all {
kotlinOptions {
jvmTarget = "1.8"
}
}
tasks.named<DokkaTask>("dokka") {
outputFormat = "html"
outputDirectory = "$buildDir/kdoc"
skipEmptyPackages = true
}

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gradle.properties Normal file
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kotlin.code.style=official
kotlinVersion=1.3.50
org.gradle.caching=true
org.gradle.console=rich
org.gradle.parallel=true
org.gradle.jvmargs=-Xmx2500M
org.gradle.daemon=true

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gradle/wrapper/gradle-wrapper.jar vendored Normal file
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gradle/wrapper/gradle-wrapper.properties vendored Normal file
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distributionBase=GRADLE_USER_HOME
distributionPath=wrapper/dists
distributionUrl=https://services.gradle.org/distributions-snapshots/gradle-5.5.1-20190713230057+0000-bin.zip
zipStoreBase=GRADLE_USER_HOME
zipStorePath=wrapper/dists

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gradlew vendored Executable file
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#!/usr/bin/env sh
#
# Copyright 2015 the original author or authors.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
##############################################################################
##
## Gradle start up script for UN*X
##
##############################################################################
# Attempt to set APP_HOME
# Resolve links: $0 may be a link
PRG="$0"
# Need this for relative symlinks.
while [ -h "$PRG" ] ; do
ls=`ls -ld "$PRG"`
link=`expr "$ls" : '.*-> \(.*\)$'`
if expr "$link" : '/.*' > /dev/null; then
PRG="$link"
else
PRG=`dirname "$PRG"`"/$link"
fi
done
SAVED="`pwd`"
cd "`dirname \"$PRG\"`/" >/dev/null
APP_HOME="`pwd -P`"
cd "$SAVED" >/dev/null
APP_NAME="Gradle"
APP_BASE_NAME=`basename "$0"`
# Add default JVM options here. You can also use JAVA_OPTS and GRADLE_OPTS to pass JVM options to this script.
DEFAULT_JVM_OPTS='"-Xmx64m" "-Xms64m"'
# Use the maximum available, or set MAX_FD != -1 to use that value.
MAX_FD="maximum"
warn () {
echo "$*"
}
die () {
echo
echo "$*"
echo
exit 1
}
# OS specific support (must be 'true' or 'false').
cygwin=false
msys=false
darwin=false
nonstop=false
case "`uname`" in
CYGWIN* )
cygwin=true
;;
Darwin* )
darwin=true
;;
MINGW* )
msys=true
;;
NONSTOP* )
nonstop=true
;;
esac
CLASSPATH=$APP_HOME/gradle/wrapper/gradle-wrapper.jar
# Determine the Java command to use to start the JVM.
if [ -n "$JAVA_HOME" ] ; then
if [ -x "$JAVA_HOME/jre/sh/java" ] ; then
# IBM's JDK on AIX uses strange locations for the executables
JAVACMD="$JAVA_HOME/jre/sh/java"
else
JAVACMD="$JAVA_HOME/bin/java"
fi
if [ ! -x "$JAVACMD" ] ; then
die "ERROR: JAVA_HOME is set to an invalid directory: $JAVA_HOME
Please set the JAVA_HOME variable in your environment to match the
location of your Java installation."
fi
else
JAVACMD="java"
which java >/dev/null 2>&1 || die "ERROR: JAVA_HOME is not set and no 'java' command could be found in your PATH.
Please set the JAVA_HOME variable in your environment to match the
location of your Java installation."
fi
# Increase the maximum file descriptors if we can.
if [ "$cygwin" = "false" -a "$darwin" = "false" -a "$nonstop" = "false" ] ; then
MAX_FD_LIMIT=`ulimit -H -n`
if [ $? -eq 0 ] ; then
if [ "$MAX_FD" = "maximum" -o "$MAX_FD" = "max" ] ; then
MAX_FD="$MAX_FD_LIMIT"
fi
ulimit -n $MAX_FD
if [ $? -ne 0 ] ; then
warn "Could not set maximum file descriptor limit: $MAX_FD"
fi
else
warn "Could not query maximum file descriptor limit: $MAX_FD_LIMIT"
fi
fi
# For Darwin, add options to specify how the application appears in the dock
if $darwin; then
GRADLE_OPTS="$GRADLE_OPTS \"-Xdock:name=$APP_NAME\" \"-Xdock:icon=$APP_HOME/media/gradle.icns\""
fi
# For Cygwin, switch paths to Windows format before running java
if $cygwin ; then
APP_HOME=`cygpath --path --mixed "$APP_HOME"`
CLASSPATH=`cygpath --path --mixed "$CLASSPATH"`
JAVACMD=`cygpath --unix "$JAVACMD"`
# We build the pattern for arguments to be converted via cygpath
ROOTDIRSRAW=`find -L / -maxdepth 1 -mindepth 1 -type d 2>/dev/null`
SEP=""
for dir in $ROOTDIRSRAW ; do
ROOTDIRS="$ROOTDIRS$SEP$dir"
SEP="|"
done
OURCYGPATTERN="(^($ROOTDIRS))"
# Add a user-defined pattern to the cygpath arguments
if [ "$GRADLE_CYGPATTERN" != "" ] ; then
OURCYGPATTERN="$OURCYGPATTERN|($GRADLE_CYGPATTERN)"
fi
# Now convert the arguments - kludge to limit ourselves to /bin/sh
i=0
for arg in "$@" ; do
CHECK=`echo "$arg"|egrep -c "$OURCYGPATTERN" -`
CHECK2=`echo "$arg"|egrep -c "^-"` ### Determine if an option
if [ $CHECK -ne 0 ] && [ $CHECK2 -eq 0 ] ; then ### Added a condition
eval `echo args$i`=`cygpath --path --ignore --mixed "$arg"`
else
eval `echo args$i`="\"$arg\""
fi
i=$((i+1))
done
case $i in
(0) set -- ;;
(1) set -- "$args0" ;;
(2) set -- "$args0" "$args1" ;;
(3) set -- "$args0" "$args1" "$args2" ;;
(4) set -- "$args0" "$args1" "$args2" "$args3" ;;
(5) set -- "$args0" "$args1" "$args2" "$args3" "$args4" ;;
(6) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" ;;
(7) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" ;;
(8) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" "$args7" ;;
(9) set -- "$args0" "$args1" "$args2" "$args3" "$args4" "$args5" "$args6" "$args7" "$args8" ;;
esac
fi
# Escape application args
save () {
for i do printf %s\\n "$i" | sed "s/'/'\\\\''/g;1s/^/'/;\$s/\$/' \\\\/" ; done
echo " "
}
APP_ARGS=$(save "$@")
# Collect all arguments for the java command, following the shell quoting and substitution rules
eval set -- $DEFAULT_JVM_OPTS $JAVA_OPTS $GRADLE_OPTS "\"-Dorg.gradle.appname=$APP_BASE_NAME\"" -classpath "\"$CLASSPATH\"" org.gradle.wrapper.GradleWrapperMain "$APP_ARGS"
# by default we should be in the correct project dir, but when run from Finder on Mac, the cwd is wrong
if [ "$(uname)" = "Darwin" ] && [ "$HOME" = "$PWD" ]; then
cd "$(dirname "$0")"
fi
exec "$JAVACMD" "$@"

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gradlew.bat vendored Normal file
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@rem
@rem Copyright 2015 the original author or authors.
@rem
@rem Licensed under the Apache License, Version 2.0 (the "License");
@rem you may not use this file except in compliance with the License.
@rem You may obtain a copy of the License at
@rem
@rem https://www.apache.org/licenses/LICENSE-2.0
@rem
@rem Unless required by applicable law or agreed to in writing, software
@rem distributed under the License is distributed on an "AS IS" BASIS,
@rem WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@rem See the License for the specific language governing permissions and
@rem limitations under the License.
@rem
@if "%DEBUG%" == "" @echo off
@rem ##########################################################################
@rem
@rem Gradle startup script for Windows
@rem
@rem ##########################################################################
@rem Set local scope for the variables with windows NT shell
if "%OS%"=="Windows_NT" setlocal
set DIRNAME=%~dp0
if "%DIRNAME%" == "" set DIRNAME=.
set APP_BASE_NAME=%~n0
set APP_HOME=%DIRNAME%
@rem Add default JVM options here. You can also use JAVA_OPTS and GRADLE_OPTS to pass JVM options to this script.
set DEFAULT_JVM_OPTS="-Xmx64m" "-Xms64m"
@rem Find java.exe
if defined JAVA_HOME goto findJavaFromJavaHome
set JAVA_EXE=java.exe
%JAVA_EXE% -version >NUL 2>&1
if "%ERRORLEVEL%" == "0" goto init
echo.
echo ERROR: JAVA_HOME is not set and no 'java' command could be found in your PATH.
echo.
echo Please set the JAVA_HOME variable in your environment to match the
echo location of your Java installation.
goto fail
:findJavaFromJavaHome
set JAVA_HOME=%JAVA_HOME:"=%
set JAVA_EXE=%JAVA_HOME%/bin/java.exe
if exist "%JAVA_EXE%" goto init
echo.
echo ERROR: JAVA_HOME is set to an invalid directory: %JAVA_HOME%
echo.
echo Please set the JAVA_HOME variable in your environment to match the
echo location of your Java installation.
goto fail
:init
@rem Get command-line arguments, handling Windows variants
if not "%OS%" == "Windows_NT" goto win9xME_args
:win9xME_args
@rem Slurp the command line arguments.
set CMD_LINE_ARGS=
set _SKIP=2
:win9xME_args_slurp
if "x%~1" == "x" goto execute
set CMD_LINE_ARGS=%*
:execute
@rem Setup the command line
set CLASSPATH=%APP_HOME%\gradle\wrapper\gradle-wrapper.jar
@rem Execute Gradle
"%JAVA_EXE%" %DEFAULT_JVM_OPTS% %JAVA_OPTS% %GRADLE_OPTS% "-Dorg.gradle.appname=%APP_BASE_NAME%" -classpath "%CLASSPATH%" org.gradle.wrapper.GradleWrapperMain %CMD_LINE_ARGS%
:end
@rem End local scope for the variables with windows NT shell
if "%ERRORLEVEL%"=="0" goto mainEnd
:fail
rem Set variable GRADLE_EXIT_CONSOLE if you need the _script_ return code instead of
rem the _cmd.exe /c_ return code!
if not "" == "%GRADLE_EXIT_CONSOLE%" exit 1
exit /b 1
:mainEnd
if "%OS%"=="Windows_NT" endlocal
:omega

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settings.gradle.kts Normal file
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/*
* This file was generated by the Gradle 'init' task.
*
* The settings file is used to specify which projects to include in your build.
*
* Detailed information about configuring a multi-project build in Gradle can be found
* in the user manual at https://docs.gradle.org/5.5.1-20190724234647+0000/userguide/multi_project_builds.html
*/
rootProject.name = "ksim65"

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src/main/kotlin/net/razorvine/ksim65/Petscii.kt Normal file
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src/main/kotlin/net/razorvine/ksim65/Sim65Main.kt Normal file
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package net.razorvine.ksim65
import net.razorvine.ksim65.components.*
import net.razorvine.ksim65.components.Cpu6502.Companion.IRQ_vector
import net.razorvine.ksim65.components.Cpu6502.Companion.NMI_vector
import net.razorvine.ksim65.components.Cpu6502.Companion.RESET_vector
fun main(args: Array<String>) {
printSoftwareHeader()
startSimulator(args)
}
internal fun printSoftwareHeader() {
val buildVersion = object {}.javaClass.getResource("/version.txt").readText().trim()
println("\nSim65 6502 cpu simulator v$buildVersion by Irmen de Jong (irmen@razorvine.net)")
println("This software is licensed under the GNU GPL 3.0, see https://www.gnu.org/licenses/gpl.html\n")
}
private fun startSimulator(args: Array<String>) {
// create a computer system.
// note that the order in which components are added to the bus, is important:
// it determines the priority of reads and writes.
val cpu = Cpu6502(true)
val ram = Ram(0, 0xffff)
ram[RESET_vector] = 0x00
ram[RESET_vector + 1] = 0x10
ram[IRQ_vector] = 0x00
ram[IRQ_vector + 1] = 0x20
ram[NMI_vector] = 0x00
ram[NMI_vector + 1] = 0x30
// // read the RTC and write the date+time to $2000
// for(b in listOf(0xa0, 0x00, 0xb9, 0x00, 0xd1, 0x99, 0x00, 0x20, 0xc8, 0xc0, 0x09, 0xd0, 0xf5, 0x00).withIndex()) {
// ram[0x1000+b.index] = b.value.toShort()
// }
// set the timer to $22aa00 and enable it on regular irq
for(b in listOf(0xa9, 0x00, 0x8d, 0x00, 0xd2, 0xa9, 0x00, 0x8d, 0x01, 0xd2, 0xa9, 0xaa, 0x8d, 0x02,
0xd2, 0xa9, 0x22, 0x8d, 0x03, 0xd2, 0xa9, 0x01, 0x8d, 0x00, 0xd2, 0x4c, 0x19, 0x10).withIndex()) {
ram[0x1000+b.index] = b.value.toShort()
}
// load the irq routine that prints 'irq!' to the parallel port
for(b in listOf(0x48, 0xa9, 0x09, 0x8d, 0x00, 0xd0, 0xee, 0x01, 0xd0, 0xa9, 0x12, 0x8d, 0x00, 0xd0,
0xee, 0x01, 0xd0, 0xa9, 0x11, 0x8d, 0x00, 0xd0, 0xee, 0x01, 0xd0, 0xa9, 0x21, 0x8d, 0x00, 0xd0,
0xee, 0x01, 0xd0, 0x68, 0x40).withIndex()) {
ram[0x2000+b.index] = b.value.toShort()
}
val parallel = ParallelPort(0xd000, 0xd001)
val clock = RealTimeClock(0xd100, 0xd108)
val timer = Timer(0xd200, 0xd203, cpu)
val bus = Bus()
bus.add(cpu)
bus.add(parallel)
bus.add(clock)
bus.add(timer)
bus.add(ram)
bus.reset()
cpu.Status.I = false // enable interrupts
try {
while (true) {
bus.clock()
}
} catch (ix: Cpu6502.InstructionError) {
println("HMMM $ix")
// ignore
}
ram.hexDump(0x1000, 0x1020)
val dis = cpu.disassemble(ram, 0x1000, 0x1020)
println(dis.joinToString("\n"))
ram.hexDump(0x2000, 0x2008)
}

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src/main/kotlin/net/razorvine/ksim65/components/Bus.kt Normal file
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package net.razorvine.ksim65.components
class Bus {
private val components = mutableListOf<BusComponent>()
private val memComponents = mutableListOf<MemMappedComponent>()
fun reset() {
components.forEach { it.reset() }
memComponents.forEach { it.reset() }
}
fun clock() {
components.forEach { it.clock() }
memComponents.forEach { it.clock() }
}
fun add(component: BusComponent) {
components.add(component)
component.bus = this
}
fun add(component: MemMappedComponent) {
memComponents.add(component)
component.bus = this
}
fun read(address: Address): UByte {
memComponents.forEach {
if(address>=it.startAddress && address<=it.endAddress)
return it[address]
}
return 0xff
}
fun write(address: Address, data: UByte) {
memComponents.forEach {
if(address>=it.startAddress && address<=it.endAddress)
it[address] = data
}
}
}

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src/main/kotlin/net/razorvine/ksim65/components/Component.kt Normal file
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package net.razorvine.ksim65.components
import net.razorvine.ksim65.Petscii
typealias UByte = Short
typealias Address = Int
abstract class BusComponent {
lateinit var bus: Bus
abstract fun clock()
abstract fun reset()
}
abstract class MemMappedComponent(val startAddress: Address, val endAddress: Address): BusComponent() {
abstract operator fun get(address: Address): UByte
abstract operator fun set(address: Address, data: UByte)
init {
require(endAddress>=startAddress)
require(startAddress>=0 && endAddress <= 0xffff) { "can only have 16-bit address space" }
}
fun hexDump(from: Address, to: Address) {
(from .. to).chunked(16).forEach {
print("\$${it.first().toString(16).padStart(4, '0')} ")
val bytes = it.map { address -> get(address) }
bytes.forEach { byte ->
print(byte.toString(16).padStart(2, '0') + " ")
}
print(" ")
print(Petscii.decodeScreencode(bytes, false).replace('\ufffe', '.'))
println()
}
}
}
abstract class MemoryComponent(startAddress: Address, endAddress: Address): MemMappedComponent(startAddress, endAddress) {
abstract fun cloneContents(): Array<UByte>
}

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src/main/kotlin/net/razorvine/ksim65/components/Cpu6502.kt Normal file
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src/main/kotlin/net/razorvine/ksim65/components/Cpu65C02.kt Normal file
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package net.razorvine.ksim65.components
class Cpu65C02(stopOnBrk: Boolean): Cpu6502(stopOnBrk) {
val waiting: Boolean = false
// TODO implement this CPU type 65C02, and re-enable the unit tests for that
}

37
src/main/kotlin/net/razorvine/ksim65/components/ParallelPort.kt Normal file
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package net.razorvine.ksim65.components
import net.razorvine.ksim65.Petscii
/**
* A parallel output device (basically, prints bytes as characters to the screen)
* First address = data byte (8 parallel bits)
* Second address = control byte (bit 0 high = write byte)
*/
class ParallelPort(startAddress: Address, endAddress: Address) : MemMappedComponent(startAddress, endAddress) {
var dataByte: UByte = 0
init {
require(endAddress - startAddress + 1 == 2) { "parallel needs exactly 2 memory bytes (data + control)" }
}
override fun clock() {}
override fun reset() {}
override operator fun get(address: Address): UByte {
return if (address == startAddress)
dataByte
else
0
}
override operator fun set(address: Address, data: UByte) {
if (address == startAddress)
dataByte = data
else if (address == endAddress) {
if ((data.toInt() and 1) == 1) {
val char = Petscii.decodeScreencode(listOf(dataByte), false).first()
println("PARALLEL WRITE: '$char'")
}
}
}
}

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src/main/kotlin/net/razorvine/ksim65/components/Ram.kt Normal file
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package net.razorvine.ksim65.components
import java.io.File
class Ram(startAddress: Address, endAddress: Address): MemoryComponent(startAddress, endAddress) {
private val memory = ShortArray(endAddress-startAddress+1)
override operator fun get(address: Address): UByte = memory[address-startAddress]
override operator fun set(address: Address, data: UByte) {
memory[address-startAddress] = data
}
override fun cloneContents(): Array<UByte> = memory.toTypedArray()
override fun clock() { }
override fun reset() {
// contents of RAM doesn't change on a reset
}
fun fill(data: UByte) {
memory.fill(data)
}
/**
* load a c64-style prg program at the given address,
* this file has the load address as the first two bytes.
*/
fun loadPrg(filename: String) {
val bytes = File(filename).readBytes()
val address = (bytes[0].toInt() or (bytes[1].toInt() shl 8)) and 65535
bytes.drop(2).forEachIndexed { index, byte ->
memory[address+index] =
if(byte>=0)
byte.toShort()
else
(256+byte).toShort()
}
}
/**
* load a binary program at the given address
*/
fun load(filename: String, address: Address) {
val bytes = File(filename).readBytes()
bytes.forEachIndexed { index, byte ->
memory[address+index] =
if(byte>=0)
byte.toShort()
else
(256+byte).toShort()
}
}
}

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package net.razorvine.ksim65.components
import java.time.LocalDate
import java.time.LocalTime
/**
* A real-time clock (time of day clock).
* byte value
* 00 year (lsb)
* 01 year (msb)
* 02 month, 1-12
* 03 day, 1-31
* 04 hour, 0-23
* 05 minute, 0-59
* 06 second, 0-59
* 07 millisecond, 0-999 (lsb)
* 08 millisecond, 0-999 (msb)
*/
class RealTimeClock(startAddress: Address, endAddress: Address) : MemMappedComponent(startAddress, endAddress) {
init {
require(endAddress - startAddress + 1 == 9) { "rtc needs exactly 9 memory bytes" }
}
override fun clock() {
/* not updated on clock pulse */
}
override fun reset() {
/* never reset */
}
override operator fun get(address: Address): UByte {
return when (address - startAddress) {
0 -> {
val year = LocalDate.now().year
(year and 255).toShort()
}
1 -> {
val year = LocalDate.now().year
(year ushr 8).toShort()
}
2 -> LocalDate.now().monthValue.toShort()
3 -> LocalDate.now().dayOfMonth.toShort()
4 -> LocalTime.now().hour.toShort()
5 -> LocalTime.now().minute.toShort()
6 -> LocalTime.now().second.toShort()
7 -> {
val ms = LocalTime.now().nano / 1000
(ms and 255).toShort()
}
8 -> {
val ms = LocalTime.now().nano / 1000
(ms ushr 8).toShort()
}
else -> 0
}
}
override operator fun set(address: Address, data: UByte) {
/* real time clock can't be set */
}
}

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package net.razorvine.ksim65.components
class Rom(startAddress: Address, endAddress: Address, data: Array<UByte>? = null) : MemoryComponent(startAddress, endAddress) {
private val memory =
if (data == null)
ShortArray(endAddress - startAddress - 1)
else
ShortArray(data.size) { index -> data[index] }
init {
if (data != null)
require(endAddress - startAddress + 1 == data.size) { "rom address range doesn't match size of data bytes" }
}
override operator fun get(address: Address): UByte = memory[address - startAddress]
override operator fun set(address: Address, data: UByte) {}
override fun cloneContents(): Array<UByte> = memory.toTypedArray()
override fun clock() {}
override fun reset() {}
}

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package net.razorvine.ksim65.components
/**
* A programmable timer. Causes an IRQ or NMI at specified 24-bits intervals.
* byte value
* 00 control register bit 0=enable bit 1=nmi (instead of irq)
* 01 24 bits interval value, bits 0-7 (lo)
* 02 24 bits interval value, bits 8-15 (mid)
* 03 24 bits interval value, bits 16-23 (hi)
*/
class Timer(startAddress: Address, endAddress: Address, val cpu: Cpu6502) : MemMappedComponent(startAddress, endAddress) {
private var counter: Int = 0
private var interval: Int = 0
private var nmi = false
private var enabled = false
set(value) {
if(value && !field) {
// timer is set to enabled (was disabled) - reset the counter
counter = 0
}
field = value
}
init {
require(endAddress - startAddress + 1 == 4) { "timer needs exactly 4 memory bytes" }
}
override fun clock() {
if (enabled && interval > 0) {
counter++
if (counter == interval) {
if (nmi)
cpu.nmi(this)
else
cpu.irq(this)
counter = 0
}
}
}
override fun reset() {
counter = 0
interval = 0
enabled = false
nmi = false
}
override operator fun get(address: Address): UByte {
when (address - startAddress) {
0 -> {
var data = 0
if (enabled) data = data or 0b00000001
if (nmi) data = data or 0b00000010
return data.toShort()
}
1 -> {
return (counter and 0xff).toShort()
}
2 -> {
return ((counter ushr 8) and 0xff).toShort()
}
3 -> {
return ((counter ushr 16) and 0xff).toShort()
}
else -> return 0
}
}
override operator fun set(address: Address, data: UByte) {
when (address - startAddress) {
0 -> {
val i = data.toInt()
enabled = (i and 0b00000001) != 0
nmi = (i and 0b00000010) != 0
}
1 -> {
interval = (interval and 0x7fffff00) or data.toInt()
}
2 -> {
interval = (interval and 0x7fff00ff) or (data.toInt() shl 8)
}
3 -> {
interval = (interval and 0x7f00ffff) or (data.toInt() shl 16)
}
}
}
}

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1.0

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; Verify decimal mode behavior
; Written by Bruce Clark. This code is public domain.
; see http://www.6502.org/tutorials/decimal_mode.html
;
; Returns:
; ERROR = 0 if the test passed
; ERROR = 1 if the test failed
; modify the code at the DONE label for desired program end
;
; This routine requires 17 bytes of RAM -- 1 byte each for:
; AR, CF, DA, DNVZC, ERROR, HA, HNVZC, N1, N1H, N1L, N2, N2L, NF, VF, and ZF
; and 2 bytes for N2H
;
; Variables:
; N1 and N2 are the two numbers to be added or subtracted
; N1H, N1L, N2H, and N2L are the upper 4 bits and lower 4 bits of N1 and N2
; DA and DNVZC are the actual accumulator and flag results in decimal mode
; HA and HNVZC are the accumulator and flag results when N1 and N2 are
; added or subtracted using binary arithmetic
; AR, NF, VF, ZF, and CF are the predicted decimal mode accumulator and
; flag results, calculated using binary arithmetic
;
; This program takes approximately 1 minute at 1 MHz (a few seconds more on
; a 65C02 than a 6502 or 65816)
;
; Configuration:
cputype = 0 ; 0 = 6502, 1 = 65C02, 2 = 65C816
vld_bcd = 0 ; 0 = allow invalid bcd, 1 = valid bcd only
chk_a = 1 ; check accumulator
chk_n = 0 ; check sign (negative) flag
chk_v = 0 ; check overflow flag
chk_z = 0 ; check zero flag
chk_c = 1 ; check carry flag
end_of_test macro
db $db ;execute 65C02 stop instruction
endm
bss
org 0
; operands - register Y = carry in
N1 ds 1
N2 ds 1
; binary result
HA ds 1
HNVZC ds 1
;04
; decimal result
DA ds 1
DNVZC ds 1
; predicted results
AR ds 1
NF ds 1
;08
VF ds 1
ZF ds 1
CF ds 1
ERROR ds 1
;0C
; workspace
N1L ds 1
N1H ds 1
N2L ds 1
N2H ds 2
code
org $200
TEST ldy #1 ; initialize Y (used to loop through carry flag values)
sty ERROR ; store 1 in ERROR until the test passes
lda #0 ; initialize N1 and N2
sta N1
sta N2
LOOP1 lda N2 ; N2L = N2 & $0F
and #$0F ; [1] see text
if vld_bcd = 1
cmp #$0a
bcs NEXT2
endif
sta N2L
lda N2 ; N2H = N2 & $F0
and #$F0 ; [2] see text
if vld_bcd = 1
cmp #$a0
bcs NEXT2
endif
sta N2H
ora #$0F ; N2H+1 = (N2 & $F0) + $0F
sta N2H+1
LOOP2 lda N1 ; N1L = N1 & $0F
and #$0F ; [3] see text
if vld_bcd = 1
cmp #$0a
bcs NEXT1
endif
sta N1L
lda N1 ; N1H = N1 & $F0
and #$F0 ; [4] see text
if vld_bcd = 1
cmp #$a0
bcs NEXT1
endif
sta N1H
jsr ADD
jsr A6502
jsr COMPARE
bne DONE
jsr SUB
jsr S6502
jsr COMPARE
bne DONE
NEXT1 inc N1 ; [5] see text
bne LOOP2 ; loop through all 256 values of N1
NEXT2 inc N2 ; [6] see text
bne LOOP1 ; loop through all 256 values of N2
dey
bpl LOOP1 ; loop through both values of the carry flag
lda #0 ; test passed, so store 0 in ERROR
sta ERROR
DONE
end_of_test
; Calculate the actual decimal mode accumulator and flags, the accumulator
; and flag results when N1 is added to N2 using binary arithmetic, the
; predicted accumulator result, the predicted carry flag, and the predicted
; V flag
;
ADD sed ; decimal mode
cpy #1 ; set carry if Y = 1, clear carry if Y = 0
lda N1
adc N2
sta DA ; actual accumulator result in decimal mode
php
pla
sta DNVZC ; actual flags result in decimal mode
cld ; binary mode
cpy #1 ; set carry if Y = 1, clear carry if Y = 0
lda N1
adc N2
sta HA ; accumulator result of N1+N2 using binary arithmetic
php
pla
sta HNVZC ; flags result of N1+N2 using binary arithmetic
cpy #1
lda N1L
adc N2L
cmp #$0A
ldx #0
bcc A1
inx
adc #5 ; add 6 (carry is set)
and #$0F
sec
A1 ora N1H
;
; if N1L + N2L < $0A, then add N2 & $F0
; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set)
;
adc N2H,x
php
bcs A2
cmp #$A0
bcc A3
A2 adc #$5F ; add $60 (carry is set)
sec
A3 sta AR ; predicted accumulator result
php
pla
sta CF ; predicted carry result
pla
;
; note that all 8 bits of the P register are stored in VF
;
sta VF ; predicted V flags
rts
; Calculate the actual decimal mode accumulator and flags, and the
; accumulator and flag results when N2 is subtracted from N1 using binary
; arithmetic
;
SUB sed ; decimal mode
cpy #1 ; set carry if Y = 1, clear carry if Y = 0
lda N1
sbc N2
sta DA ; actual accumulator result in decimal mode
php
pla
sta DNVZC ; actual flags result in decimal mode
cld ; binary mode
cpy #1 ; set carry if Y = 1, clear carry if Y = 0
lda N1
sbc N2
sta HA ; accumulator result of N1-N2 using binary arithmetic
php
pla
sta HNVZC ; flags result of N1-N2 using binary arithmetic
rts
if cputype != 1
; Calculate the predicted SBC accumulator result for the 6502 and 65816
;
SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0
lda N1L
sbc N2L
ldx #0
bcs S11
inx
sbc #5 ; subtract 6 (carry is clear)
and #$0F
clc
S11 ora N1H
;
; if N1L - N2L >= 0, then subtract N2 & $F0
; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear)
;
sbc N2H,x
bcs S12
sbc #$5F ; subtract $60 (carry is clear)
S12 sta AR
rts
endif
if cputype = 1
; Calculate the predicted SBC accumulator result for the 6502 and 65C02
;
SUB2 cpy #1 ; set carry if Y = 1, clear carry if Y = 0
lda N1L
sbc N2L
ldx #0
bcs S21
inx
and #$0F
clc
S21 ora N1H
;
; if N1L - N2L >= 0, then subtract N2 & $F0
; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear)
;
sbc N2H,x
bcs S22
sbc #$5F ; subtract $60 (carry is clear)
S22 cpx #0
beq S23
sbc #6
S23 sta AR ; predicted accumulator result
rts
endif
; Compare accumulator actual results to predicted results
;
; Return:
; Z flag = 1 (BEQ branch) if same
; Z flag = 0 (BNE branch) if different
;
COMPARE
if chk_a = 1
lda DA
cmp AR
bne C1
endif
if chk_n = 1
lda DNVZC ; [7] see text
eor NF
and #$80 ; mask off N flag
bne C1
endif
if chk_v = 1
lda DNVZC ; [8] see text
eor VF
and #$40 ; mask off V flag
bne C1 ; [9] see text
endif
if chk_z = 1
lda DNVZC
eor ZF ; mask off Z flag
and #2
bne C1 ; [10] see text
endif
if chk_c = 1
lda DNVZC
eor CF
and #1 ; mask off C flag
endif
C1 rts
; These routines store the predicted values for ADC and SBC for the 6502,
; 65C02, and 65816 in AR, CF, NF, VF, and ZF
if cputype = 0
A6502 lda VF ; 6502
;
; since all 8 bits of the P register were stored in VF, bit 7 of VF contains
; the N flag for NF
;
sta NF
lda HNVZC
sta ZF
rts
S6502 jsr SUB1
lda HNVZC
sta NF
sta VF
sta ZF
sta CF
rts
endif
if cputype = 1
A6502 lda AR ; 65C02
php
pla
sta NF
sta ZF
rts
S6502 jsr SUB2
lda AR
php
pla
sta NF
sta ZF
lda HNVZC
sta VF
sta CF
rts
endif
if cputype = 2
A6502 lda AR ; 65C816
php
pla
sta NF
sta ZF
rts
S6502 jsr SUB1
lda AR
php
pla
sta NF
sta ZF
lda HNVZC
sta VF
sta CF
rts
endif
end TEST

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GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
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This is a set of functional tests for the 6502/65C02 type processors.
The 6502_functional_test.a65 is an assembler sourcecode to test all valid
opcodes and addressing modes of the original NMOS 6502 cpu.
The 65C02_extended_opcodes_test.a65c tests all additional opcodes of the
65C02 processor including undefined opcodes.
The 6502_interrupt_test.a65 is a simple test to check the interrupt system
of both processors. A feedback register is required to inject IRQ and NMI
requests.
Detailed information about how to configure, assemble and run the tests is
included in each source file.
The tests have primarily been written to test my own ATMega16 6502 emulator
project. You can find it here: http://2m5.de/6502_Emu/index.htm
A discussion about the tests can be found here:
http://forum.6502.org/viewtopic.php?f=2&t=2241
Good luck debugging your emulator, simulator, fpga core, discrete
logic implementation or whatever you have!

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src/test/kotlin/6502_functional_tests/report.i65 Normal file
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;**** report 6502 funtional test errors to standard I/O ****
;
;this include file is part of the 6502 functional tests
;it is used when you configure report = 1 in the tests
;
;to adopt the standard output vectors of your test environment
;you must modify the rchar and rget subroutines in this include
;
;I/O hardware may have to be initialized in report_init
;print message macro - \1 = message location
rprt macro
ldx #0
lda \1
loop\?
jsr rchar
inx
lda \1,x
bne loop\?
endm
;initialize I/O as required (example: configure & enable ACIA)
report_init
;nothing to initialize
rprt rmsg_start
rts
;show stack (with saved registers), zeropage and absolute memory workspace
;after an error was trapped in the test program
report_error
;save registers
php
pha
txa
pha
tya
pha
cld
;show stack with index to registers at error
rprt rmsg_stack
tsx
inx
lda #1 ;address high
jsr rhex
txa ;address low
jsr rhex
rstack jsr rspace
lda $100,x ;stack data
jsr rhex
inx
bne rstack
jsr rcrlf ;new line
;show zero page workspace
lda #0
jsr rhex
lda #zpt
tax
jsr rhex
rzp jsr rspace
lda 0,x
jsr rhex
inx
cpx #zp_bss
bne rzp
jsr rcrlf
;show absolute workspace
lda #hi(data_segment)
jsr rhex
lda #lo(data_segment)
jsr rhex
ldx #0
rabs jsr rspace
lda data_segment,x
jsr rhex
inx
cpx #(data_bss-data_segment)
bne rabs
;ask to continue
rprt rmsg_cont
rerr1 jsr rget
cmp #'S'
beq rskip
cmp #'C'
bne rerr1
;restore registers
pla
tay
pla
tax
pla
plp
rts
;skip the current test
rskip lda #$f0 ;already end of tests?
cmp test_case
beq rerr1 ;skip is not available
ldx #$ff ;clear stack
txs
inc test_case ;next test
lda #lo(start) ;find begin of test
sta zpt
lda #hi(start)
sta zpt+1
rskipl1 ldy #4 ;search pattern
rskipl2 lda (zpt),y ;next byte
cmp rmark,y
bne rskipnx ;no match
dey
bmi rskipf ;found pattern
cpy #1 ;skip immediate value
bne rskipl2
dey
beq rskipl2
rskipnx inc zpt ;next RAM location
bne rskipl1
inc zpt+1
bne rskipl1
rskipf ldy #1 ;pattern found - check test number
lda (zpt),y ;test number
cmp #$f0 ;end of last test?
beq rskipe ;ask to rerun all
cmp test_case ;is next test?
bne rskipnx ;continue searching
rskipe jmp (zpt) ;start next test or rerun at end of tests
rmark lda #0 ;begin of test search pattern
sta test_case
;show test has ended, ask to repeat
report_success
if rep_int = 1
rprt rmsg_priority
lda data_segment ;show interrupt sequence
jsr rhex
jsr rspace
lda data_segment+1
jsr rhex
jsr rspace
lda data_segment+2
jsr rhex
endif
rprt rmsg_success
rsuc1 jsr rget
cmp #'R'
bne rsuc1
rts
;input subroutine
;get a character from standard input
;adjust according to the needs in your test environment
rget ;get character in A
;rget1
; lda $bff1 ;wait RDRF
; and #8
; beq rget1
;not a real ACIA - so RDRF is not checked
; lda $bff0 ;read acia rx reg
lda $f004 ;Kowalski simulator default
;the load can be replaced by a call to a kernal routine
; jsr $ffcf ;example: CHRIN for a C64
cmp #'a' ;lower case
bcc rget1
and #$5f ;convert to upper case
rget1 rts
;output subroutines
rcrlf lda #10
jsr rchar
lda #13
bne rchar
rspace lda #' '
bne rchar
rhex pha ;report hex byte in A
lsr a ;high nibble first
lsr a
lsr a
lsr a
jsr rnib
pla ;now low nibble
and #$f
rnib clc ;report nibble in A
adc #'0' ;make printable 0-9
cmp #'9'+1
bcc rchar
adc #6 ;make printable A-F
;send a character to standard output
;adjust according to the needs in your test environment
;register X needs to be preserved!
rchar ;report character in A
; pha ;wait TDRF
;rchar1 lda $bff1
; and #$10
; beq rchar1
; pla
;not a real ACIA - so TDRF is not checked
; sta $bff0 ;write acia tx reg
sta $f001 ;Kowalski simulator default
;the store can be replaced by a call to a kernal routine
; jsr $ffd2 ;example: CHROUT for a C64
rts
rmsg_start
db 10,13,"Started testing",10,13,0
rmsg_stack
db 10,13,"regs Y X A PS PCLPCH",10,13,0
rmsg_cont
db 10,13,"press C to continue or S to skip current test",10,13,0
rmsg_success
db 10,13,"All tests completed, press R to repeat",10,13,0
if rep_int = 1
rmsg_priority
db 10,13,"interrupt sequence (NMI IRQ BRK) ",0
endif

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src/test/kotlin/6502testsuite/_Test Suite 2.15.txt Normal file
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C64 Emulator Test Suite - Public Domain, no Copyright
https://github.com/mattgodbolt/jsbeeb/blob/master/tests/suite/cbm-hackers-post.md
The purpose of the C64 Emulator Test Suite is
- to help C64 emulator authors improve the compatibility
- ensure that updated emulators have no new bugs in old code parts
The suite are a few hundred C64 programs which check the details of the C64 they are running on. The suite runs automated and stops only if it has detected an error. That the suite doesn't stop on my C64-I/PAL proves that the suite has no bugs. That the same suite doesn't stop on an emulator proves that this particular emulator is compatible to my C64 regarding every tested detail. Of course, the emulator may still have bugs in parts which are not tested by the suite. There may also be a difference between your C64 and my C64.
While the Test Suite is running, the Datasette should be disconnected. Needs about 80 min to complete.
The source code has been developed with MACRO(SS)ASS+ by Wolfram Roemhild. The file TEMPLATE.ASM provides a starting point for adding new tests to the suite.
///////////////////////////////////////////////////////////////////////////////
Program _START - some 6510 basic commands, just as an insurance
///////////////////////////////////////////////////////////////////////////////
Programs LDAb to SBCb(EB) - 6510 command function
addressing modes
-----------------------------------
n none (implied and accu)
b byte (immediate)
w word (absolute for JMP and JSR)
z zero page
zx zero page,x
zy zero page,y
a absolute
ax absolute,x
ay absolute,y
i indirect (JMP)
ix (indirect,x)
iy (indirect),y
r relative
Display:
before data accu xreg yreg flags sp
after data accu xreg yreg flags sp
right data accu xreg yreg flags sp
Either press STOP or any other key to continue.
All 256 opcodes are tested except HLTn (02 12 22 32 42 52 62 72 92 B2 D2 F2).
Indexed addressing modes count the index registers from 00 to FF.
JMPi (xxFF) is tested.
Single operand commands: 256 data combinations from 00 to FF multiplied by 256 flag combinations.
Two operand commands: 256 data combinations 00/00, 00/11, ... FF/EE, FF/FF multiplied by 256 flag combinations.
ANEb, LASay, SHAay, SHAiy, SHXay, SHYax and SHSay are executed only in the y border. These commands cause unpredictable results when a DMA comes between the command byte and the operand.
SHAay, SHAiy, SHXay, SHYax and SHSay are tested on a data address xxFF only. When the hibyte of the indexed address needs adjustment, these commands will write to different locations, depending on the data written.
///////////////////////////////////////////////////////////////////////////////
Programs TRAP* - 6510 IO traps, page boundaries and wrap arounds
# code data zd zptr aspect tested
-----------------------------------------------------------------------------
1 2800 29C0 F7 F7/F8 basic functionality
2 2FFE 29C0 F7 F7/F8 4k boundary within 3 byte commands
3 2FFF 29C0 F7 F7/F8 4k boundary within 2 and 3 byte commands
4 D000 29C0 F7 F7/F8 IO traps for code fetch
5 CFFE 29C0 F7 F7/F8 RAM/IO boundary within 3 byte commands
6 CFFF 29C0 F7 F7/F8 RAM/IO boundary within 2 and 3 byte commands
7 2800 D0C0 F7 F7/F8 IO traps for 16 bit data access
8 2800 D000 F7 F7/F8 IO trap adjustment in ax, ay and iy addressing
9 2800 29C0 02 F7/F8 wrap around in zx and zy addressing
10 2800 29C0 00 F7/F8 IO traps for 8 bit data access
11 2800 29C0 F7 02/03 wrap around in ix addressing
12 2800 29C0 F7 FF/00 wrap around and IO trap for pointer accesses
13 2800 0002 F7 F7/F8 64k wrap around in ax, ay and iy addressing
14 2800 0000 F7 F7/F8 64k wrap around plus IO trap
15 CFFF D0C6 00 FF/00 1-14 all together as a stress test
16 FFFE ---- -- --/-- 64k boundary within 3 byte commands
17 FFFF ---- -- --/-- 64k boundary within 2 and 3 byte commands
In the programs TRAP16 and TRAP17, the locations of data, zerodata and zeroptr depend on the addressing mode. The CPU port at 00/01 is not able to hold all 256 bit combinations.
The datasette may not be connected while TRAP16 and TRAP17 are running!
Display:
after data accu xreg yreg flags
right data accu xreg yreg flags
If all displayed values match, some other aspect is wrong, e.g. the stack pointer or data on stack.
All 256 commands are tested except HLTn. Registers before:
data 1B (00 01 10 11)
accu C6 (11 00 01 10)
xreg B1 (10 11 00 01)
yreg 6C (01 10 11 00)
flags 00
sptr not initialized, typically F8
The code length is 6 bytes maximum (SHSay).
When the lowbyte of the data address is less than C0, SHAay, SHAiy, SHXay, SHYax and SHSay aren't tested. Those commands don't handle the address adjustment correctly.
Relative jumps are tested in 4 combinations: offset 01 no jump, offset 01 jump, offset 80 no jump, offset 80 jump. For the offset 80, a RTS is written to the location at code - 7E.
///////////////////////////////////////////////////////////////////////////////
Program BRANCHWRAP - Forward branches from FFxx to 00xx
Backward branches from 00xx to FFxx were already tested in TRAP16 and TRAP17.
///////////////////////////////////////////////////////////////////////////////
Program MMUFETCH - 6510 code fetching while memory configuration changes
An example is the code sequence LDA #$37 : STA 1 : BRK in RAM at Axxx. Because STA 1 maps the Basic ROM, the BRK will never get executed.
addr sequence
---------------------
A4DF RAM-Basic-RAM
B828 RAM-Basic-RAM
EA77 RAM-Kernal-RAM
FD25 RAM-Kernal-RAM
D400 RAM-Charset-RAM
D000 RAM-IO-RAM
The sequence IO-Charset-IO is not tested because I didn't find some appropriate code bytes in the Charset ROM at D000-D3FF. The SID registers at D4xx are write-only.
///////////////////////////////////////////////////////////////////////////////
Program MMU - 6510 port at 00/01 bits 0-2
Display:
0/1=0-7 repeated 6 times: values stored in 0 and 1
after 0 1 A000 E000 D000 IO
right 0 1 A000 E000 D000 IO
address value meaning
----------------------------------------
A000 94 read Basic, write RAM
A000 01 read/write RAM
E000 86 read Kernal, write RAM
E000 01 read/write RAM
D000/IO 3D/02 read Charset, write RAM
D000/IO 01/02 read/write RAM
D000/IO 00/03 read/write IO
///////////////////////////////////////////////////////////////////////////////
Program CPUPORT - 6510 port at 00/01 bits 0-7
Display:
0/1=00/FF repeated 6 times: values stored in 0 and 1
after 00 01
right 00 01
The datasette may not be connected while CPUPORT is running!
If both values match, the port behaves instable. On my C64, this will only happen when a datasette is connected.
///////////////////////////////////////////////////////////////////////////////
Program CPUTIMING - 6510 timing whole commands
Display:
xx command byte
clocks #measured
right #2
#1 #2 command or addressing mode
--------------------------------------
2 2 n
2 2 b
3 3 Rz/Wz
5 5 Mz
4 8 Rzx/Rzy/Wzx/Wzy
6 10 Mzx/Mzy
4 4 Ra/Wa
6 6 Ma
4 8 Rax/Ray (same page)
5 9 Rax/Ray (different page)
5 9 Wax/Way
7 11 Max/May
6 8 Rix/Wix
8 10 Mix/Miy
5 7 Riy (same page)
6 8 Riy (different page)
6 8 Wiy
8 10 Miy
2 18 r+00 same page not taken
3 19 r+00 same page taken
3 19 r+7F same page taken
4 20 r+01 different page taken
4 20 r+7F different page taken
3 19 r-03 same page taken
3 19 r-80 same page taken
4 20 r-03 different page taken
4 20 r-80 different page taken
7 7 BRKn
3 3 PHAn/PHPn
4 4 PLAn/PLPn
3 3 JMPw
5 5 JMPi
6 6 JSRw
6 6 RTSn
6 6 RTIn
#1 = command execution time without overhead
#2 = displayed value including overhead for measurement
R/W/M = Read/Write/Modify
///////////////////////////////////////////////////////////////////////////////
Programs IRQ and NMI - CPU interrupts within commands
Tested are all commands except HLTn. For a command of n cycles, a loop with the interrupt occurring before cycle 1..n is performed. Rax/Ray/Riy addressing is tested with both the same page and a different page. Branches are tested not taken, taken to the same page, and taken to a different page.
Display:
stack <address> <flags on stack& $14> <flags in handler & $14>
right <address> <flags on stack& $14> <flags in handler & $14>
When an interrupt occurs 2 or more cycles before the current command ends, it is executed immediately after the command. Otherwise, the CPU executes the next command first before it calls the interrupt handler.
The only exception to this rule are taken branches to the same page which last 3 cycles. Here, the interrupt must have occurred before clock 1 of the branch command; the normal rule says before clock 2. Branches to a different page or branches not taken are behaving normal.
The 6510 will set the IFlag on NMI, too. 6502 untested.
When an IRQ occurs while SEIn is executing, the IFlag on the stack will be set.
When an NMI occurs before clock 4 of a BRKn command, the BRK is finished as a NMI. In this case, BFlag on the stack will not be cleared.
///////////////////////////////////////////////////////////////////////////////
Programs CIA1TB123 and CIA2TB123 - CIA timer B 1-3 cycles after writing CRB
The cycles 1-3 after STA DD0F cannot be measured with LDA DD06 because it takes 3 cycles to decode the LDAa. Executing the STA DD0F at DD03 lets the CPU read DD06 within one cycle.
#1 #2 DD06 sequence 1/2/3 (4)
---------------------------------
00 01 keep keep count count
00 10 keep load keep keep
00 11 keep load keep count
01 11 count load keep count
01 10 count load keep keep
01 00 count count keep keep
#1, #2 = values written to DD0F
///////////////////////////////////////////////////////////////////////////////
Programs CIA1PB6 to CIA2PB7 - CIA timer output to PB6 and PB7
Checks 128 combinations of CRA/B in One Shot mode:
old CRx bit 0 Start
CRx bit 1 PBxOut
CRx bit 2 PBxToggle
new CRx bit 0 Start
CRx bit 1 PBxOut
CRx bit 2 PBxToggle
CRx bit 4 Force Load
The resulting PB6/7 bit is:
0 if new PBxToggle is 0
1 if new PBxToggle is 1
- (undetermined) if PBxOut is 0
Old values do not influence the result. Start and Force Load don't either.
Next, the programs test if PBx is toggled to 0 on the first underflow and that neither writing CRx except bit 0 nor Timer Hi/Lo will set it back to 1. The only source which is able to reset the toggle line is a rising edge on the Start bit 0 of CRx.
Another test verifies that the toggle line is independent from PBxOut and PBxToggle. Changing these two bits will have no effect on switching the toggle flip flop when the timer underflows.
The last test checks for the correct timing in Pulse and Toggle Mode.
///////////////////////////////////////////////////////////////////////////////
Program CIA1TAB - TA, TB, PB67 and ICR in cascaded mode
Both latches are set to 2. TA counts system clocks, TB counts TA underflows (cascaded). PB6 is high for one cycle when TA underflows, PB7 is toggled when TB underflows. IMR is $02.
TA 01 02 02 01 02 02 01 02 02 01 02 02
TB 02 02 02 01 01 01 00 00 02 02 02 02
PB 80 C0 80 80 C0 80 80 C0 00 00 40 00
ICR 00 01 01 01 01 01 01 01 03 83 83 83
If one of the registers doesn't match this table, the program displays the wrong values with red color.
///////////////////////////////////////////////////////////////////////////////
Program LOADTH - Load timer high byte
Writing to the high byte of the latch may load the counter only when it is not running.
writing counter load
------------------------
high byte stopped yes
high byte running no
low byte stopped no
low byte running no
///////////////////////////////////////////////////////////////////////////////
Program CNTO2 - Switches between CNT and o2 input
When the timer input is switched from o2 to CNT or from CNT back to o2, there must be a two clock delay until the switch is recognized.
///////////////////////////////////////////////////////////////////////////////
Program ICR01 - Reads ICR around an underflow
Reads ICR when an underflow occurs and checks if the NMI is executed.
time ICR NMI
--------------
t-1 00 yes
t 01 no
t+1 81 yes
///////////////////////////////////////////////////////////////////////////////
Program IMR - Interrupt mask register
When a condition in the ICR is true, setting the corresponding bit in the IMR must also set the interrupt. Clearing the bit in the IMR may not clear the interrupt. Only reading the ICR may clear the interrupt.
///////////////////////////////////////////////////////////////////////////////
Program FLIPOS - Flip one shot
Sets and clears the one shot bit when an underflow occurs at t. Set must take effect at t-1, clear at t-2.
time set clear
------------------
t-2 stop count
t-1 stop stop
t count stop
///////////////////////////////////////////////////////////////////////////////
Program ONESHOT - Checks for start bit cleared
Reads CRA in one shot mode with an underflow at t.
time CRA
---------
t-1 $09
t $08
///////////////////////////////////////////////////////////////////////////////
Program CNTDEF - CNT default
CNT must be high by default. This is tested with timer B cascaded mode CRB = $61.
*******************************************
** U N D E R C O N S T R U C T I O N **
*******************************************
///////////////////////////////////////////////////////////////////////////////
Programs CIA1TA to CIA2TB - CIA timers in sysclock mode
PC64Win 2.15 bug:
before 05/02/01/00
after xx
cr 11/19
after xx
timer low doesn't match

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