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https://github.com/irmen/ksim65.git
synced 2025-04-22 11:37:45 +00:00
fix disassembly of address wrap arounds
This commit is contained in:
Irmen de Jong
parent
b7ebf6c922
commit
7f3dd9c95d
src
@ -94,6 +94,8 @@ open class Cpu6502 : BusComponent() {
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val regP = StatusRegister()
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var currentOpcode: Int = 0
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protected set
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var currentOpcodeAddress: Address = 0 // the PC can be changed already depending on the addressing mode
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protected set
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var instrCycles: Int = 0
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protected set
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@ -167,8 +169,7 @@ open class Cpu6502 : BusComponent() {
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[location+1]
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val rel = memory[location+2]
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val target = if (rel <= 0x7f) location+3+rel+baseAddress
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else location+3-(256-rel)+baseAddress
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val target = (if (rel <= 0x7f) location+3+rel+baseAddress else location+3-(256-rel)+baseAddress) and 0xffff
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Pair(line+"${hexB(zpAddr)} ${hexB(rel)} $spacing3 ${opcode.mnemonic} \$${hexB(zpAddr)}, \$${hexW(target, true)}", 3)
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}
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AddrMode.Izp -> {
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@ -193,8 +194,7 @@ open class Cpu6502 : BusComponent() {
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}
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AddrMode.Rel -> {
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val rel = memory[location+1]
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val target = if (rel <= 0x7f) location+2+rel+baseAddress
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else location+2-(256-rel)+baseAddress
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val target = (if (rel <= 0x7f) location+2+rel+baseAddress else location+2-(256-rel)+baseAddress) and 0xffff
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Pair(line+"${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(target, true)}", 2)
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}
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AddrMode.Abs -> {
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@ -268,6 +268,7 @@ open class Cpu6502 : BusComponent() {
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currentInstruction = instructions[0]
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} else {
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// no interrupt, fetch next instruction from memory
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currentOpcodeAddress = regPC
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currentOpcode = read(regPC)
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currentInstruction = instructions[currentOpcode]
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@ -1386,75 +1387,75 @@ open class Cpu6502 : BusComponent() {
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// unofficial/illegal 6502 instructions
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private fun iAhx() {
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TODO("ahx - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - ahx - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iAlr() {
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TODO("alr=asr - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - alr=asr - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iAnc() {
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TODO("anc - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - anc - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iArr() {
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TODO("arr - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - arr - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iAxs() {
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TODO("axs - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - axs - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iDcp() {
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TODO("dcp - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - dcp - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iIsc() {
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TODO("isc=isb - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - isc=isb - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iLas() {
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TODO("las=lar - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - las=lar - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iLax() {
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TODO("lax - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - lax - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iRla() {
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TODO("rla - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - rla - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iRra() {
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TODO("rra - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - rra - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iSax() {
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TODO("sax - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - sax - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iShx() {
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TODO("shx - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - shx - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iShy() {
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TODO("shy - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - shy - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iSlo() {
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TODO("slo=aso - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - slo=aso - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iSre() {
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TODO("sre=lse - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - sre=lse - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iTas() {
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TODO("tas - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - tas - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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private fun iXaa() {
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TODO("xaa - ('illegal' instruction)")
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TODO("\$${hexB(currentOpcode)} - xaa - ('illegal' instruction) @ \$${hexW(currentOpcodeAddress)}")
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}
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// invalid instruction (JAM / KIL)
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@ -14,7 +14,7 @@ fun hexB(number: Short): String = hexB(number.toInt())
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fun hexB(number: Int): String {
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val hexdigits = "0123456789abcdef"
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val loNibble = number and 15
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val hiNibble = number ushr 4
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val hiNibble = (number and 65535) ushr 4
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return hexdigits[hiNibble].toString()+hexdigits[loNibble]
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}
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@ -52,7 +52,7 @@ class Test6502Klaus2m5Functional {
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}
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@Test
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fun testFunctional65C02() {
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fun testExtendedOpcodes65C02() {
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val cpu = Cpu65C02()
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val bus = Bus()
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val ram = Ram(0, 0xffff)
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@ -61,28 +61,22 @@ class Test6502Klaus2m5Functional {
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bus.add(ram)
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cpu.reset()
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cpu.regPC = 0x0400
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cpu.addBreakpoint(0x24f1) { _, _ ->
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// reaching this address means successful test result
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if(cpu.currentOpcode==0x4c)
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throw SuccessfulTestResult()
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Cpu6502.BreakpointResultAction(null, null)
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}
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try {
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while (cpu.totalCycles < 100000000) {
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cpu.clock()
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}
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} catch (sx: SuccessfulTestResult) {
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println("test successful")
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return
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do {
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val previousPC = cpu.regPC
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cpu.step()
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} while(cpu.regPC!=previousPC)
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} catch(nx: NotImplementedError) {
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println("encountered a not yet implemented feature: ${nx.message}")
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}
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println(cpu.snapshot())
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val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
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println(d.first.joinToString ("\n"))
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fail("test failed")
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// the test is successful if address 0x24f1 is reached ("success" label in source code)
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if(cpu.regPC!=0x24f1) {
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println(cpu.snapshot())
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val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
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println(d.first.joinToString("\n"))
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fail("test failed")
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}
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}
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@Test
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@ -96,28 +90,22 @@ class Test6502Klaus2m5Functional {
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bus.add(ram)
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cpu.reset()
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cpu.regPC = 0x0400
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// cpu.addBreakpoint(0x3469) { _, _ ->
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// // reaching this address means successful test result
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// if(cpu.currentOpcode==0x4c)
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// throw SuccessfulTestResult()
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// Cpu6502.BreakpointResultAction(null, null)
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// }
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try {
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while (cpu.totalCycles < 100000000) {
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cpu.clock()
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}
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} catch (sx: SuccessfulTestResult) {
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println("test successful ${cpu.totalCycles}")
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return
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do {
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val previousPC = cpu.regPC
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cpu.step()
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} while(cpu.regPC!=previousPC)
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} catch(nx: NotImplementedError) {
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println("encountered a not yet implemented feature: ${nx.message}")
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}
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println(cpu.snapshot())
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val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
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println(d.first.joinToString ("\n"))
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fail("test failed")
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// the test is successful if address 0x06f5 is reached ("success" label in source code)
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if(cpu.regPC!=0x06f5) {
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println(cpu.snapshot())
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val d = cpu.disassemble(ram, max(0, cpu.regPC-20), min(65535, cpu.regPC+20))
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println(d.first.joinToString("\n"))
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fail("test failed")
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}
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}
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@Test
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