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forgot to checkin the bus changes for memory mapping
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@ -5,13 +5,13 @@ import razorvine.ksim65.components.Rom
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import razorvine.ksim65.components.UByte
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/**
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* The C64's bus is a bit peculiar
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* Appearance of RAM or ROM in certain adress ranges can be dynamically controlled
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* via the 6510's IO port register in $00/$01
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* We only implement banking in or out the character rom or I/O space at $d000-$e000 for now.
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* Doing it here in the bus directly is the poor man's mmu solution, I guess
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* The C64's bus is a bit peculiar:
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* appearance of RAM or ROM in certain address ranges can be dynamically controlled
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* via the 6510's IO port register in $00/$01, "bank switching".
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* More info here https://www.c64-wiki.com/wiki/Bank_Switching
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*
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* TODO: mapping the RAM/ROMs in and out of the other banks in the address space (controlled by loram and hiram).
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* Note: we don't implement the expansion port's _EXROM and _GAME lines that are used
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* for mapping in cartridge ROMs into the address space.
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*/
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class Bus6510(private val ioPort: CpuIoPort,
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private val chargen: Rom,
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@ -19,13 +19,30 @@ class Bus6510(private val ioPort: CpuIoPort,
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private val kernal: Rom): razorvine.ksim65.Bus() {
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override fun read(address: Address): UByte {
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if(address in 0xd000..0xe000) {
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if(!ioPort.charen) {
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// character rom is enabled in this address range (instead of I/O)
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return chargen[address-chargen.startAddress]
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return when(address) {
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in 0x0000..0x9fff -> super.read(address) // always RAM
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in 0xa000..0xbfff -> {
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// BASIC or RAM
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if(ioPort.loram && ioPort.hiram)
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basic[address - 0xa000]
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else
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super.read(address)
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}
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in 0xc000..0xcfff -> super.read(address) // always RAM
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in 0xd000..0xdfff -> {
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// IO or CHAR ROM
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if(ioPort.charen)
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super.read(address)
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else
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chargen[address - 0xd000]
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}
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else -> {
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// 0xe000..0xffff, KERNAL or RAM
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if(ioPort.hiram)
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kernal[address - 0xe000]
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else
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super.read(address)
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}
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}
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return super.read(address)
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}
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}
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