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https://github.com/irmen/ksim65.git
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introduced separate Assembler class
This commit is contained in:
Irmen de Jong
parent
c619ddabf1
commit
deaf79fcc2
237
src/main/kotlin/razorvine/ksim65/Assembler.kt
Normal file
237
src/main/kotlin/razorvine/ksim65/Assembler.kt
Normal file
@ -0,0 +1,237 @@
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package razorvine.ksim65
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import razorvine.ksim65.components.Address
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import razorvine.ksim65.components.MemMappedComponent
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class Assembler(cpu: Cpu6502, val memory: MemMappedComponent, initialStartAddress: Address? = null) {
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companion object {
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fun parseRelativeToPC(relative: String, currentAddress: Int): Int {
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val rest = relative.substring(1).trim()
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if(rest.isNotEmpty()) {
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return when(rest[0]) {
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'-' -> currentAddress-parseNumber(rest.substring(1))
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'+' -> currentAddress+parseNumber(rest.substring(1))
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else -> throw NumberFormatException("invalid address syntax")
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}
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}
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return currentAddress
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}
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fun parseNumber(number: String, decimalFirst: Boolean = false): Int {
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val num = number.trim()
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if (num.isBlank()) return 0
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if (decimalFirst && num[0].isDigit()) return num.toInt(10)
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return when (num[0]) {
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'$' -> num.substring(1).trimStart().toInt(16)
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'#' -> num.substring(1).trimStart().toInt(10)
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'%' -> num.substring(1).trimStart().toInt(2)
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else -> num.toInt(16)
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}
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}
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}
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private var address = initialStartAddress ?: 0
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private var assembledSize = 0
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private val instructions by lazy {
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val instr = cpu.instructions.withIndex().associate {
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Pair(it.value.mnemonic, it.value.mode) to it.index
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}.toMutableMap()
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instr[Pair("nop", Cpu6502.AddrMode.Imp)] = 0xea
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instr.toMap()
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}
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class Result(val success: Boolean, val error: String, val startAddress: Address, val numBytes: Int)
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fun assemble(lines: Iterable<String>): Result {
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for(line in lines) {
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val result = assemble(line)
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if(!result.success)
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return result
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assembledSize += result.numBytes
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}
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return Result(true, "", address, assembledSize)
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}
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fun assemble(line: String): Result {
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/*
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The command is a line of the form:
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"<address> <instruction> [<arguments>]"
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" <instruction> [<arguments>]"
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"* = <address>"
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*/
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var args = line.trim().split(' ')
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if(args.isEmpty() || args.size == 1 && args[0] == "")
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return Result(true, "", address, 0)
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if(args[0].startsWith("*=") && args.size==1) {
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address = parseNumber(args[0].substring(2))
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return Result(true, "", address, 0)
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}
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else if(args[0] == "*" && args[1] == "=") {
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address = parseNumber(args[2])
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return Result(true, "", address, 0)
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} else {
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// line with an instruction, may be preceded by a 4 or 5 char address
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if(args[0].length == 4 || args[0].length==5) {
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if(args.size!=2 && args.size !=3)
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return Result(false, "syntax error", address, 0)
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address = parseNumber(args[0])
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args = args.drop(1)
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}
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}
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val instructionSize: Int
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val mnemonic = args[0].toLowerCase().trim()
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when (args.size) {
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1 -> {
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// implied or acc
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instructionSize = 1
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var instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Imp)]
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if (instruction == null) instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Acc)]
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if (instruction == null) return Result(false, "invalid instruction", this.address, 0)
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memory[address] = instruction.toShort()
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}
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2 -> {
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val arg = args[1]
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when {
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arg.startsWith('#') -> {
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// immediate
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Imm)] ?: return Result(false, "invalid instruction",
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this.address, 0)
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memory[address] = instruction.toShort()
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memory[address+1] = parseNumber(arg.substring(1), decimalFirst = true).toShort()
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instructionSize = 2
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}
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arg.startsWith("(") && arg.endsWith(",x)") -> {
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// indirect X
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val indAddress = try {
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parseNumber(arg.substring(1, arg.length-3))
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} catch (x: NumberFormatException) {
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return Result(false, "invalid instruction", this.address, 0)
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}
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.IzX)] ?: return Result(false, "invalid instruction",
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this.address, 0)
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memory[address] = instruction.toShort()
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memory[address+1] = indAddress.toShort()
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instructionSize = 2
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}
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arg.startsWith("(") && arg.endsWith("),y") -> {
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// indirect Y
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val indAddress = try {
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parseNumber(arg.substring(1, arg.length-3))
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} catch (x: NumberFormatException) {
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return Result(false, "invalid instruction", this.address, 0)
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}
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.IzY)] ?: return Result(false, "invalid instruction",
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this.address, 0)
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memory[address] = instruction.toShort()
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memory[address+1] = indAddress.toShort()
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instructionSize = 2
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}
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arg.endsWith(",x") -> {
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// indexed X or zpIndexed X
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val indAddress = try {
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parseNumber(arg.substring(1, arg.length-2))
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} catch (x: NumberFormatException) {
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return Result(false, "invalid instruction", this.address, 0)
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}
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instructionSize = if (indAddress <= 255) {
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.ZpX)] ?: return Result(false, "invalid instruction",
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this.address, 0)
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memory[address] = instruction.toShort()
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memory[address+1] = indAddress.toShort()
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2
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} else {
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.AbsX)] ?: return Result(false, "invalid instruction",
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this.address, 0)
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memory[address] = instruction.toShort()
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memory[address+1] = (indAddress and 255).toShort()
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memory[address+2] = (indAddress ushr 8).toShort()
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3
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}
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}
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arg.endsWith(",y") -> {
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// indexed Y or zpIndexed Y
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val indAddress = try {
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parseNumber(arg.substring(1, arg.length-2))
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} catch (x: NumberFormatException) {
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return Result(false, "invalid instruction", this.address, 0)
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}
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instructionSize = if (indAddress <= 255) {
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.ZpY)] ?: return Result(false, "invalid instruction",
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this.address, 0)
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memory[address] = instruction.toShort()
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memory[address+1] = indAddress.toShort()
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2
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} else {
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.AbsY)] ?: return Result(false, "invalid instruction",
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this.address, 0)
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memory[address] = instruction.toShort()
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memory[address+1] = (indAddress and 255).toShort()
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memory[address+2] = (indAddress ushr 8).toShort()
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3
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}
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}
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arg.endsWith(")") -> {
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// indirect (jmp)
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val indAddress = try {
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parseNumber(arg.substring(1, arg.length-1))
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} catch (x: NumberFormatException) {
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return Result(false, "invalid instruction", this.address, 0)
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}
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Ind)]
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?: return Result(false, "invalid instruction", this.address, 0)
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memory[address] = instruction.toShort()
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memory[address+1] = (indAddress and 255).toShort()
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memory[address+2] = (indAddress ushr 8).toShort()
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instructionSize = 3
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}
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else -> {
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val instr = instructions[Pair(mnemonic, Cpu6502.AddrMode.Rel)]
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if (instr != null) {
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// relative address
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val rel = try {
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parseRelativeToPC(arg, address)
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} catch (x: NumberFormatException) {
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return Result(false, "invalid numeral", this.address, 0)
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}
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memory[address] = instr.toShort()
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memory[address+1] = (rel-address-2 and 255).toShort()
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instructionSize = 2
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} else {
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// absolute or absZp
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val absAddress = try {
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if(arg.startsWith('*')) parseRelativeToPC(arg, address) else parseNumber(arg)
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} catch (x: NumberFormatException) {
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return Result(false, "invalid numeral", this.address, 0)
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}
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val zpInstruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Zp)]
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instructionSize = if (absAddress <= 255 && zpInstruction != null) {
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memory[address] = zpInstruction.toShort()
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memory[address+1] = absAddress.toShort()
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2
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} else {
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val absInstr = instructions[Pair(mnemonic, Cpu6502.AddrMode.Abs)] ?: return Result(false, "invalid instruction",
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this.address, 0)
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memory[address] = absInstr.toShort()
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memory[address+1] = (absAddress and 255).toShort()
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memory[address+2] = (absAddress ushr 8).toShort()
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3
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}
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}
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}
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}
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}
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else ->
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return Result(false, "syntax error", this.address, 0)
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}
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return Result(true, "", this.address, instructionSize)
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}
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}
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@ -64,4 +64,8 @@ open class Bus {
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it[address-it.startAddress] = data
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}
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}
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fun memoryComponentFor(address: Address) =
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memComponents.first { it is MemoryComponent && address >= it.startAddress && address <= it.endAddress } as MemoryComponent
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}
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@ -4,14 +4,6 @@ import kotlin.math.max
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class Monitor(val bus: Bus, val cpu: Cpu6502) {
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private val instructions by lazy {
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val instr = cpu.instructions.withIndex().associate {
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Pair(it.value.mnemonic, it.value.mode) to it.index
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}.toMutableMap()
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instr[Pair("nop", Cpu6502.AddrMode.Imp)] = 0xea
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instr.toMap()
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}
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private val disassembler = Disassembler(cpu)
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fun command(command: String): IVirtualMachine.MonitorCmdResult {
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@ -26,9 +18,9 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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val parts = command.substring(1).trim().split(' ')
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if (parts.size != 3) IVirtualMachine.MonitorCmdResult("?syntax error", command, false)
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else {
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val start = parseNumber(parts[0])
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val end = parseNumber(parts[1])
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val value = parseNumber(parts[2]).toShort()
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val start = Assembler.parseNumber(parts[0])
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val end = Assembler.parseNumber(parts[1])
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val value = Assembler.parseNumber(parts[2]).toShort()
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for (addr in start..end) {
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bus.write(addr, value)
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}
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@ -37,8 +29,8 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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}
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'm' -> {
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val addresses = command.substring(1).trim().split(' ')
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val start = parseNumber(addresses[0])
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val end = if (addresses.size > 1) parseNumber(addresses[1]) else start+1
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val start = Assembler.parseNumber(addresses[0])
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val end = if (addresses.size > 1) Assembler.parseNumber(addresses[1]) else start+1
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val result = mutableListOf<String>()
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for (addr in start until end step 16) {
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result.add("m$${hexW(addr)} "+(0..15).joinToString(" ") { hexB(bus.read(addr+it)) }+" "+(0..15).joinToString("") {
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@ -51,15 +43,15 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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}
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'p' -> {
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val numbers = command.substring(1).trim().split(' ')
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val address = parseNumber(numbers[0])
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val values = numbers.drop(1).map { parseNumber(it) }
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val address = Assembler.parseNumber(numbers[0])
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val values = numbers.drop(1).map { Assembler.parseNumber(it) }
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values.forEachIndexed { index, i -> bus.write(address+index, i.toShort()) }
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IVirtualMachine.MonitorCmdResult("ok", "", true)
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}
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'i' -> {
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val addresses = command.substring(1).trim().split(' ')
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val start = parseNumber(addresses[0])
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val end = if (addresses.size > 1) parseNumber(addresses[1]) else start+1
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val start = Assembler.parseNumber(addresses[0])
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val end = if (addresses.size > 1) Assembler.parseNumber(addresses[1]) else start+1
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val result = mutableListOf<String>()
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for (addr in start until end step 64) {
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result.add("i$${hexW(addr)} "+(0..63).joinToString("") {
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@ -71,33 +63,41 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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IVirtualMachine.MonitorCmdResult(result.joinToString("\n"), "", true)
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}
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'$' -> {
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val number = parseNumber(command)
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val number = Assembler.parseNumber(command)
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val output = "$${hexW(number)} #$number %${number.toString(2)}"
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IVirtualMachine.MonitorCmdResult(output, "", true)
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}
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'#' -> {
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val number = parseNumber(command)
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val number = Assembler.parseNumber(command)
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val output = "$${hexW(number)} #$number %${number.toString(2)}"
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IVirtualMachine.MonitorCmdResult(output, "", true)
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}
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'%' -> {
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val number = parseNumber(command)
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val number = Assembler.parseNumber(command)
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val output = "$${hexW(number)} #$number %${number.toString(2)}"
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IVirtualMachine.MonitorCmdResult(output, "", true)
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}
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'g' -> {
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val address = parseNumber(command.substring(1))
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val address = Assembler.parseNumber(command.substring(1))
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cpu.regPC = address
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IVirtualMachine.MonitorCmdResult("", "", true)
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}
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'a' -> {
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val parts = command.substring(1).trim().split(' ')
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assemble(command, parts)
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val address = 0 // TODO parse from line
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val assembler = Assembler(cpu, bus.memoryComponentFor(address), address)
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val result = assembler.assemble(command.substring(1).trimStart())
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if(result.success) {
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val memory = (result.startAddress..result.startAddress+result.numBytes).map { bus[it] }.toTypedArray()
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val d = disassembler.disassembleOneInstruction(memory, 0, result.startAddress)
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IVirtualMachine.MonitorCmdResult(d.first, "a$${hexW(result.startAddress+result.numBytes)} ", false)
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}
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else
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IVirtualMachine.MonitorCmdResult(result.error, command, false)
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}
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'd' -> {
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val addresses = command.substring(1).trim().split(' ')
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val start = parseNumber(addresses[0])
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val end = if (addresses.size > 1) parseNumber(addresses[1]) else start
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val start = Assembler.parseNumber(addresses[0])
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val end = if (addresses.size > 1) Assembler.parseNumber(addresses[1]) else start
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val memory = (start .. max(0xffff, end+3)).map {bus[it]}.toTypedArray()
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val disassem = disassembler.disassemble(memory, 0 .. end-start, start)
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IVirtualMachine.MonitorCmdResult(disassem.first.joinToString("\n") { "d$it" }, "d$${hexW(disassem.second)}", false)
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@ -107,164 +107,4 @@ class Monitor(val bus: Bus, val cpu: Cpu6502) {
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}
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}
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}
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private fun assemble(command: String, parts: List<String>): IVirtualMachine.MonitorCmdResult {
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if (parts.size < 2) return IVirtualMachine.MonitorCmdResult("done", "", false)
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val address = parseNumber(parts[0])
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val mnemonic = parts[1].toLowerCase()
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when (parts.size) {
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2 -> {
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// implied or acc
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var instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Imp)]
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if (instruction == null) instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Acc)]
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if (instruction == null) return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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bus.write(address, instruction.toShort())
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}
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3 -> {
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val arg = parts[2]
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when {
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arg.startsWith('#') -> {
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// immediate
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Imm)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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bus.write(address, instruction.toShort())
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bus.write(address+1, parseNumber(arg.substring(1), decimalFirst = true).toShort())
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}
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arg.startsWith("(") && arg.endsWith(",x)") -> {
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// indirect X
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val indAddress = try {
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parseNumber(arg.substring(1, arg.length-3))
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} catch (x: NumberFormatException) {
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return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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}
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.IzX)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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bus.write(address, instruction.toShort())
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bus.write(address+1, indAddress.toShort())
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}
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arg.startsWith("(") && arg.endsWith("),y") -> {
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// indirect Y
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val indAddress = try {
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parseNumber(arg.substring(1, arg.length-3))
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} catch (x: NumberFormatException) {
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return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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}
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.IzY)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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bus.write(address, instruction.toShort())
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bus.write(address+1, indAddress.toShort())
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}
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arg.endsWith(",x") -> {
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// indexed X or zpIndexed X
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val indAddress = try {
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parseNumber(arg.substring(1, arg.length-2))
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} catch (x: NumberFormatException) {
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return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
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}
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if (indAddress <= 255) {
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val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.ZpX)] ?: return IVirtualMachine.MonitorCmdResult(
|
||||
"?invalid instruction", command, false)
|
||||
bus.write(address, instruction.toShort())
|
||||
bus.write(address+1, indAddress.toShort())
|
||||
} else {
|
||||
val instruction =
|
||||
instructions[Pair(mnemonic, Cpu6502.AddrMode.AbsX)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
|
||||
bus.write(address, instruction.toShort())
|
||||
bus.write(address+1, (indAddress and 255).toShort())
|
||||
bus.write(address+2, (indAddress ushr 8).toShort())
|
||||
}
|
||||
}
|
||||
arg.endsWith(",y") -> {
|
||||
// indexed Y or zpIndexed Y
|
||||
val indAddress = try {
|
||||
parseNumber(arg.substring(1, arg.length-2))
|
||||
} catch (x: NumberFormatException) {
|
||||
return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
|
||||
}
|
||||
if (indAddress <= 255) {
|
||||
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.ZpY)] ?: return IVirtualMachine.MonitorCmdResult(
|
||||
"?invalid instruction", command, false)
|
||||
bus.write(address, instruction.toShort())
|
||||
bus.write(address+1, indAddress.toShort())
|
||||
} else {
|
||||
val instruction =
|
||||
instructions[Pair(mnemonic, Cpu6502.AddrMode.AbsY)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
|
||||
bus.write(address, instruction.toShort())
|
||||
bus.write(address+1, (indAddress and 255).toShort())
|
||||
bus.write(address+2, (indAddress ushr 8).toShort())
|
||||
}
|
||||
}
|
||||
arg.endsWith(")") -> {
|
||||
// indirect (jmp)
|
||||
val indAddress = try {
|
||||
parseNumber(arg.substring(1, arg.length-1))
|
||||
} catch (x: NumberFormatException) {
|
||||
return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
|
||||
}
|
||||
val instruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Ind)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
|
||||
bus.write(address, instruction.toShort())
|
||||
bus.write(address+1, (indAddress and 255).toShort())
|
||||
bus.write(address+2, (indAddress ushr 8).toShort())
|
||||
}
|
||||
else -> {
|
||||
val instr = instructions[Pair(mnemonic, Cpu6502.AddrMode.Rel)]
|
||||
if (instr != null) {
|
||||
// relative address
|
||||
val rel = try {
|
||||
parseRelativeToPC(arg, address)
|
||||
} catch (x: NumberFormatException) {
|
||||
return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
|
||||
}
|
||||
bus.write(address, instr.toShort())
|
||||
bus.write(address+1, (rel-address-2 and 255).toShort())
|
||||
} else {
|
||||
// absolute or absZp
|
||||
val absAddress = try {
|
||||
if(arg.startsWith('*')) parseRelativeToPC(arg, address) else parseNumber(arg)
|
||||
} catch (x: NumberFormatException) {
|
||||
return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
|
||||
}
|
||||
val zpInstruction = instructions[Pair(mnemonic, Cpu6502.AddrMode.Zp)]
|
||||
if (absAddress <= 255 && zpInstruction!=null) {
|
||||
bus.write(address, zpInstruction.toShort())
|
||||
bus.write(address+1, absAddress.toShort())
|
||||
} else {
|
||||
val absInstr = instructions[Pair(mnemonic, Cpu6502.AddrMode.Abs)] ?: return IVirtualMachine.MonitorCmdResult("?invalid instruction", command, false)
|
||||
bus.write(address, absInstr.toShort())
|
||||
bus.write(address+1, (absAddress and 255).toShort())
|
||||
bus.write(address+2, (absAddress ushr 8).toShort())
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else -> return IVirtualMachine.MonitorCmdResult("?syntax error", command, false)
|
||||
}
|
||||
|
||||
val memory = listOf(bus[address], bus[address+1], bus[address+2]).toTypedArray()
|
||||
val disassem = disassembler.disassembleOneInstruction(memory, 0, address)
|
||||
return IVirtualMachine.MonitorCmdResult(disassem.first, "a$${hexW(disassem.second + address)} ", false)
|
||||
}
|
||||
|
||||
private fun parseRelativeToPC(relative: String, currentAddress: Int): Int {
|
||||
val rest = relative.substring(1).trim()
|
||||
if(rest.isNotEmpty()) {
|
||||
return when(rest[0]) {
|
||||
'-' -> currentAddress-parseNumber(rest.substring(1))
|
||||
'+' -> currentAddress+parseNumber(rest.substring(1))
|
||||
else -> throw Cpu6502.InstructionError("invalid address syntax")
|
||||
}
|
||||
}
|
||||
return currentAddress
|
||||
}
|
||||
|
||||
private fun parseNumber(number: String, decimalFirst: Boolean = false): Int {
|
||||
val num = number.trim()
|
||||
if (num.isBlank()) return 0
|
||||
if (decimalFirst && num[0].isDigit()) return num.toInt(10)
|
||||
return when (num[0]) {
|
||||
'$' -> num.substring(1).trimStart().toInt(16)
|
||||
'#' -> num.substring(1).trimStart().toInt(10)
|
||||
'%' -> num.substring(1).trimStart().toInt(2)
|
||||
else -> num.toInt(16)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
43
src/test/kotlin/TestAssembler.kt
Normal file
43
src/test/kotlin/TestAssembler.kt
Normal file
@ -0,0 +1,43 @@
|
||||
import razorvine.ksim65.*
|
||||
import razorvine.ksim65.components.Ram
|
||||
import kotlin.test.*
|
||||
|
||||
|
||||
class TestAssembler {
|
||||
|
||||
@Test
|
||||
fun testAssembleSingleInstruction() {
|
||||
val cpu = Cpu6502()
|
||||
val ram = Ram(0, 0xffff)
|
||||
val assembler = Assembler(cpu, ram)
|
||||
|
||||
val result = assembler.assemble("${'$'}c000 jmp ${'$'}ea31")
|
||||
assertTrue(result.success)
|
||||
assertEquals("", result.error)
|
||||
assertEquals(0xc000, result.startAddress)
|
||||
assertEquals(3, result.numBytes)
|
||||
assertEquals(0x4c, ram[0xc000])
|
||||
assertEquals(0x31, ram[0xc001])
|
||||
assertEquals(0xea, ram[0xc002])
|
||||
}
|
||||
|
||||
@Test
|
||||
fun testAssembleMulti() {
|
||||
val cpu = Cpu6502()
|
||||
val ram = Ram(0, 0xffff)
|
||||
val assembler = Assembler(cpu, ram)
|
||||
val result = assembler.assemble("""
|
||||
*=${'$'}a2b3
|
||||
nop
|
||||
jmp ${'$'}ea31
|
||||
bne *-2
|
||||
""".lines())
|
||||
assertEquals("", result.error)
|
||||
assertTrue(result.success)
|
||||
assertEquals(0xa2b3, result.startAddress)
|
||||
assertEquals(6, result.numBytes)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user