mirror of
https://github.com/irmen/ksim65.git
synced 2024-06-06 22:29:33 +00:00
some more cleanup
This commit is contained in:
Irmen de Jong
parent
e40456d7e4
commit
e5e41d053e
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@ -70,8 +70,8 @@ private class BitmapScreenPanel : JPanel() {
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image = gd.createCompatibleImage(ScreenDefs.SCREEN_WIDTH, ScreenDefs.SCREEN_HEIGHT, Transparency.OPAQUE)
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g2d = image.graphics as Graphics2D
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val size =
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Dimension((image.width*ScreenDefs.DISPLAY_PIXEL_SCALING).toInt(), (image.height*ScreenDefs.DISPLAY_PIXEL_SCALING).toInt())
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val size = Dimension((image.width*ScreenDefs.DISPLAY_PIXEL_SCALING).toInt(),
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(image.height*ScreenDefs.DISPLAY_PIXEL_SCALING).toInt())
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minimumSize = size
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maximumSize = size
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preferredSize = size
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@ -26,7 +26,6 @@ open class Cpu6502 : BusComponent() {
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const val NMI_vector = 0xfffa
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const val RESET_vector = 0xfffc
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const val IRQ_vector = 0xfffe
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const val resetCycles = 8
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}
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class StatusRegister(var C: Boolean = false, var Z: Boolean = false, var I: Boolean = false, var D: Boolean = false,
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@ -73,15 +72,17 @@ open class Cpu6502 : BusComponent() {
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class State(val A: UByte, val X: UByte, val Y: UByte, val SP: Address, val P: StatusRegister, val PC: Address, val cycles: Long) {
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override fun toString(): String {
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return "cycle:$cycles - pc=${hexW(PC)} "+"A=${hexB(A)} "+"X=${hexB(X)} "+"Y=${hexB(Y)} "+"SP=${hexB(
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SP)} "+" n="+(if (P.N) "1" else "0")+" v="+(if (P.V) "1" else "0")+" b="+(if (P.B) "1" else "0")+" d="+(if (P.D) "1" else "0")+" i="+(if (P.I) "1" else "0")+" z="+(if (P.Z) "1" else "0")+" c="+(if (P.C) "1" else "0")
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return "cycle:$cycles - pc=${hexW(PC)} "+"A=${hexB(A)} "+"X=${hexB(X)} "+"Y=${hexB(Y)} "+
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"SP=${hexB(SP)} "+" n="+(if (P.N) "1" else "0")+" v="+(if (P.V) "1" else "0")+
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" b="+(if (P.B) "1" else "0")+" d="+(if (P.D) "1" else "0")+" i="+(if (P.I) "1" else "0")+
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" z="+(if (P.Z) "1" else "0")+" c="+(if (P.C) "1" else "0")
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}
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}
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enum class AddrMode {
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Imp, Acc, Imm, Zp, Zpr, // special addressing mode used by the 65C02
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ZpX, ZpY, Rel, Abs, AbsX, AbsY, Ind, IzX, IzY, Izp, // special addressing mode used by the 65C02
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IaX, // special addressing mode used by the 65C02
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Imp, Acc, Imm, Zp, ZpX, ZpY, Rel, Abs, AbsX, AbsY, Ind, IzX, IzY,
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// modes used only by the 65C02:
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Zpr, Izp, IaX
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}
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class Instruction(val mnemonic: String, val mode: AddrMode, val cycles: Int)
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@ -97,9 +98,7 @@ open class Cpu6502 : BusComponent() {
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var instrCycles: Int = 0
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protected set
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protected lateinit var currentInstruction: Instruction
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val currentMnemonic: String
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get() = currentInstruction.mnemonic
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lateinit var currentInstruction: Instruction
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val averageSpeedKhzSinceReset: Double
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get() = totalCycles.toDouble()/(System.nanoTime()-resetTime)*1_000_000
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@ -125,9 +124,7 @@ open class Cpu6502 : BusComponent() {
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private val breakpoints = mutableMapOf<Address, BreakpointHandler>()
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fun addBreakpoint(address: Address, handler: BreakpointHandler) {
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breakpoints[address] = handler
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}
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fun addBreakpoint(address: Address, handler: BreakpointHandler) { breakpoints[address] = handler }
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fun removeBreakpoint(address: Address) = breakpoints.remove(address)
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@ -136,13 +133,11 @@ open class Cpu6502 : BusComponent() {
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fun disassemble(memory: Array<UByte>, baseAddress: Address, from: Address, to: Address): Pair<List<String>, Address> {
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var location = from
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val result = mutableListOf<String>()
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while (location <= to) {
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val dis = disassembleOneInstruction(memory, location, baseAddress)
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result.add(dis.first)
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location += dis.second
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}
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return Pair(result, location)
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}
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@ -170,7 +165,7 @@ open class Cpu6502 : BusComponent() {
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)}", 2)
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}
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AddrMode.Zpr -> {
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// addressing mode used by the 65C02, put here for convenience
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[location+1]
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val rel = memory[location+2]
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val target = if (rel <= 0x7f) location+3+rel+baseAddress
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@ -178,12 +173,12 @@ open class Cpu6502 : BusComponent() {
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Pair(line+"${hexB(zpAddr)} ${hexB(rel)} $spacing3 ${opcode.mnemonic} \$${hexB(zpAddr)}, \$${hexW(target, true)}", 3)
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}
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AddrMode.Izp -> {
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// addressing mode used by the 65C02, put here for convenience
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val zpAddr = memory[location+1]
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Pair(line+"${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$(${hexB(zpAddr)})", 2)
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}
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AddrMode.IaX -> {
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// addressing mode used by the 65C02, put here for convenience
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// addressing mode used by the 65C02, put here for convenience rather than the subclass
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val lo = memory[location+1]
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val hi = memory[location+2]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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@ -254,7 +249,7 @@ open class Cpu6502 : BusComponent() {
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regA = 0
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regX = 0
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regY = 0
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instrCycles = resetCycles // a reset takes time as well
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instrCycles = 8 // a reset takes 8 clock cycles
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currentOpcode = 0
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currentInstruction = instructions[0]
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totalCycles = 0
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@ -15,12 +15,6 @@ class Cpu65C02 : Cpu6502() {
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var waiting: Wait = Wait.Normal
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companion object {
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const val NMI_vector = Cpu6502.NMI_vector
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const val RESET_vector = Cpu6502.RESET_vector
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const val IRQ_vector = Cpu6502.NMI_vector
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const val resetCycles = Cpu6502.resetCycles
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}
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/**
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* Process once clock cycle in the cpu
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@ -276,7 +276,7 @@ class Test6502 : TestCommon6502() {
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writeMem(memory, 0, listOf(0x6c, 0xff, 0x00))
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mpu.step()
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assertEquals(0x6c00, mpu.regPC)
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assertEquals((5+ Cpu6502.resetCycles).toLong(), mpu.totalCycles)
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assertEquals(13L, mpu.totalCycles)
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}
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// ORA Indexed, Indirect (Y)
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@ -65,7 +65,7 @@ class Test65C02 : TestCommon6502() {
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memory[0xABCD] = 0x00
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(13L, mpu.totalCycles)
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assertEquals(0x00, mpu.regA)
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assertFalse(mpu.regP.C)
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assertFalse(mpu.regP.N)
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@ -83,7 +83,7 @@ class Test65C02 : TestCommon6502() {
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memory[0xABCD] = 0x00
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(13L, mpu.totalCycles)
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assertEquals(0x01, mpu.regA)
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assertFalse(mpu.regP.N)
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assertFalse(mpu.regP.Z)
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@ -100,7 +100,7 @@ class Test65C02 : TestCommon6502() {
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memory[0xABCD] = 0xFE
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(13L, mpu.totalCycles)
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assertEquals(0xFF, mpu.regA)
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assertTrue(mpu.regP.N)
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assertFalse(mpu.regP.C)
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@ -117,7 +117,7 @@ class Test65C02 : TestCommon6502() {
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memory[0xABCD] = 0xFF
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(13L, mpu.totalCycles)
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assertEquals(0x01, mpu.regA)
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assertTrue(mpu.regP.C)
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assertFalse(mpu.regP.N)
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@ -212,7 +212,7 @@ class Test65C02 : TestCommon6502() {
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memory[0xABCD] = 0x00
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(13L, mpu.totalCycles)
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assertEquals(0x00, mpu.regA)
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assertTrue(mpu.regP.Z)
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assertFalse(mpu.regP.N)
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@ -228,7 +228,7 @@ class Test65C02 : TestCommon6502() {
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memory[0xABCD] = 0xAA
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(13L, mpu.totalCycles)
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assertEquals(0xAA, mpu.regA)
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assertTrue(mpu.regP.N)
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assertFalse(mpu.regP.Z)
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@ -246,7 +246,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0xFF
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mpu.step()
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assertTrue(mpu.regP.N)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x0003, mpu.regPC)
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}
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@ -260,7 +260,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0xFF
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mpu.step()
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assertFalse(mpu.regP.N)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x0003, mpu.regPC)
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}
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@ -274,7 +274,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0xFF
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mpu.step()
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assertTrue(mpu.regP.V)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x0003, mpu.regPC)
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}
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@ -288,7 +288,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0xFF
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mpu.step()
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assertFalse(mpu.regP.V)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x0003, mpu.regPC)
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}
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@ -304,7 +304,7 @@ class Test65C02 : TestCommon6502() {
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assertTrue(mpu.regP.Z)
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assertEquals(0x01, mpu.regA)
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assertEquals(0x00, memory[0xFEED])
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x0003, mpu.regPC)
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}
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@ -320,7 +320,7 @@ class Test65C02 : TestCommon6502() {
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assertFalse(mpu.regP.Z) // result of AND is non-zero
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assertEquals(0x01, mpu.regA)
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assertEquals(0x01, memory[0xFEED])
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x0003, mpu.regPC)
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}
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@ -336,7 +336,7 @@ class Test65C02 : TestCommon6502() {
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assertTrue(mpu.regP.Z) // result of AND is zero
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assertEquals(0x01, mpu.regA)
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assertEquals(0x00, memory[0xFEED])
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x0003, mpu.regPC)
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}
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@ -353,7 +353,7 @@ class Test65C02 : TestCommon6502() {
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assertTrue(mpu.regP.N)
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assertTrue(mpu.regP.V)
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assertEquals(0x00, mpu.regA)
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assertEquals(2 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(10, mpu.totalCycles)
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assertEquals(0x02, mpu.regPC)
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}
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@ -366,7 +366,7 @@ class Test65C02 : TestCommon6502() {
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mpu.step()
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assertTrue(mpu.regP.Z)
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assertEquals(0x01, mpu.regA)
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assertEquals(2 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(10, mpu.totalCycles)
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assertEquals(0x02, mpu.regPC)
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}
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@ -379,7 +379,7 @@ class Test65C02 : TestCommon6502() {
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mpu.step()
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assertFalse(mpu.regP.Z) // result of AND is non-zero
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assertEquals(0x01, mpu.regA)
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assertEquals(2 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(10, mpu.totalCycles)
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assertEquals(0x02, mpu.regPC)
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}
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@ -392,7 +392,7 @@ class Test65C02 : TestCommon6502() {
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mpu.step()
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assertTrue(mpu.regP.Z) // result of AND is zero
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assertEquals(0x01, mpu.regA)
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assertEquals(2 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(10, mpu.totalCycles)
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assertEquals(0x02, mpu.regPC)
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}
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@ -408,7 +408,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0xFF
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertTrue(mpu.regP.N)
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}
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@ -422,7 +422,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0xFF
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertFalse(mpu.regP.N)
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}
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@ -436,7 +436,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0xFF
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertTrue(mpu.regP.V)
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}
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@ -450,7 +450,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0xFF
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertFalse(mpu.regP.V)
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}
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@ -465,7 +465,7 @@ class Test65C02 : TestCommon6502() {
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mpu.step()
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assertTrue(mpu.regP.Z)
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assertEquals(0x0002, mpu.regPC)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x01, mpu.regA)
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assertEquals(0x00, memory[0x0010 + mpu.regX])
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}
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@ -481,7 +481,7 @@ class Test65C02 : TestCommon6502() {
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mpu.step()
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assertFalse(mpu.regP.Z) // result of AND is non-zero
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assertEquals(0x0002, mpu.regPC)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertEquals(0x01, mpu.regA)
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assertEquals(0x01, memory[0x0010 + mpu.regX])
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}
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@ -496,7 +496,7 @@ class Test65C02 : TestCommon6502() {
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mpu.regA = 0x01
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(12, mpu.totalCycles)
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assertTrue(mpu.regP.Z) // result of AND is zero
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assertEquals(0x01, mpu.regA)
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assertEquals(0x00, memory[0x0010 + mpu.regX])
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@ -527,7 +527,7 @@ class Test65C02 : TestCommon6502() {
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memory[0xABCD] = 0x42
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(13L, mpu.totalCycles)
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assertEquals(0x42, mpu.regA)
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assertTrue(mpu.regP.Z)
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assertFalse(mpu.regP.N)
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@ -543,7 +543,7 @@ class Test65C02 : TestCommon6502() {
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memory[0xABCD] = 0x42
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x43, mpu.regA)
|
||||
assertFalse(mpu.regP.Z)
|
||||
assertFalse(mpu.regP.N)
|
||||
|
|
@ -561,7 +561,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xABCD] = 0xFF
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(0xFF, memory[0xABCD])
|
||||
assertTrue(mpu.regP.Z)
|
||||
|
|
@ -577,7 +577,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xABCD] = 0xFF
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(0xFF, memory[0xABCD])
|
||||
assertTrue(mpu.regP.N)
|
||||
|
|
@ -628,7 +628,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0, listOf(0x6c, 0xFF, 0x10))
|
||||
mpu.step()
|
||||
assertEquals(0xABCD, mpu.regPC)
|
||||
assertEquals(6 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(14, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// JMP Indirect Absolute X-Indexed
|
||||
|
|
@ -642,7 +642,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0xABCF, listOf(0x34, 0x12))
|
||||
mpu.step()
|
||||
assertEquals(0x1234, mpu.regPC)
|
||||
assertEquals(6 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(14, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// LDA Zero Page, Indirect
|
||||
|
|
@ -657,7 +657,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xABCD] = 0x80
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x80, mpu.regA)
|
||||
assertTrue(mpu.regP.N)
|
||||
assertFalse(mpu.regP.Z)
|
||||
|
|
@ -673,7 +673,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xABCD] = 0x00
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertTrue(mpu.regP.Z)
|
||||
assertFalse(mpu.regP.N)
|
||||
|
|
@ -694,7 +694,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xABCD] = 0x00
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertTrue(mpu.regP.Z)
|
||||
}
|
||||
|
|
@ -710,7 +710,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xABCD] = 0x82
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x83, mpu.regA)
|
||||
assertTrue(mpu.regP.N)
|
||||
assertFalse(mpu.regP.Z)
|
||||
|
|
@ -729,7 +729,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0xAB, mpu.regX)
|
||||
assertEquals(0xAB, memory[0x01FF])
|
||||
assertEquals(0xFE, mpu.regSP)
|
||||
assertEquals(3 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// PHY
|
||||
|
|
@ -745,7 +745,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0xAB, mpu.regY)
|
||||
assertEquals(0xAB, memory[0x01FF])
|
||||
assertEquals(0xFE, mpu.regSP)
|
||||
assertEquals(3 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// PLX
|
||||
|
|
@ -760,7 +760,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0x0001, mpu.regPC)
|
||||
assertEquals(0xAB, mpu.regX)
|
||||
assertEquals(0xFF, mpu.regSP)
|
||||
assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(12, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// PLY
|
||||
|
|
@ -775,7 +775,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0x0001, mpu.regPC)
|
||||
assertEquals(0xAB, mpu.regY)
|
||||
assertEquals(0xFF, mpu.regSP)
|
||||
assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(12, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// RMB0
|
||||
|
|
@ -787,7 +787,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x07, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b11111110
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -812,7 +812,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x17, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b11111101
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -837,7 +837,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x27, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b11111011.toShort()
|
||||
assertEquals(expected, memory[0x0043])
|
||||
|
||||
|
|
@ -863,7 +863,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x37, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b11110111
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -888,7 +888,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x47, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b11101111
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -913,7 +913,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x57, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b11011111
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -938,7 +938,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x67, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b10111111.toShort()
|
||||
assertEquals(expected, memory[0x0043])
|
||||
}
|
||||
|
|
@ -963,7 +963,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x77, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b01111111
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
|
||||
|
|
@ -994,7 +994,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xFEED] = 0x00
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0xFF, memory[0xFEED])
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
|
|
@ -1012,7 +1012,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xFEED] = 0xFF
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x00, memory[0xFEED])
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
|
|
@ -1027,7 +1027,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x87, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b00000001.toShort()
|
||||
assertEquals(expected, memory[0x0043])
|
||||
}
|
||||
|
|
@ -1052,7 +1052,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x97, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b00000010
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -1077,7 +1077,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0xA7, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b00000100
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
|
||||
|
|
@ -1103,7 +1103,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0xB7, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b00001000
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
|
||||
|
|
@ -1129,7 +1129,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0xC7, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b00010000
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
|
||||
|
|
@ -1155,7 +1155,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0xD7, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b00100000
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -1180,7 +1180,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0xE7, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b01000000
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -1205,7 +1205,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0xF7, 0x43))
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
val expected = 0b10000000
|
||||
assertEquals(expected, memory[0x0043].toInt())
|
||||
}
|
||||
|
|
@ -1235,7 +1235,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xFEED] = 0x00
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertFalse(mpu.regP.N)
|
||||
assertTrue(mpu.regP.C)
|
||||
|
|
@ -1254,7 +1254,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xFEED] = 0x01
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertFalse(mpu.regP.N)
|
||||
assertTrue(mpu.regP.C)
|
||||
|
|
@ -1273,7 +1273,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xFEED] = 0x00
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertFalse(mpu.regP.N)
|
||||
assertTrue(mpu.regP.C)
|
||||
|
|
@ -1292,7 +1292,7 @@ class Test65C02 : TestCommon6502() {
|
|||
memory[0xFEED] = 0x02
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
assertEquals(0x04, mpu.regA)
|
||||
assertFalse(mpu.regP.N)
|
||||
assertFalse(mpu.regP.Z)
|
||||
|
|
@ -1311,7 +1311,7 @@ class Test65C02 : TestCommon6502() {
|
|||
mpu.step()
|
||||
assertEquals(0x00, memory[0x0032])
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(3 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// STZ Zero Page, X-Indexed
|
||||
|
|
@ -1326,7 +1326,7 @@ class Test65C02 : TestCommon6502() {
|
|||
mpu.step()
|
||||
assertEquals(0x00, memory[0x0032])
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(12, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// STZ Absolute
|
||||
|
|
@ -1340,7 +1340,7 @@ class Test65C02 : TestCommon6502() {
|
|||
mpu.step()
|
||||
assertEquals(0x00, memory[0xFEED])
|
||||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(4 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(12, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// STZ Absolute, X-Indexed
|
||||
|
|
@ -1356,7 +1356,7 @@ class Test65C02 : TestCommon6502() {
|
|||
mpu.step()
|
||||
assertEquals(0x00, memory[0xFEED])
|
||||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// TSB Zero Page
|
||||
|
|
@ -1372,7 +1372,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0xF0, memory[0x00BB])
|
||||
assertFalse(mpu.regP.Z)
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
}
|
||||
|
||||
@Test
|
||||
|
|
@ -1386,7 +1386,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0xE0, memory[0x00BB])
|
||||
assertTrue(mpu.regP.Z)
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// TSB Absolute
|
||||
|
|
@ -1402,7 +1402,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0xF0, memory[0xFEED])
|
||||
assertFalse(mpu.regP.Z)
|
||||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(6 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(14, mpu.totalCycles)
|
||||
}
|
||||
|
||||
@Test
|
||||
|
|
@ -1416,7 +1416,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0xE0, memory[0xFEED])
|
||||
assertTrue(mpu.regP.Z)
|
||||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(6 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(14, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// TRB Zero Page
|
||||
|
|
@ -1432,7 +1432,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0x80, memory[0x00BB])
|
||||
assertFalse(mpu.regP.Z)
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
}
|
||||
|
||||
@Test
|
||||
|
|
@ -1446,7 +1446,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0x80, memory[0x00BB])
|
||||
assertTrue(mpu.regP.Z)
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(13L, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// TRB Absolute
|
||||
|
|
@ -1462,7 +1462,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0x80, memory[0xFEED])
|
||||
assertFalse(mpu.regP.Z)
|
||||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(6 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(14, mpu.totalCycles)
|
||||
}
|
||||
|
||||
@Test
|
||||
|
|
@ -1476,7 +1476,7 @@ class Test65C02 : TestCommon6502() {
|
|||
assertEquals(0x80, memory[0xFEED])
|
||||
assertTrue(mpu.regP.Z)
|
||||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(6 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(14, mpu.totalCycles)
|
||||
}
|
||||
|
||||
@Test
|
||||
|
|
@ -1518,7 +1518,7 @@ class Test65C02 : TestCommon6502() {
|
|||
writeMem(memory, 0x0000, listOf(0x80, 0x10))
|
||||
mpu.step()
|
||||
assertEquals(0x12, mpu.regPC)
|
||||
assertEquals(3 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11, mpu.totalCycles)
|
||||
}
|
||||
|
||||
@Test
|
||||
|
|
@ -1528,7 +1528,7 @@ class Test65C02 : TestCommon6502() {
|
|||
mpu.regPC = 0x0204
|
||||
mpu.step()
|
||||
assertEquals(0x1F6, mpu.regPC)
|
||||
assertEquals(3 + Cpu65C02.resetCycles, mpu.totalCycles.toInt()) // Crossed boundry
|
||||
assertEquals(11, mpu.totalCycles) // Crossed boundry
|
||||
}
|
||||
|
||||
// WAI
|
||||
|
|
@ -1543,7 +1543,7 @@ class Test65C02 : TestCommon6502() {
|
|||
mpu.step()
|
||||
assertEquals(Cpu65C02.Wait.Waiting, mpu.waiting)
|
||||
assertEquals(0x0205, mpu.regPC)
|
||||
assertEquals(3 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11, mpu.totalCycles)
|
||||
}
|
||||
|
||||
// BBR and BBS
|
||||
|
|
|
|||
|
|
@ -1901,7 +1901,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regA = 0xFF
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11L, mpu.totalCycles)
|
||||
assertTrue(mpu.regP.N)
|
||||
}
|
||||
|
||||
|
|
@ -1914,7 +1914,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regA = 0xFF
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11L, mpu.totalCycles)
|
||||
assertFalse(mpu.regP.N)
|
||||
}
|
||||
|
||||
|
|
@ -1927,7 +1927,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regA = 0xFF
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11L, mpu.totalCycles)
|
||||
assertTrue(mpu.regP.V)
|
||||
}
|
||||
|
||||
|
|
@ -1940,7 +1940,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regA = 0xFF
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11L, mpu.totalCycles)
|
||||
assertFalse(mpu.regP.V)
|
||||
}
|
||||
|
||||
|
|
@ -1953,7 +1953,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regA = 0x01
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11L, mpu.totalCycles)
|
||||
assertTrue(mpu.regP.Z)
|
||||
assertEquals(0x01, mpu.regA)
|
||||
assertEquals(0x00, memory[0x0010])
|
||||
|
|
@ -1968,7 +1968,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regA = 0x01
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11L, mpu.totalCycles)
|
||||
assertFalse(mpu.regP.Z) // result of AND is non-zero
|
||||
assertEquals(0x01, mpu.regA)
|
||||
assertEquals(0x01, memory[0x0010])
|
||||
|
|
@ -1983,7 +1983,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regA = 0x01
|
||||
mpu.step()
|
||||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt())
|
||||
assertEquals(11L, mpu.totalCycles)
|
||||
assertTrue(mpu.regP.Z) // result of AND is zero
|
||||
assertEquals(0x01, mpu.regA)
|
||||
assertEquals(0x00, memory[0x0010])
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user