This commit is contained in:
Irmen de Jong 2020-02-21 01:57:00 +01:00
parent cd00191dcf
commit ec9b80433f
4 changed files with 11 additions and 11 deletions

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@ -16,15 +16,15 @@ This is a Kotlin/JVM library that simulates the 8-bit 6502 and 65C02 microproces
Properties of this simulator:
- Written in Kotlin. It is low-level code, but hopefully still readable :-)
- Designed to simulate various hardware components (bus, cpu, memory, i/o controllers)
- IRQ and NMI simulation
- Aims to simulate correct instruction cycle timing, but is not 100% cycle exact for simplicity
- Aims to implements all 6502 and 65c02 instructions, including the 'illegal' 6502 instructions (not yet done)
- written in Kotlin. It is low-level code, but hopefully still readable :-)
- simulates various hardware components (bus, cpu, memory, i/o controllers)
- IRQ and NMI
- instruction cycle times are simulated (however the *internal* cpu behavior is not cycle-exact for simplicity reasons)
- has all 6502 and 65c02 instructions, including many of the 'illegal' 6502 instructions (goal is 100% eventually)
- correct BCD mode for adc/sbc instructions on both cpu types
- passes several extensive unit test suites that verify instruction and cpu flags behavior
- simple debugging machine monitor, which basic disassembler and assembler functions
- provide a few virtual example machines, one of which is a Commodore-64
- provide a few virtual example machines, one of which is a fairly capable Commodore-64
## Documentation

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@ -86,7 +86,7 @@ class Cia(val number: Int, startAddress: Address, endAddress: Address, val cpu:
totalCycles++
if (totalCycles%20000 == 0) {
// TOD resolution is 0.1 second, no need to update it in every cycle
// TOD resolution is 0.1 second, no need to update it in every bus cycle
tod.update()
}

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@ -160,7 +160,7 @@ open class Cpu6502 : BusComponent() {
/**
* Process once clock cycle in the cpu.
* Use this if goal is cycle-perfect emulation.
* Use this if you need cycle-perfect instruction timing simulation.
*/
override fun clock() {
if (instrCycles == 0) {
@ -222,7 +222,7 @@ open class Cpu6502 : BusComponent() {
/**
* Execute one single complete instruction.
* Use this when the goal is emulation performance and not a cycle perfect system.
* Use this when you don't care about clock cycle instruction timing simulation.
*/
open fun step() {
totalCycles += instrCycles

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@ -17,7 +17,7 @@ class Cpu65C02 : Cpu6502() {
/**
* Process once clock cycle in the cpu
* Use this if goal is cycle-perfect emulation.
* Use this if you need cycle-perfect instruction timing simulation.
*/
override fun clock() {
when (waiting) {
@ -40,7 +40,7 @@ class Cpu65C02 : Cpu6502() {
/**
* Execute one single complete instruction.
* Use this when the goal is emulation performance and not a cycle perfect system.
* Use this when you don't care about clock cycle instruction timing simulation.
*/
override fun step() {
totalCycles += instrCycles