mirror of
https://github.com/irmen/ksim65.git
synced 2024-06-15 04:29:31 +00:00
fixed jdk11 specifics and debugger race condition
This commit is contained in:
Irmen de Jong
parent
81c01ec2d5
commit
fce84a6881
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@ -271,16 +271,17 @@ class DebugWindow(private val vm: IVirtualMachine) : JFrame("debugger"), ActionL
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}
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}
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fun updateCpu(cpu: Cpu6502, bus: Bus) {
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cyclesTf.text = cpu.totalCycles.toString()
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regAtf.text = cpu.hexB(cpu.regA)
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regXtf.text = cpu.hexB(cpu.regX)
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regYtf.text = cpu.hexB(cpu.regY)
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regPtf.text = "NV-BDIZC\n" + cpu.regP.asByte().toString(2).padStart(8, '0')
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regPCtf.text = cpu.hexW(cpu.regPC)
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regSPtf.text = cpu.hexB(cpu.regSP)
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val memory = bus.memoryComponentFor(cpu.regPC)
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disassemTf.text = cpu.disassembleOneInstruction(memory.data, cpu.regPC, memory.startAddress).first.substringAfter(' ').trim()
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fun updateCpu(cpu2: Cpu6502, bus: Bus) {
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val state = cpu2.snapshot()
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cyclesTf.text = state.cycles.toString()
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regAtf.text = cpu2.hexB(state.A)
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regXtf.text = cpu2.hexB(state.X)
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regYtf.text = cpu2.hexB(state.Y)
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regPtf.text = "NV-BDIZC\n" + state.P.asInt().toString(2).padStart(8, '0')
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regPCtf.text = cpu2.hexW(state.PC)
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regSPtf.text = cpu2.hexB(state.SP)
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val memory = bus.memoryComponentFor(state.PC)
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disassemTf.text = cpu2.disassembleOneInstruction(memory.data, state.PC, memory.startAddress).first.substringAfter(' ').trim()
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val pages = vm.getZeroAndStackPages()
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if(pages.isNotEmpty()) {
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val zpLines = (0..0xff step 32).map { location ->
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@ -300,7 +301,7 @@ class DebugWindow(private val vm: IVirtualMachine) : JFrame("debugger"), ActionL
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}
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val spentTime = System.currentTimeMillis() - startTime
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val speedKhz = cpu.totalCycles.toDouble() / spentTime
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val speedKhz = state.cycles.toDouble() / spentTime
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speedKhzTf.text = "%.1f".format(speedKhz)
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}
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}
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@ -15,7 +15,7 @@ class EhBasicMachine(title: String) {
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val bus = Bus()
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val cpu = Cpu6502(false)
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val ram = Ram(0x0000, 0xbfff)
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val rom = Rom(0xc000, 0xffff).also { it.load(javaClass.getResourceAsStream("/ehbasic_C000.bin").readAllBytes()) }
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val rom = Rom(0xc000, 0xffff).also { it.load(javaClass.getResourceAsStream("/ehbasic_C000.bin").readBytes()) }
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private val hostDisplay = MainWindow(title)
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private val display = Display(0xd000, 0xd00a, hostDisplay,
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@ -71,12 +71,8 @@ class Bus {
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}
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}
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fun memoryComponentFor(address: Address): MemoryComponent {
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memComponents.forEach {
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if (it is MemoryComponent && address >= it.startAddress && address <= it.endAddress) {
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return it
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}
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}
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throw NoSuchElementException()
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}
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fun memoryComponentFor(address: Address): MemoryComponent =
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memComponents.first {
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it is MemoryComponent && address >= it.startAddress && address <= it.endAddress
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} as MemoryComponent
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}
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@ -53,7 +53,7 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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var V: Boolean = false,
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var N: Boolean = false
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) {
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fun asByte(): UByte {
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fun asInt(): Int {
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return (0b00100000 or
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(if (N) 0b10000000 else 0) or
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(if (V) 0b01000000 else 0) or
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@ -62,10 +62,10 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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(if (I) 0b00000100 else 0) or
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(if (Z) 0b00000010 else 0) or
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(if (C) 0b00000001 else 0)
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).toShort()
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)
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}
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fun fromByte(byte: Int) {
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fun fromInt(byte: Int) {
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N = (byte and 0b10000000) != 0
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V = (byte and 0b01000000) != 0
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B = (byte and 0b00010000) != 0
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@ -76,20 +76,31 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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}
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override fun toString(): String {
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return asByte().toString(2).padStart(8, '0')
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return asInt().toString(2).padStart(8, '0')
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}
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override fun hashCode(): Int = asByte().toInt()
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override fun hashCode(): Int = asInt()
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override fun equals(other: Any?): Boolean {
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if (other !is StatusRegister)
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return false
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return asByte() == other.asByte()
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return asInt() == other.asInt()
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}
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}
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protected class Instruction(val mnemonic: String, val mode: AddrMode, val cycles: Int)
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class BreakpointResult(val newPC: Address?, val newOpcode: Int?)
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class State (
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val A: UByte,
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val X: UByte,
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val Y: UByte,
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val SP: Address,
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val P: StatusRegister,
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val PC: Address,
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val cycles: Long
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)
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var regA: Int = 0
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var regX: Int = 0
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@ -106,6 +117,17 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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val currentMnemonic: String
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get() = currentInstruction.mnemonic
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@Synchronized fun snapshot(): State {
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val status = StatusRegister().also { it.fromInt(regP.asInt()) }
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return State(regA.toShort(),
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regX.toShort(),
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regY.toShort(),
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regSP,
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status,
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regPC,
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totalCycles)
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}
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// has an interrupt been requested?
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protected enum class Interrupt {
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IRQ,
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@ -119,8 +141,6 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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// all other addressing modes yield a fetched memory address
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protected var fetchedAddress: Address = 0
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class BreakpointResult(val newPC: Address?, val newOpcode: Int?)
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private val breakpoints = mutableMapOf<Address, (cpu: Cpu6502, pc: Address) -> BreakpointResult>()
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fun addBreakpoint(address: Address, action: (cpu: Cpu6502, pc: Address) -> BreakpointResult) {
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@ -395,7 +415,7 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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}
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protected fun pushStack(status: StatusRegister) {
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pushStack(status.asByte().toInt())
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pushStack(status.asInt())
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}
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protected fun pushStack(data: Int) {
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@ -1282,7 +1302,7 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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}
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protected fun iPlp() {
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regP.fromByte(popStack())
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regP.fromInt(popStack())
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regP.B = true // break is always 1 except when pushing on stack
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}
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@ -1321,7 +1341,7 @@ open class Cpu6502(private val stopOnBrk: Boolean = false) : BusComponent() {
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}
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protected fun iRti() {
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regP.fromByte(popStack())
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regP.fromInt(popStack())
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regP.B = true // break is always 1 except when pushing on stack
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regPC = popStackAddr()
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}
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@ -32,7 +32,7 @@ class Ram(startAddress: Address, endAddress: Address) : MemoryComponent(startAdd
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* Load a c64-style prg program. This file type has the load address as the first two bytes.
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*/
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fun loadPrg(stream: InputStream) {
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val bytes = stream.readAllBytes()
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val bytes = stream.readBytes()
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val loadAddress = (bytes[0].toInt() or (bytes[1].toInt() shl 8)) and 65535
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val baseAddress = loadAddress - startAddress
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bytes.drop(2).forEachIndexed { index, byte ->
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@ -1 +1 @@
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version=1.0
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version=1.1
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@ -45,7 +45,7 @@ abstract class FunctionalTestsBase {
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ram.loadPrg("src/test/kotlin/6502testsuite/$testprogram")
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bus.reset()
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cpu.regSP = 0xfd
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cpu.regP.fromByte(0b00100100)
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cpu.regP.fromInt(0b00100100)
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try {
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while (cpu.totalCycles < 50000000L) {
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bus.clock()
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@ -24,7 +24,7 @@ class Test6502CpuBasics {
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assertEquals(0, cpu.regY)
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assertEquals(0, cpu.currentOpcode)
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assertEquals(Cpu6502.StatusRegister(C = false, Z = false, I = true, D = false, B = false, V = false, N = false), cpu.regP)
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assertEquals(0b00100100, cpu.regP.asByte())
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assertEquals(0b00100100, cpu.regP.asInt())
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}
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@Test
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@ -42,7 +42,7 @@ class Test6502CpuBasics {
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assertEquals(0, cpu.regY)
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assertEquals(0, cpu.currentOpcode)
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assertEquals(Cpu6502.StatusRegister(C = false, Z = false, I = true, D = false, B = false, V = false, N = false), cpu.regP)
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assertEquals(0b00100100, cpu.regP.asByte())
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assertEquals(0b00100100, cpu.regP.asInt())
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}
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@Test
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@ -798,9 +798,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 RMB0 $43
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writeMem(memory, 0x0000, listOf(0x07, 0x43))
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val expected = 0b01110101
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// RMB1
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@ -823,9 +823,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 RMB1 $43
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writeMem(memory, 0x0000, listOf(0x17, 0x43))
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val expected = 0b01110101
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// RMB2
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@ -838,8 +838,8 @@ class Test65C02 : TestCommon6502() {
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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val expected = 0b11111011
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assertEquals(expected, memory[0x0043].toInt())
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val expected = 0b11111011.toShort()
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assertEquals(expected, memory[0x0043])
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}
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@ -849,9 +849,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 RMB2 $43
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writeMem(memory, 0x0000, listOf(0x27, 0x43))
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val expected = 0b01110101
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// RMB3
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@ -874,9 +874,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 RMB3 $43
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writeMem(memory, 0x0000, listOf(0x37, 0x43))
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val expected = 0b01110101
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// RMB4
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@ -899,9 +899,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 RMB4 $43
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writeMem(memory, 0x0000, listOf(0x47, 0x43))
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val expected = 0b01110101
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// RMB5
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@ -924,9 +924,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 RMB5 $43
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writeMem(memory, 0x0000, listOf(0x57, 0x43))
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val expected = 0b01110101
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// RMB6
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@ -939,8 +939,8 @@ class Test65C02 : TestCommon6502() {
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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val expected = 0b10111111
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assertEquals(expected, memory[0x0043].toInt())
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val expected = 0b10111111.toShort()
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assertEquals(expected, memory[0x0043])
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}
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@Test
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@ -949,9 +949,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 RMB6 $43
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writeMem(memory, 0x0000, listOf(0x67, 0x43))
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val expected = 0b01110101
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// RMB7
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@ -975,9 +975,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 RMB7 $43
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writeMem(memory, 0x0000, listOf(0x77, 0x43))
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val expected = 0b01110101
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// STA Zero Page, Indirect
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@ -985,7 +985,7 @@ class Test65C02 : TestCommon6502() {
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@Test
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fun test_sta_zp_ind_stores_a_leaves_a_and_n_flag_unchanged() {
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val flags = 0xFF and fNEGATIVE.inv()
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mpu.regP.fromByte(flags)
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mpu.regP.fromInt(flags)
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mpu.regA = 0xFF
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// $0000 STA ($0010)
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// $0010 Vector to $FEED
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@ -997,13 +997,13 @@ class Test65C02 : TestCommon6502() {
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(0xFF, memory[0xFEED])
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assertEquals(0xFF, mpu.regA)
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assertEquals(flags, mpu.regP.asByte().toInt())
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assertEquals(flags, mpu.regP.asInt())
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}
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@Test
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fun test_sta_zp_ind_stores_a_leaves_a_and_z_flag_unchanged() {
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val flags = 0xFF and fZERO.inv()
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mpu.regP.fromByte(flags)
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mpu.regP.fromInt(flags)
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mpu.regA = 0x00
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// $0000 STA ($0010)
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// $0010 Vector to $FEED
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@ -1015,7 +1015,7 @@ class Test65C02 : TestCommon6502() {
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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assertEquals(0x00, memory[0xFEED])
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assertEquals(0x00, mpu.regA)
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assertEquals(flags, mpu.regP.asByte().toInt())
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assertEquals(flags, mpu.regP.asInt())
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}
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// SMB0
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@ -1028,8 +1028,8 @@ class Test65C02 : TestCommon6502() {
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mpu.step()
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assertEquals(0x0002, mpu.regPC)
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assertEquals(5 + Cpu65C02.resetCycles, mpu.totalCycles.toInt())
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val expected = 0b00000001
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assertEquals(expected, memory[0x0043].toInt())
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val expected = 0b00000001.toShort()
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assertEquals(expected, memory[0x0043])
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}
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@Test
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@ -1038,9 +1038,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 SMB0 $43
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writeMem(memory, 0x0000, listOf(0x87, 0x43))
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val expected = 0b11101100
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// SMB1
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@ -1063,9 +1063,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 SMB1 $43
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writeMem(memory, 0x0000, listOf(0x97, 0x43))
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val expected = 0b11101100
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mpu.regP.fromByte(expected)
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mpu.regP.fromInt(expected)
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mpu.step()
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assertEquals(expected, mpu.regP.asByte().toInt())
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assertEquals(expected, mpu.regP.asInt())
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}
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// SMB2
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@ -1089,9 +1089,9 @@ class Test65C02 : TestCommon6502() {
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// $0000 SMB2 $43
|
||||
writeMem(memory, 0x0000, listOf(0xA7, 0x43))
|
||||
val expected = 0b11101100
|
||||
mpu.regP.fromByte(expected)
|
||||
mpu.regP.fromInt(expected)
|
||||
mpu.step()
|
||||
assertEquals(expected, mpu.regP.asByte().toInt())
|
||||
assertEquals(expected, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// SMB3
|
||||
|
|
@ -1115,9 +1115,9 @@ class Test65C02 : TestCommon6502() {
|
|||
// $0000 SMB3 $43
|
||||
writeMem(memory, 0x0000, listOf(0xB7, 0x43))
|
||||
val expected = 0b11101100
|
||||
mpu.regP.fromByte(expected)
|
||||
mpu.regP.fromInt(expected)
|
||||
mpu.step()
|
||||
assertEquals(expected, mpu.regP.asByte().toInt())
|
||||
assertEquals(expected, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// SMB4
|
||||
|
|
@ -1141,9 +1141,9 @@ class Test65C02 : TestCommon6502() {
|
|||
// $0000 SMB4 $43
|
||||
writeMem(memory, 0x0000, listOf(0xC7, 0x43))
|
||||
val expected = 0b11101100
|
||||
mpu.regP.fromByte(expected)
|
||||
mpu.regP.fromInt(expected)
|
||||
mpu.step()
|
||||
assertEquals(expected, mpu.regP.asByte().toInt())
|
||||
assertEquals(expected, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// SMB5
|
||||
|
|
@ -1166,9 +1166,9 @@ class Test65C02 : TestCommon6502() {
|
|||
// $0000 SMB5 $43
|
||||
writeMem(memory, 0x0000, listOf(0xD7, 0x43))
|
||||
val expected = 0b11101100
|
||||
mpu.regP.fromByte(expected)
|
||||
mpu.regP.fromInt(expected)
|
||||
mpu.step()
|
||||
assertEquals(expected, mpu.regP.asByte().toInt())
|
||||
assertEquals(expected, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// SMB6
|
||||
|
|
@ -1191,9 +1191,9 @@ class Test65C02 : TestCommon6502() {
|
|||
// $0000 SMB6 $43
|
||||
writeMem(memory, 0x0000, listOf(0xE7, 0x43))
|
||||
val expected = 0b11101100
|
||||
mpu.regP.fromByte(expected)
|
||||
mpu.regP.fromInt(expected)
|
||||
mpu.step()
|
||||
assertEquals(expected, mpu.regP.asByte().toInt())
|
||||
assertEquals(expected, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// SMB7
|
||||
|
|
@ -1216,9 +1216,9 @@ class Test65C02 : TestCommon6502() {
|
|||
// $0000 SMB7 $43
|
||||
writeMem(memory, 0x0000, listOf(0xF7, 0x43))
|
||||
val expected = 0b11101100
|
||||
mpu.regP.fromByte(expected)
|
||||
mpu.regP.fromInt(expected)
|
||||
mpu.step()
|
||||
assertEquals(expected, mpu.regP.asByte().toInt())
|
||||
assertEquals(expected, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// SBC Zero Page, Indirect
|
||||
|
|
|
|||
|
|
@ -2099,7 +2099,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0xC0, memory[0x1FF]) // PCH
|
||||
assertEquals(0x02, memory[0x1FE]) // PCL
|
||||
assertEquals(fBREAK or fUNUSED, memory[0x1FD].toInt(), "Status on stack should have no I flag")
|
||||
assertEquals(fBREAK or fUNUSED or fINTERRUPT, mpu.regP.asByte().toInt())
|
||||
assertEquals(fBREAK or fUNUSED or fINTERRUPT, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// BVC
|
||||
|
|
@ -4122,7 +4122,7 @@ abstract class TestCommon6502 {
|
|||
fun test_php_pushes_processor_status_and_updates_sp() {
|
||||
for (flags in 0 until 0x100) {
|
||||
mpu.reset()
|
||||
mpu.regP.fromByte(flags or fBREAK or fUNUSED)
|
||||
mpu.regP.fromInt(flags or fBREAK or fUNUSED)
|
||||
// $0000 PHP
|
||||
memory[0x0000] = 0x08
|
||||
mpu.step()
|
||||
|
|
@ -4156,7 +4156,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regSP = 0xFE
|
||||
mpu.step()
|
||||
assertEquals(0x0001, mpu.regPC)
|
||||
assertEquals(0xBA, mpu.regP.asByte())
|
||||
assertEquals(0xBA, mpu.regP.asInt())
|
||||
assertEquals(0xFF, mpu.regSP)
|
||||
}
|
||||
|
||||
|
|
@ -4847,7 +4847,7 @@ abstract class TestCommon6502 {
|
|||
mpu.regSP = 0xFC
|
||||
mpu.step()
|
||||
assertEquals(0xFF, mpu.regSP)
|
||||
assertEquals(0xFC, mpu.regP.asByte())
|
||||
assertEquals(0xFC, mpu.regP.asInt())
|
||||
assertEquals(0xC003, mpu.regPC)
|
||||
}
|
||||
|
||||
|
|
@ -5505,7 +5505,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sta_absolute_stores_a_leaves_a_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0xFF
|
||||
// $0000 STA $ABCD
|
||||
writeMem(memory, 0x0000, listOf(0x8D, 0xCD, 0xAB))
|
||||
|
|
@ -5514,13 +5514,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0xABCD])
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sta_absolute_stores_a_leaves_a_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0x00
|
||||
// $0000 STA $ABCD
|
||||
writeMem(memory, 0x0000, listOf(0x8D, 0xCD, 0xAB))
|
||||
|
|
@ -5529,7 +5529,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0x00, memory[0xABCD])
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STA Zero Page
|
||||
|
|
@ -5537,7 +5537,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sta_zp_stores_a_leaves_a_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0xFF
|
||||
// $0000 STA $0010
|
||||
writeMem(memory, 0x0000, listOf(0x85, 0x10))
|
||||
|
|
@ -5546,13 +5546,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0x0010])
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sta_zp_stores_a_leaves_a_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0x00
|
||||
// $0000 STA $0010
|
||||
writeMem(memory, 0x0000, listOf(0x85, 0x10))
|
||||
|
|
@ -5561,7 +5561,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0x00, memory[0x0010])
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STA Absolute, X-Indexed
|
||||
|
|
@ -5569,7 +5569,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sta_abs_x_indexed_stores_a_leaves_a_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0xFF
|
||||
mpu.regX = 0x03
|
||||
// $0000 STA $ABCD,X
|
||||
|
|
@ -5579,13 +5579,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0xABCD + mpu.regX])
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sta_abs_x_indexed_stores_a_leaves_a_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0x00
|
||||
mpu.regX = 0x03
|
||||
// $0000 STA $ABCD,X
|
||||
|
|
@ -5595,7 +5595,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0x00, memory[0xABCD + mpu.regX])
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STA Absolute, Y-Indexed
|
||||
|
|
@ -5603,7 +5603,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sta_abs_y_indexed_stores_a_leaves_a_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0xFF
|
||||
mpu.regY = 0x03
|
||||
// $0000 STA $ABCD,Y
|
||||
|
|
@ -5613,13 +5613,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0xABCD + mpu.regY])
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sta_abs_y_indexed_stores_a_leaves_a_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0x00
|
||||
mpu.regY = 0x03
|
||||
// $0000 STA $ABCD,Y
|
||||
|
|
@ -5629,7 +5629,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0x00, memory[0xABCD + mpu.regY])
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STA Indirect, Indexed (X)
|
||||
|
|
@ -5637,7 +5637,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sta_ind_indexed_x_stores_a_leaves_a_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0xFF
|
||||
mpu.regX = 0x03
|
||||
// $0000 STA ($0010,X)
|
||||
|
|
@ -5649,13 +5649,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0xFEED])
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sta_ind_indexed_x_stores_a_leaves_a_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0x00
|
||||
mpu.regX = 0x03
|
||||
// $0000 STA ($0010,X)
|
||||
|
|
@ -5667,7 +5667,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0x00, memory[0xFEED])
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STA Indexed, Indirect (Y)
|
||||
|
|
@ -5675,7 +5675,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sta_indexed_ind_y_stores_a_leaves_a_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0xFF
|
||||
mpu.regY = 0x03
|
||||
// $0000 STA ($0010),Y
|
||||
|
|
@ -5687,13 +5687,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0xFEED + mpu.regY])
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sta_indexed_ind_y_stores_a_leaves_a_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0x00
|
||||
mpu.regY = 0x03
|
||||
// $0000 STA ($0010),Y
|
||||
|
|
@ -5705,7 +5705,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0x00, memory[0xFEED + mpu.regY])
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STA Zero Page, X-Indexed
|
||||
|
|
@ -5713,7 +5713,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sta_zp_x_indexed_stores_a_leaves_a_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0xFF
|
||||
mpu.regX = 0x03
|
||||
// $0000 STA $0010,X
|
||||
|
|
@ -5723,13 +5723,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0x0010 + mpu.regX])
|
||||
assertEquals(0xFF, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sta_zp_x_indexed_stores_a_leaves_a_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regA = 0x00
|
||||
mpu.regX = 0x03
|
||||
// $0000 STA $0010,X
|
||||
|
|
@ -5739,7 +5739,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0x00, memory[0x0010 + mpu.regX])
|
||||
assertEquals(0x00, mpu.regA)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STX Absolute
|
||||
|
|
@ -5747,7 +5747,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_stx_absolute_stores_x_leaves_x_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regX = 0xFF
|
||||
// $0000 STX $ABCD
|
||||
writeMem(memory, 0x0000, listOf(0x8E, 0xCD, 0xAB))
|
||||
|
|
@ -5756,13 +5756,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0xABCD])
|
||||
assertEquals(0xFF, mpu.regX)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_stx_absolute_stores_x_leaves_x_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regX = 0x00
|
||||
// $0000 STX $ABCD
|
||||
writeMem(memory, 0x0000, listOf(0x8E, 0xCD, 0xAB))
|
||||
|
|
@ -5771,7 +5771,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0x00, memory[0xABCD])
|
||||
assertEquals(0x00, mpu.regX)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STX Zero Page
|
||||
|
|
@ -5779,7 +5779,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_stx_zp_stores_x_leaves_x_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regX = 0xFF
|
||||
// $0000 STX $0010
|
||||
writeMem(memory, 0x0000, listOf(0x86, 0x10))
|
||||
|
|
@ -5788,13 +5788,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0x0010])
|
||||
assertEquals(0xFF, mpu.regX)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_stx_zp_stores_x_leaves_x_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regX = 0x00
|
||||
// $0000 STX $0010
|
||||
writeMem(memory, 0x0000, listOf(0x86, 0x10))
|
||||
|
|
@ -5803,7 +5803,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0x00, memory[0x0010])
|
||||
assertEquals(0x00, mpu.regX)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STX Zero Page, Y-Indexed
|
||||
|
|
@ -5811,7 +5811,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_stx_zp_y_indexed_stores_x_leaves_x_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regX = 0xFF
|
||||
mpu.regY = 0x03
|
||||
// $0000 STX $0010,Y
|
||||
|
|
@ -5821,13 +5821,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0x0010 + mpu.regY])
|
||||
assertEquals(0xFF, mpu.regX)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_stx_zp_y_indexed_stores_x_leaves_x_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regX = 0x00
|
||||
mpu.regY = 0x03
|
||||
// $0000 STX $0010,Y
|
||||
|
|
@ -5837,7 +5837,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0x00, memory[0x0010 + mpu.regY])
|
||||
assertEquals(0x00, mpu.regX)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STY Absolute
|
||||
|
|
@ -5845,7 +5845,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sty_absolute_stores_y_leaves_y_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regY = 0xFF
|
||||
// $0000 STY $ABCD
|
||||
writeMem(memory, 0x0000, listOf(0x8C, 0xCD, 0xAB))
|
||||
|
|
@ -5854,13 +5854,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0xABCD])
|
||||
assertEquals(0xFF, mpu.regY)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sty_absolute_stores_y_leaves_y_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regY = 0x00
|
||||
// $0000 STY $ABCD
|
||||
writeMem(memory, 0x0000, listOf(0x8C, 0xCD, 0xAB))
|
||||
|
|
@ -5869,7 +5869,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0003, mpu.regPC)
|
||||
assertEquals(0x00, memory[0xABCD])
|
||||
assertEquals(0x00, mpu.regY)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STY Zero Page
|
||||
|
|
@ -5877,7 +5877,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sty_zp_stores_y_leaves_y_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regY = 0xFF
|
||||
// $0000 STY $0010
|
||||
writeMem(memory, 0x0000, listOf(0x84, 0x10))
|
||||
|
|
@ -5886,13 +5886,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0x0010])
|
||||
assertEquals(0xFF, mpu.regY)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sty_zp_stores_y_leaves_y_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regY = 0x00
|
||||
// $0000 STY $0010
|
||||
writeMem(memory, 0x0000, listOf(0x84, 0x10))
|
||||
|
|
@ -5901,7 +5901,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0x00, memory[0x0010])
|
||||
assertEquals(0x00, mpu.regY)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// STY Zero Page, X-Indexed
|
||||
|
|
@ -5909,7 +5909,7 @@ abstract class TestCommon6502 {
|
|||
@Test
|
||||
fun test_sty_zp_x_indexed_stores_y_leaves_y_and_n_flag_unchanged() {
|
||||
val flags = 0xFF and fNEGATIVE.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regY = 0xFF
|
||||
mpu.regX = 0x03
|
||||
// $0000 STY $0010,X
|
||||
|
|
@ -5919,13 +5919,13 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0xFF, memory[0x0010 + mpu.regX])
|
||||
assertEquals(0xFF, mpu.regY)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
@Test
|
||||
fun test_sty_zp_x_indexed_stores_y_leaves_y_and_z_flag_unchanged() {
|
||||
val flags = 0xFF and fZERO.inv()
|
||||
mpu.regP.fromByte(flags)
|
||||
mpu.regP.fromInt(flags)
|
||||
mpu.regY = 0x00
|
||||
mpu.regX = 0x03
|
||||
// $0000 STY $0010,X
|
||||
|
|
@ -5935,7 +5935,7 @@ abstract class TestCommon6502 {
|
|||
assertEquals(0x0002, mpu.regPC)
|
||||
assertEquals(0x00, memory[0x0010 + mpu.regX])
|
||||
assertEquals(0x00, mpu.regY)
|
||||
assertEquals(flags, mpu.regP.asByte().toInt())
|
||||
assertEquals(flags, mpu.regP.asInt())
|
||||
}
|
||||
|
||||
// TAX
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user