Added MVIX instruction.

This commit is contained in:
mooz 2018-11-10 17:48:14 +01:00
parent 93ffdf28dd
commit 09a45eaffb
3 changed files with 46 additions and 10 deletions

View File

@ -40,7 +40,7 @@ local Keywords_data = {
local Keywords_7801 = {
'aci','adi','adinc','ani','bit0','bit1','bit2','bit3','bit4','bit5','bit6','bit7',
'block','calb','calf','call','calt','clc','ei','eqi','daa','di','dcr','dcrw','dcx',
'ex','exx','gti','halt','inr','inrw','inx','jb','jmp','jr','jre','ldaw','lti','lxi','mov','mvi','nei','nop',
'ex','exx','gti','halt','inr','inrw','inx','jb','jmp','jr','jre','ldaw','lti','lxi','mov','mvi','mvix','nei','nop',
'offi','oni','ori','pen','per','pex','ret','reti','rets','rld','rrd','sio','softi','staw','stc','stm',
'sbi','sui','suinb','table','xri',
}
@ -90,6 +90,9 @@ local opcode_reg_reg = lookupify{
local opcode_regb = lookupify{
'aci','adi','adinc','ani','eqi','gti','lti','mvi','nei','offi','oni','ori','sbi','sui','suinb','xri',
}
local opcode_regb_ind = lookupify{
'mvix'
}
local opcode_regw = lookupify{
'lxi'
}
@ -102,9 +105,9 @@ local opcode_reg_list = {
h = lookupify{'mvi'},
l = lookupify{'mvi'},
v = lookupify{'mvi'},
bc = lookupify{'lxi'},
de = lookupify{'lxi'},
hl = lookupify{'dcx','inx','lxi'},
bc = lookupify{'lxi','mvix'},
de = lookupify{'lxi','mvix'},
hl = lookupify{'dcx','inx','lxi','mvix'},
sp = lookupify{'dcx','inx','lxi'},
}
@ -146,6 +149,7 @@ local addressing_map = {
reg = opcode_reg,
regb = opcode_regb,
regw = opcode_regw,
regb_ind = opcode_regb_ind,
}
local Scope = {
@ -1453,6 +1457,33 @@ local function ParseLua(src, src_name)
end
stat = emit_call{name=op, args={expr, mod_expr}, inverse_encapsulate=inverse_encapsulate, paren_open_white=paren_open_whites} break
end
if opcode_regb_ind[op] then
if not tok:ConsumeSymbol('(', tokenList) then
return false, GenerateError("Unexpected character")
end
local register_name = tok:Get(tokenList).Data
if not Registers_7801[register_name] then
return false, GenerateError(register_name .. " is not a valid register")
end
if not (opcode_reg_list[register_name] and opcode_reg_list[register_name][op]) then
return false, GenerateError("Opcode " .. op .. " doesn't support this addressing mode")
end
if not tok:ConsumeSymbol(')', tokenList)
or not tok:ConsumeSymbol(',', tokenList) then
return false, GenerateError("Unexpected character")
end
inverse_encapsulate = tok:ConsumeSymbol('!', tokenList)
local st, expr = ParseExpr(scope) if not st then return false, expr end
local paren_open_whites = {}
if inverse_encapsulate then for _,v in ipairs(tokenList[#tokenList-1].LeadingWhite) do table.insert(paren_open_whites, v) end end
for _,v in ipairs(tokenList[#tokenList].LeadingWhite) do table.insert(paren_open_whites, v) end
if tok:ConsumeSymbol(',', tokenList) then
commaTokenList[1] = tokenList[#tokenList]
mod_st, mod_expr = ParseExpr(scope)
if not mod_st then return false, mod_expr end
end
stat = emit_call{name=op .. register_name, args={expr, mod_expr}, inverse_encapsulate=inverse_encapsulate, paren_open_white=paren_open_whites} break
end
if opcode_wa[op] then
if not tok:ConsumeSymbol('(', tokenList) then
return false, GenerateError("Unexpected character")

View File

@ -113,4 +113,8 @@ section{"rom", org=0x8000}
inx bc
inx de
inx hl
mvix (bc),0xf9
mvix (de),0xe8
mvix (hl),0xd7
writebin(filename .. '.bin')

View File

@ -91,7 +91,10 @@ local opregxx ={
mvie=M.op(0x6d,7),
mvih=M.op(0x6e,7),
mvil=M.op(0x6f,7),
mviv=M.op(0x68,7)
mviv=M.op(0x68,7),
mvixbc=M.op(0x49,10),
mvixde=M.op(0x4a,10),
mvixhl=M.op(0x4b,10),
} M.opregxx = opregxx
for k,v in pairs(opregxx) do
M[k] = function(late, early)
@ -305,11 +308,6 @@ return M
staxm=M.op(0x3f,7),
staxp=M.op(0x3d,7)
-- (r16),hhll
mvixbc=M.op(0x49,10),
mvixde=M.op(0x4a,10),
mvixhl=M.op(0x4b,10)
- (r16)
ldaxbc=M.op(0x29,7),
ldaxde=M.op(0x2a,7),
@ -318,6 +316,9 @@ return M
staxde=M.op(0x3a,7),
staxhl=M.op(0x3b,7),
-- (wa),xx
mviw (v,xx),xx 0x71 3 13
16 bits instructions:
0x48xx
0x4cxx