llvm-6502/test/MC/Mips/mips5/invalid-mips64r2-xfail.s

# Instructions that are supposed to be invalid but currently aren't
# This test will XPASS if any insn stops assembling.
#
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \
# RUN:     2> %t1
# RUN: not FileCheck %s < %t1
# XFAIL: *

# CHECK-NOT: error
        .set noat
	rdhwr	$sp,$11
[mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5\|64) does not accept MIPS64r2 Summary: To limit the number of tests required, only one 64-bit ISA prior to MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3697 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3698 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208785 91177308-0d34-0410-b5e6-96231b3b80d8 2014-05-14 15:35:03 +00:00			`# Instructions that are supposed to be invalid but currently aren't`
			`# This test will XPASS if any insn stops assembling.`
			`#`
			`# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \`
			`# RUN: 2> %t1`
			`# RUN: not FileCheck %s < %t1`
			`# XFAIL: *`

			`# CHECK-NOT: error`
			`.set noat`
			`rdhwr $sp,$11`