llvm-6502/test/MC/AArch64/arm64-v128_lo-diagnostics.s

// RUN: not llvm-mc -triple arm64 -mattr=neon %s 2> %t > /dev/null
// RUN: FileCheck %s < %t

        sqrdmulh v0.8h, v1.8h, v16.h[0]
// CHECK: error: invalid operand for instruction

        sqrdmulh h0, h1, v16.h[0]
// CHECK: error: invalid operand for instruction

        sqdmull2 v0.4h, v1.8h, v16.h[0]
// CHECK: error: invalid operand for instruction
ARM64: diagnose use of v16-v31 in certain indexed NEON instructions. Someone couldn't bear to have a completely orthogonal set of floating-point registers, so we've got some instructions that only accept v0-v15 (coming in ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...). Anyway, we were permitting even the out of range registers during assembly (CodeGen handled it correctly). This adds a diagnostic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207412 91177308-0d34-0410-b5e6-96231b3b80d8 2014-04-28 11:27:43 +00:00			`// RUN: not llvm-mc -triple arm64 -mattr=neon %s 2> %t > /dev/null`
			`// RUN: FileCheck %s < %t`

			`sqrdmulh v0.8h, v1.8h, v16.h[0]`
			`// CHECK: error: invalid operand for instruction`

			`sqrdmulh h0, h1, v16.h[0]`
			`// CHECK: error: invalid operand for instruction`

			`sqdmull2 v0.4h, v1.8h, v16.h[0]`
			`// CHECK: error: invalid operand for instruction`