llvm-6502/test/MC/ARM/ldr-pseudo-parse-errors.s

@RUN: not llvm-mc -triple=armv7-unknown-linux-gnueabi < %s  2>&1 | FileCheck %s
@RUN: not llvm-mc -triple=armv7-apple-darwin < %s  2>&1 | FileCheck %s

.text
bar:
  mov r0, =0x101
@ CHECK: error: unexpected token in operand
@ CHECK: mov r0, =0x101
@ CHECK:         ^
Implement the ldr-pseudo opcode for ARM assembly The ldr-pseudo opcode is a convenience for loading 32-bit constants. It is converted into a pc-relative load from a constant pool. For example, ldr r0, =0x10001 ldr r1, =bar will generate this output in the final assembly ldr r0, .Ltmp0 ldr r1, .Ltmp1 ... .Ltmp0: .long 0x10001 .Ltmp1: .long bar Sketch of the LDR pseudo implementation: Keep a map from Section => ConstantPool When parsing ldr r0, =val parse val as an MCExpr get ConstantPool for current Section Label = CreateTempSymbol() remember val in ConstantPool at next free slot add operand to ldr that is MCSymbolRef of Label On finishParse() callback Write out all non-empty constant pools for each Entry in ConstantPool Emit Entry.Label Emit Entry.Value Possible improvements to be added in a later patch: 1. Does not convert load of small constants to mov (e.g. ldr r0, =0x1 => mov r0, 0x1) 2. Does reuse constant pool entries for same constant The implementation was tested for ARM, Thumb1, and Thumb2 targets on linux and darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197708 91177308-0d34-0410-b5e6-96231b3b80d8 2013-12-19 18:12:36 +00:00			`@RUN: not llvm-mc -triple=armv7-unknown-linux-gnueabi < %s 2>&1 \| FileCheck %s`
			`@RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2>&1 \| FileCheck %s`

			`.text`
			`bar:`
			`mov r0, =0x101`
			`@ CHECK: error: unexpected token in operand`
			`@ CHECK: mov r0, =0x101`
			`@ CHECK: ^`