6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-12 13:30:51 +00:00
Code Issues Projects Releases Wiki Activity
release_35
llvm-6502/test/MC/ARM/thumb-only-conditionals.s

55 lines
1.3 KiB
ArmAsm
Raw Permalink Normal View History

ARM: allow predicated barriers in Thumb mode The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 16:52:32 +00:00
@ RUN: llvm-mc -triple=thumbv7-apple-ios -o - %s | FileCheck %s
itte eq
dmbeq #11
dsbeq #7
isbne #15
@ CHECK: itte eq
@ CHECK-NEXT: dmbeq ish
@ CHECK-NEXT: dsbeq nsh
@ CHECK-NEXT: isbne sy
itet le
dmble
dsbgt
isble
@ CHECK: itet le
@ CHECK-NEXT: dmble sy
@ CHECK-NEXT: dsbgt sy
@ CHECK-NEXT: isble sy
ARM: fix more cases where predication may or may not be allowed Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 16:52:40 +00:00
itt gt
cdpgt p7, #1, c1, c1, c1, #4
cdp2gt p7, #1, c1, c1, c1, #4
@ CHECK: itt gt
@ CHECK-NEXT: cdpgt p7, #1, c1, c1, c1, #4
@ CHECK-NEXT: cdp2gt p7, #1, c1, c1, c1, #4
itt ne
mcrne p0, #0, r0, c0, c0, #0
mcr2ne p0, #0, r0, c0, c0, #0
@ CHECK: itt ne
@ CHECK-NEXT: mcrne p0, #0, r0, c0, c0, #0
@ CHECK-NEXT: mcr2ne p0, #0, r0, c0, c0, #0
ite le
mcrrle p7, #15, r5, r4, c1
mcrr2gt p7, #15, r5, r4, c1
@ CHECK: ite le
@ CHECK-NEXT: mcrrle p7, #15, r5, r4, c1
@ CHECK-NEXT: mcrr2gt p7, #15, r5, r4, c1
ite eq
[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 09:16:31 +00:00
mrceq p9, #1, r1, c2, c2
ARM: fix more cases where predication may or may not be allowed Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 16:52:40 +00:00
mrc2ne p12, #3, r3, c3, c4
@ CHECK: ite eq
[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 09:16:31 +00:00
@ CHECK-NEXT: mrceq p9, #1, r1, c2, c2
ARM: fix more cases where predication may or may not be allowed Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-26 16:52:40 +00:00
@ CHECK-NEXT: mrc2ne p12, #3, r3, c3, c4
itt lo
mrrclo p7, #1, r5, r4, c1
mrrc2lo p7, #1, r5, r4, c1
@ CHECK: itt lo
@ CHECK-NEXT: mrrclo p7, #1, r5, r4, c1
@ CHECK-NEXT: mrrc2lo p7, #1, r5, r4, c1
Reference in New Issue Copy Permalink