llvm-6502/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll

; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s | FileCheck %s
; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
; rdar://11331541

define i32 @t(i32 %a) nounwind {
; CHECK: t:
; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
; CHECK: eors [[REG1]], [[REG2]]
  %tmp0 = ashr i32 %a, 31
  %tmp1 = xor i32 %tmp0, %a
  ret i32 %tmp1
}
- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2 instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8 2012-04-27 01:27:19 +00:00			`; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=cortex-m0 < %s \| FileCheck %s`
			`; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)`
			`; rdar://11331541`

			`define i32 @t(i32 %a) nounwind {`
			`; CHECK: t:`
Make test less fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155732 91177308-0d34-0410-b5e6-96231b3b80d8 2012-04-27 20:48:18 +00:00			`; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31`
			`; CHECK: eors [[REG1]], [[REG2]]`
- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2 instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8 2012-04-27 01:27:19 +00:00			`%tmp0 = ashr i32 %a, 31`
			`%tmp1 = xor i32 %tmp0, %a`
			`ret i32 %tmp1`
			`}`