2011-07-07 03:55:05 +00:00
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; RUN: llc < %s -mtriple=armv7-apple-darwin -mattr=+v7,+mp -show-mc-encoding | FileCheck %s -check-prefix=ARM
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+v7 -show-mc-encoding | FileCheck %s -check-prefix=T2
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2011-01-27 23:48:34 +00:00
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; rdar://8924681
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define void @t1(i8* %ptr) nounwind {
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entry:
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; ARM: t1:
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; ARM: pldw [r0] @ encoding: [0x00,0xf0,0x90,0xf5]
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; ARM: pld [r0] @ encoding: [0x00,0xf0,0xd0,0xf5]
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; T2: t1:
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; T2: pld [r0] @ encoding: [0x90,0xf8,0x00,0xf0]
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tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 )
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tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
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ret void
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}
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define void @t2(i8* %ptr) nounwind {
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entry:
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; ARM: t2:
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; ARM: pld [r0, #1023] @ encoding: [0xff,0xf3,0xd0,0xf5]
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; T2: t2:
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; T2: pld [r0, #1023] @ encoding: [0x90,0xf8,0xff,0xf3]
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%tmp = getelementptr i8* %ptr, i32 1023
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tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 )
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ret void
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}
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define void @t3(i32 %base, i32 %offset) nounwind {
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entry:
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; ARM: t3:
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; ARM: pld [r0, r1, lsr #2] @ encoding: [0x21,0xf1,0xd0,0xf7]
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; T2: t3:
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; T2: pld [r0, r1] @ encoding: [0x10,0xf8,0x01,0xf0]
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%tmp1 = lshr i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i8*
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
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ret void
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}
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define void @t4(i32 %base, i32 %offset) nounwind {
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entry:
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; ARM: t4:
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; ARM: pld [r0, r1, lsl #2] @ encoding: [0x01,0xf1,0xd0,0xf7]
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; T2: t4:
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; T2: pld [r0, r1, lsl #2] @ encoding: [0x10,0xf8,0x21,0xf0]
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%tmp1 = shl i32 %offset, 2
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%tmp2 = add i32 %base, %tmp1
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%tmp3 = inttoptr i32 %tmp2 to i8*
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tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
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ret void
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}
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declare void @llvm.prefetch(i8*, i32, i32) nounwind
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