llvm-6502/test/CodeGen/ARM/fast-isel-ret.ll

; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s

; Sign-extend of i1 currently not supported by fast-isel
;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp {
;entry:
;  ret i1 %a
;}

define zeroext i1 @ret1(i1 signext %a) nounwind uwtable ssp {
entry:
; CHECK: ret1
; CHECK: and r0, r0, #1
; CHECK: bx lr
  ret i1 %a
}

define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp {
entry:
; CHECK: ret2
; CHECK: sxtb r0, r0
; CHECK: bx lr
  ret i8 %a
}

define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp {
entry:
; CHECK: ret3
; CHECK: and r0, r0, #255
; CHECK: bx lr
  ret i8 %a
}

define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp {
entry:
; CHECK: ret4
; CHECK: sxth r0, r0
; CHECK: bx lr
  ret i16 %a
}

define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp {
entry:
; CHECK: ret5
; CHECK: uxth r0, r0
; CHECK: bx lr
  ret i16 %a
}

define i16 @ret6(i16 %a) nounwind uwtable ssp {
entry:
; CHECK: ret6
; CHECK-NOT: uxth
; CHECK-NOT: sxth
; CHECK: bx lr
  ret i16 %a
}
ARM: Clean up fast-isel machine verifier errors. Lots of machine verifier errors result from using a plain GPR regclass for incoming argument copies. A more restrictive rGPR class is more appropriate since it more accurately represents what's happening, plus it lines up better with isel later on so the verifier is happier. Reduces the number of ARM fast-isel tests not running with the verifier enabled by over half. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188592 91177308-0d34-0410-b5e6-96231b3b80d8 2013-08-16 23:37:23 +00:00			`; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs \| FileCheck %s`
			`; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs \| FileCheck %s`
ARM: Fast-isel register class constrain for extends. Properly constrain the operand register class for instructions used in [sz]ext expansion. Update more tests to use the verifier now that we're getting the register classes correct. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188594 91177308-0d34-0410-b5e6-96231b3b80d8 2013-08-16 23:37:36 +00:00			`; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs \| FileCheck %s`
Add fast-isel support for returning i1, i8, and i16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8 2011-11-04 00:50:21 +00:00
			`; Sign-extend of i1 currently not supported by fast-isel`
			`;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp {`
			`;entry:`
			`; ret i1 %a`
			`;}`

			`define zeroext i1 @ret1(i1 signext %a) nounwind uwtable ssp {`
			`entry:`
			`; CHECK: ret1`
			`; CHECK: and r0, r0, #1`
			`; CHECK: bx lr`
			`ret i1 %a`
			`}`

			`define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp {`
			`entry:`
			`; CHECK: ret2`
			`; CHECK: sxtb r0, r0`
			`; CHECK: bx lr`
			`ret i8 %a`
			`}`

			`define zeroext i8 @ret3(i8 signext %a) nounwind uwtable ssp {`
			`entry:`
			`; CHECK: ret3`
ARM FastISel integer sext/zext improvements My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8 2013-06-07 20:10:37 +00:00			`; CHECK: and r0, r0, #255`
Add fast-isel support for returning i1, i8, and i16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8 2011-11-04 00:50:21 +00:00			`; CHECK: bx lr`
			`ret i8 %a`
			`}`

			`define signext i16 @ret4(i16 signext %a) nounwind uwtable ssp {`
			`entry:`
			`; CHECK: ret4`
			`; CHECK: sxth r0, r0`
			`; CHECK: bx lr`
			`ret i16 %a`
			`}`

			`define zeroext i16 @ret5(i16 signext %a) nounwind uwtable ssp {`
			`entry:`
			`; CHECK: ret5`
			`; CHECK: uxth r0, r0`
			`; CHECK: bx lr`
			`ret i16 %a`
			`}`
[fast-isel] Add support for returning non-legal types with no sign- or zero- entend flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8 2012-02-17 01:21:28 +00:00
			`define i16 @ret6(i16 %a) nounwind uwtable ssp {`
			`entry:`
			`; CHECK: ret6`
			`; CHECK-NOT: uxth`
			`; CHECK-NOT: sxth`
			`; CHECK: bx lr`
			`ret i16 %a`
			`}`