2015-06-29 23:51:55 +00:00
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//===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file defines the WebAssembly-specific subclass of TargetMachine.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyTargetMachine.h"
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#include "WebAssemblyTargetObjectFile.h"
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#include "WebAssemblyTargetTransformInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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2015-07-01 23:41:25 +00:00
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#include "llvm/Transforms/Scalar.h"
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2015-06-29 23:51:55 +00:00
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using namespace llvm;
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#define DEBUG_TYPE "wasm"
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extern "C" void LLVMInitializeWebAssemblyTarget() {
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// Register the target.
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2015-07-01 21:42:34 +00:00
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RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32);
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RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64);
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2015-06-29 23:51:55 +00:00
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}
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//===----------------------------------------------------------------------===//
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// WebAssembly Lowering public interface.
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//===----------------------------------------------------------------------===//
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/// Create an WebAssembly architecture model.
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///
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WebAssemblyTargetMachine::WebAssemblyTargetMachine(
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const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
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const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT.isArch64Bit()
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? "e-p:64:64-i64:64-v128:8:128-n32:64-S128"
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: "e-p:32:32-i64:64-v128:8:128-n32:64-S128",
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TT, CPU, FS, Options, RM, CM, OL),
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TLOF(make_unique<WebAssemblyTargetObjectFile>()) {
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initAsmInfo();
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// We need a reducible CFG, so disable some optimizations which tend to
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// introduce irreducibility.
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setRequiresStructuredCFG(true);
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}
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WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {}
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const WebAssemblySubtarget *
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WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
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}
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return I.get();
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}
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namespace {
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/// WebAssembly Code Generator Pass Configuration Options.
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class WebAssemblyPassConfig final : public TargetPassConfig {
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public:
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WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
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return getTM<WebAssemblyTargetMachine>();
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}
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FunctionPass *createTargetRegisterAllocator(bool) override;
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void addFastRegAlloc(FunctionPass *RegAllocPass) override;
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void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
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void addIRPasses() override;
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bool addPreISel() override;
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bool addInstSelector() override;
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bool addILPOpts() override;
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void addPreRegAlloc() override;
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void addRegAllocPasses(bool Optimized);
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void addPostRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // end anonymous namespace
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TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis([this](Function &F) {
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return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
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});
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}
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TargetPassConfig *
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WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new WebAssemblyPassConfig(this, PM);
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}
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FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
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return nullptr; // No reg alloc
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}
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void WebAssemblyPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
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assert(!RegAllocPass && "WebAssembly uses no regalloc!");
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addRegAllocPasses(false);
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}
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void WebAssemblyPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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assert(!RegAllocPass && "WebAssembly uses no regalloc!");
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addRegAllocPasses(true);
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}
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//===----------------------------------------------------------------------===//
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// The following functions are called from lib/CodeGen/Passes.cpp to modify
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// the CodeGen pass sequence.
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//===----------------------------------------------------------------------===//
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void WebAssemblyPassConfig::addIRPasses() {
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2015-07-01 23:41:25 +00:00
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// FIXME: the default for this option is currently POSIX, whereas
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// WebAssembly's MVP should default to Single.
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if (TM->Options.ThreadModel == ThreadModel::Single)
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addPass(createLowerAtomicPass());
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else
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// Expand some atomic operations. WebAssemblyTargetLowering has hooks which
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// control specifically what gets lowered.
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addPass(createAtomicExpandPass(TM));
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2015-06-29 23:51:55 +00:00
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TargetPassConfig::addIRPasses();
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}
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bool WebAssemblyPassConfig::addPreISel() { return false; }
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bool WebAssemblyPassConfig::addInstSelector() {
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addPass(
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createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
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return false;
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}
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bool WebAssemblyPassConfig::addILPOpts() { return true; }
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void WebAssemblyPassConfig::addPreRegAlloc() {}
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void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {}
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void WebAssemblyPassConfig::addPostRegAlloc() {}
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void WebAssemblyPassConfig::addPreSched2() {}
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void WebAssemblyPassConfig::addPreEmitPass() {}
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