2014-01-24 22:36:53 +00:00
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon
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; Bug: i8 type in FRP8 register but not registering with register class causes segmentation fault.
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; Fix: Removed i8 type from FPR8 register class.
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define void @test_concatvector_v8i8() {
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entry.split:
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br i1 undef, label %if.then, label %if.end
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if.then: ; preds = %entry.split
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unreachable
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if.end: ; preds = %entry.split
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br i1 undef, label %if.then9, label %if.end18
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if.then9: ; preds = %if.end
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unreachable
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if.end18: ; preds = %if.end
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br label %for.body
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for.body: ; preds = %for.inc, %if.end18
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br i1 false, label %if.then30, label %for.inc
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if.then30: ; preds = %for.body
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unreachable
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for.inc: ; preds = %for.body
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br i1 undef, label %for.end, label %for.body
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for.end: ; preds = %for.inc
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br label %for.body77
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for.body77: ; preds = %for.body77, %for.end
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br i1 undef, label %for.end106, label %for.body77
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for.end106: ; preds = %for.body77
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br i1 undef, label %for.body130.us.us, label %stmt.for.body130.us.us
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stmt.for.body130.us.us: ; preds = %stmt.for.body130.us.us, %for.end106
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%_p_splat.us = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <8 x i32> zeroinitializer
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store <8 x i8> %_p_splat.us, <8 x i8>* undef, align 1
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br label %stmt.for.body130.us.us
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for.body130.us.us: ; preds = %for.body130.us.us, %for.end106
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br label %for.body130.us.us
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}
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2014-03-10 09:34:07 +00:00
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declare <1 x i16> @llvm.aarch64.neon.vuqrshrn.v1i16(<1 x i32>, i32)
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define <8 x i16> @test_splat(i32 %l) nounwind {
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; CHECK-LABEL: test_splat:
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; CHECK: ret
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%lhs = insertelement <1 x i32> undef, i32 %l, i32 0
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%shift = tail call <1 x i16> @llvm.aarch64.neon.vuqrshrn.v1i16(<1 x i32> %lhs, i32 11)
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%vec = shufflevector <1 x i16> %shift, <1 x i16> undef, <8 x i32> zeroinitializer
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ret <8 x i16> %vec
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}
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define <8 x i16> @test_notsplat(<8 x i16> %a, <8 x i16> %b, i32 %l) nounwind {
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; CHECK-LABEL: test_notsplat:
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; CHECK: ret
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entry:
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%lhs = insertelement <1 x i32> undef, i32 %l, i32 0
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%shift = tail call <1 x i16> @llvm.aarch64.neon.vuqrshrn.v1i16(<1 x i32> %lhs, i32 11)
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%vec = shufflevector <1 x i16> %shift, <1 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i16> %vec
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}
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