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llvm-6502/test/CodeGen/X86/tbm-intrinsics-x86_64.ll

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Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 18:38:42 +00:00
; RUN: llc -mtriple=x86_64-unknown-unknown -march=x86-64 -mattr=+tbm < %s | FileCheck %s
define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind readnone {
entry:
; CHECK-LABEL: test_x86_tbm_bextri_u32:
; CHECK-NOT: mov
; CHECK: bextr $
%0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %a, i32 2814)
ret i32 %0
}
declare i32 @llvm.x86.tbm.bextri.u32(i32, i32) nounwind readnone
define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind readonly {
entry:
; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
; CHECK-NOT: mov
; CHECK: bextr $
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00
%tmp1 = load i32, i32* %a, align 4
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 18:38:42 +00:00
%0 = tail call i32 @llvm.x86.tbm.bextri.u32(i32 %tmp1, i32 2814)
ret i32 %0
}
define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind readnone {
entry:
; CHECK-LABEL: test_x86_tbm_bextri_u64:
; CHECK-NOT: mov
; CHECK: bextr $
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 04:16:45 +00:00
%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %a, i64 2814)
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 18:38:42 +00:00
ret i64 %0
}
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 04:16:45 +00:00
declare i64 @llvm.x86.tbm.bextri.u64(i64, i64) nounwind readnone
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 18:38:42 +00:00
define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly {
entry:
Fix broken CHECK lines git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 07:31:05 +00:00
; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 18:38:42 +00:00
; CHECK-NOT: mov
; CHECK: bextr $
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00
%tmp1 = load i64, i64* %a, align 8
Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-03 04:16:45 +00:00
%0 = tail call i64 @llvm.x86.tbm.bextri.u64(i64 %tmp1, i64 2814)
Adding intrinsics to the llvm backend for TBM instruction set. Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-27 18:38:42 +00:00
ret i64 %0
}
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