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llvm-6502/test/CodeGen/Mips/blockaddr.ll

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Fix LowerBlockAddress to produce instructions with the correct relocation types for N32 ABI and update test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 18:22:53 +00:00
; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-O32
; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-O32
[mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler. Summary: This removes the need to coerce UnknownABI to the default ABI (O32 for MIPS32, N64 for MIPS64 [*]) in both MipsSubtarget and MipsAsmParser. Clang has been updated to disable both possible default ABI's before enabling the ABI it intends to use. [*] N64 being the default for MIPS64 is not actually correct. However N32 is not fully implemented/tested yet. Depends on: D2830 Reviewers: jacksprat, matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D2832 Differential Revision: http://llvm-reviews.chandlerc.com/D2846 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201792 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 14:58:19 +00:00
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n32 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N32
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n32 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N32
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n64 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC-N64
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=-n64,n64 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-N64
[Mips] Adjust float ABI settings in case of MIPS16 mode. Hard float for mips16 means essentially to compile as soft float but to use a runtime library for soft float that is written with native mips32 floating point instructions (those runtime routines run in mips32 hard float mode). The patch reviewed by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 12:20:17 +00:00
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-MIPS16-1
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -mattr=+mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC-MIPS16-2
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 20:01:52 +00:00
@reg = common global i8* null, align 4
define i8* @dummy(i8* %x) nounwind readnone noinline {
entry:
ret i8* %x
}
Fix LowerBlockAddress to produce instructions with the correct relocation types for N32 ABI and update test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 18:22:53 +00:00
; PIC-O32: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]])
; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]])
; PIC-O32: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]])
; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]])
; STATIC-O32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]])
; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
; STATIC-O32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]])
; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
; PIC-N32: lw $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]])
; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]])
; PIC-N32: lw $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]])
; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]])
; STATIC-N32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]])
; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
; STATIC-N32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]])
; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
; PIC-N64: ld $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]])
; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]])
; PIC-N64: ld $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]])
; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]])
; STATIC-N64: ld $[[R2:[0-9]+]], %got_page($tmp[[T2:[0-9]+]])
; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst($tmp[[T2]])
; STATIC-N64: ld $[[R3:[0-9]+]], %got_page($tmp[[T3:[0-9]+]])
; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst($tmp[[T3]])
Support tblockaddr for static compilation in Mips16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 22:01:40 +00:00
; STATIC-MIPS16-1: .ent f
; STATIC-MIPS16-2: .ent f
; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]])
; STATIC-MIPS16-1: sll ${{[0-9]+}}, $[[R1_16]], 16
; STATIC-MIPS16-2: li ${{[0-9]+}}, %lo($tmp{{[0-9]+}})
Fix broken CHECK lines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199016 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-11 21:06:00 +00:00
; STATIC-MIPS16-1: jal dummy
; STATIC-MIPS16-2: jal dummy
Support tblockaddr for static compilation in Mips16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 22:01:40 +00:00
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 20:01:52 +00:00
define void @f() nounwind {
entry:
%call = tail call i8* @dummy(i8* blockaddress(@f, %baz))
indirectbr i8* %call, [label %baz, label %foo]
foo: ; preds = %foo, %entry
store i8* blockaddress(@f, %foo), i8** @reg, align 4
br label %foo
baz: ; preds = %entry
store i8* null, i8** @reg, align 4
ret void
}
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