2013-05-07 19:53:00 +00:00
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//=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// When the compiler is invoked with no small data, for instance, with the -G0
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// command line option, then all CONST32_* opcodes should be broken down into
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// appropriate LO and HI instructions. This splitting is done by this pass.
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// The only reason this is not done in the DAG lowering itself is that there
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// is no simple way of getting the register allocator to allot the same hard
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// register to the result of LO and HI instructions. This pass is always
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// scheduled after register allocation.
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//
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//===----------------------------------------------------------------------===//
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2013-08-21 20:36:42 +00:00
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#include "HexagonMachineFunctionInfo.h"
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2014-01-07 11:48:04 +00:00
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#include "HexagonSubtarget.h"
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2014-05-21 22:42:07 +00:00
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#include "HexagonTargetMachine.h"
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#include "HexagonTargetObjectFile.h"
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2013-08-21 20:36:42 +00:00
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#include "llvm/ADT/Statistic.h"
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2013-05-07 19:53:00 +00:00
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2013-08-21 20:36:42 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2013-05-07 19:53:00 +00:00
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2013-08-21 20:36:42 +00:00
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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2013-05-07 19:53:00 +00:00
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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2013-08-21 20:36:42 +00:00
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#include "llvm/CodeGen/SchedulerRegistry.h"
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2014-01-07 11:48:04 +00:00
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#include "llvm/Support/CommandLine.h"
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2013-05-07 19:53:00 +00:00
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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2014-01-07 11:48:04 +00:00
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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2013-05-07 19:53:00 +00:00
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#include <map>
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using namespace llvm;
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2014-04-22 02:41:26 +00:00
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#define DEBUG_TYPE "xfer"
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2013-05-07 19:53:00 +00:00
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namespace {
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class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
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public:
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static char ID;
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2015-02-02 22:11:43 +00:00
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HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {}
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2013-05-07 19:53:00 +00:00
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2014-04-29 07:58:16 +00:00
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const char *getPassName() const override {
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2013-05-07 19:53:00 +00:00
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return "Hexagon Split Const32s and Const64s";
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}
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2014-04-29 07:58:16 +00:00
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bool runOnMachineFunction(MachineFunction &Fn) override;
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2013-05-07 19:53:00 +00:00
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};
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char HexagonSplitConst32AndConst64::ID = 0;
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bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
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2014-05-21 22:42:07 +00:00
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const HexagonTargetObjectFile &TLOF =
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2015-02-02 22:11:43 +00:00
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*static_cast<const HexagonTargetObjectFile *>(
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Fn.getTarget().getObjFileLowering());
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2014-05-21 22:42:07 +00:00
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if (TLOF.IsSmallDataEnabled())
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return true;
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2015-02-02 22:11:43 +00:00
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const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
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2013-05-07 19:53:00 +00:00
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
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MBBb != MBBe; ++MBBb) {
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MachineBasicBlock* MBB = MBBb;
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// Traverse the basic block
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MachineBasicBlock::iterator MII = MBB->begin();
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MachineBasicBlock::iterator MIE = MBB->end ();
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while (MII != MIE) {
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MachineInstr *MI = MII;
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int Opc = MI->getOpcode();
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if (Opc == Hexagon::CONST32_set) {
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int DestReg = MI->getOperand(0).getReg();
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MachineOperand &Symbol = MI->getOperand (1);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
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// MBB->erase returns the iterator to the next instruction, which is the
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// one we want to process next
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST32_set_jt) {
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int DestReg = MI->getOperand(0).getReg();
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MachineOperand &Symbol = MI->getOperand (1);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
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// MBB->erase returns the iterator to the next instruction, which is the
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// one we want to process next
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST32_Label) {
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int DestReg = MI->getOperand(0).getReg();
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MachineOperand &Symbol = MI->getOperand (1);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
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// MBB->erase returns the iterator to the next instruction, which is the
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// one we want to process next
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST32_Int_Real) {
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int DestReg = MI->getOperand(0).getReg();
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int64_t ImmValue = MI->getOperand(1).getImm ();
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
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MII = MBB->erase (MI);
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continue;
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}
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else if (Opc == Hexagon::CONST64_Int_Real) {
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int DestReg = MI->getOperand(0).getReg();
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int64_t ImmValue = MI->getOperand(1).getImm ();
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2015-02-02 22:11:43 +00:00
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unsigned DestLo = Fn.getSubtarget().getRegisterInfo()->getSubReg(
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2014-08-04 21:25:23 +00:00
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DestReg, Hexagon::subreg_loreg);
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2015-02-02 22:11:43 +00:00
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unsigned DestHi = Fn.getSubtarget().getRegisterInfo()->getSubReg(
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2014-08-04 21:25:23 +00:00
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DestReg, Hexagon::subreg_hireg);
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2013-05-07 19:53:00 +00:00
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int32_t LowWord = (ImmValue & 0xFFFFFFFF);
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int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
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// Lower Registers Lower Half
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
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// Lower Registers Higher Half
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
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// Higher Registers Lower Half
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
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// Higher Registers Higher Half.
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BuildMI (*MBB, MII, MI->getDebugLoc(),
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TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
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MII = MBB->erase (MI);
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continue;
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}
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++MII;
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}
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}
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return true;
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}
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}
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//===----------------------------------------------------------------------===//
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// Public Constructor Functions
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//===----------------------------------------------------------------------===//
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FunctionPass *
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2015-02-02 22:11:43 +00:00
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llvm::createHexagonSplitConst32AndConst64() {
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return new HexagonSplitConst32AndConst64();
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2013-05-07 19:53:00 +00:00
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}
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