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llvm-6502/test/CodeGen/R600/elf.ll

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R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-10 17:11:46 +00:00
; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG-CHECK %s
R600: Emit ELF formatted code rather than raw ISA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:21 +00:00
R600/SI: Emit config values in register value pairs. Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:35 +00:00
; ELF-CHECK: Format: ELF32
; ELF-CHECK: Name: .AMDGPU.config
R600: Use SHT_PROGBITS for the .AMDGPU.config section The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 23:56:14 +00:00
; ELF-CHECK: Type: SHT_PROGBITS
R600/SI: Emit config values in register value pairs. Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:35 +00:00
R600: Align functions to 256 bytes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219002 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-03 19:02:02 +00:00
; CONFIG-CHECK: .align 256
; CONFIG-CHECK: test:
R600/SI: Emit config values in register value pairs. Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:35 +00:00
; CONFIG-CHECK: .section .AMDGPU.config
; CONFIG-CHECK-NEXT: .long 45096
; CONFIG-CHECK-NEXT: .long 0
R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE We need to intialize this to something and since clang does not set the shader type attribute and clang is used only for compute shaders, initializing it to COMPUTE seems like the best choice. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 18:32:24 +00:00
define void @test(i32 %p) #0 {
R600: Emit ELF formatted code rather than raw ISA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 17:51:21 +00:00
%i = add i32 %p, 2
%r = bitcast i32 %i to float
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r)
ret void
}
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE We need to intialize this to something and since clang does not set the shader type attribute and clang is used only for compute shaders, initializing it to COMPUTE seems like the best choice. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-26 18:32:24 +00:00
attributes #0 = { "ShaderType"="0" } ; Pixel Shader
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