mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
577 lines
11 KiB
LLVM
577 lines
11 KiB
LLVM
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; Test that compares are ommitted if CC already has the right value
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; (z10 version).
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare void @foo()
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; Addition provides enough for equality comparisons with zero. First teest
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; the EQ case.
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define i32 @f1(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f1:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: je .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = add i32 %a, 1000000
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%cmp = icmp eq i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with NE.
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define i32 @f2(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f2:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: jne .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = add i32 %a, 1000000
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; SLT requires a comparison.
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define i32 @f3(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f3:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = add i32 %a, 1000000
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...SLE too.
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define i32 @f4(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f4:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: cijle %r2, 0, .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = add i32 %a, 1000000
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%cmp = icmp sle i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...SGT too.
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define i32 @f5(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f5:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: cijh %r2, 0, .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = add i32 %a, 1000000
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%cmp = icmp sgt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...SGE too.
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define i32 @f6(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f6:
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; CHECK: afi %r2, 1000000
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; CHECK-NEXT: cijhe %r2, 0, .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = add i32 %a, 1000000
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%cmp = icmp sge i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Subtraction also provides enough for equality comparisons with zero.
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define i32 @f7(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f7:
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; CHECK: s %r2, 0(%r4)
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; CHECK-NEXT: jne .L{{.*}}
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; CHECK: br %r14
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entry:
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%cur = load i32 *%dest
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%res = sub i32 %a, %cur
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...but not for ordered comparisons.
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define i32 @f8(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f8:
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; CHECK: s %r2, 0(%r4)
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; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
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; CHECK: br %r14
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entry:
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%cur = load i32 *%dest
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%res = sub i32 %a, %cur
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Logic register-register instructions also provide enough for equality
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; comparisons with zero.
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define i32 @f9(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f9:
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; CHECK: nr %r2, %r3
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = and i32 %a, %b
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...but not for ordered comparisons.
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define i32 @f10(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f10:
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; CHECK: nr %r2, %r3
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; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = and i32 %a, %b
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Logic register-immediate instructions also provide enough for equality
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; comparisons with zero if the immediate covers the whole register.
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define i32 @f11(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f11:
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; CHECK: nilf %r2, 100
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = and i32 %a, 100
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; Partial logic register-immediate instructions do not provide simple
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; zero results.
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define i32 @f12(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f12:
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; CHECK: nill %r2, 65436
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; CHECK-NEXT: cijlh %r2, 0, .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = and i32 %a, -100
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; SRA provides the same CC result as a comparison with zero.
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define i32 @f13(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f13:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: je .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp eq i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and again with NE.
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define i32 @f14(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f14:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: jlh .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp ne i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and SLT.
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define i32 @f15(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f15:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp slt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and SLE.
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define i32 @f16(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f16:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: jle .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp sle i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and SGT.
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define i32 @f17(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f17:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: jh .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp sgt i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; ...and SGE.
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define i32 @f18(i32 %a, i32 %b, i32 *%dest) {
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; CHECK-LABEL: f18:
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; CHECK: sra %r2, 0(%r3)
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; CHECK-NEXT: jhe .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = ashr i32 %a, %b
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%cmp = icmp sge i32 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i32 %b, i32 *%dest
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br label %exit
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exit:
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ret i32 %res
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}
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; RISBG provides the same result as a comparison against zero.
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; Test the EQ case.
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define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
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; CHECK-LABEL: f19:
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; CHECK: risbg %r2, %r3, 0, 190, 0
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; CHECK-NEXT: je .L{{.*}}
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; CHECK: br %r14
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entry:
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%res = and i64 %b, -2
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%cmp = icmp eq i64 %res, 0
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br i1 %cmp, label %exit, label %store
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store:
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store i64 %b, i64 *%dest
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br label %exit
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exit:
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ret i64 %res
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}
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; ...and the SLT case.
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define i64 @f20(i64 %a, i64 %b, i64 *%dest) {
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; CHECK-LABEL: f20:
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; CHECK: risbg %r2, %r3, 0, 190, 0
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; CHECK-NEXT: jl .L{{.*}}
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; CHECK: br %r14
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||
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entry:
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||
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%res = and i64 %b, -2
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%cmp = icmp slt i64 %res, 0
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||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i64 %b, i64 *%dest
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret i64 %res
|
||
|
|
}
|
||
|
|
|
||
|
|
; Test a case where the register we're testing is set by a non-CC-clobbering
|
||
|
|
; instruction.
|
||
|
|
define i32 @f21(i32 %a, i32 %b, i32 *%dest) {
|
||
|
|
; CHECK-LABEL: f21:
|
||
|
|
; CHECK: afi %r2, 1000000
|
||
|
|
; CHECK-NEXT: #APP
|
||
|
|
; CHECK-NEXT: blah %r2
|
||
|
|
; CHECK-NEXT: #NO_APP
|
||
|
|
; CHECK-NEXT: cije %r2, 0, .L{{.*}}
|
||
|
|
; CHECK: br %r14
|
||
|
|
entry:
|
||
|
|
%add = add i32 %a, 1000000
|
||
|
|
%res = call i32 asm "blah $0", "=r,0" (i32 %add)
|
||
|
|
%cmp = icmp eq i32 %res, 0
|
||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i32 %b, i32 *%dest
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret i32 %res
|
||
|
|
}
|
||
|
|
|
||
|
|
; ...and again with a CC-clobbering instruction.
|
||
|
|
define i32 @f22(i32 %a, i32 %b, i32 *%dest) {
|
||
|
|
; CHECK-LABEL: f22:
|
||
|
|
; CHECK: afi %r2, 1000000
|
||
|
|
; CHECK-NEXT: #APP
|
||
|
|
; CHECK-NEXT: blah %r2
|
||
|
|
; CHECK-NEXT: #NO_APP
|
||
|
|
; CHECK-NEXT: cije %r2, 0, .L{{.*}}
|
||
|
|
; CHECK: br %r14
|
||
|
|
entry:
|
||
|
|
%add = add i32 %a, 1000000
|
||
|
|
%res = call i32 asm "blah $0", "=r,0,~{cc}" (i32 %add)
|
||
|
|
%cmp = icmp eq i32 %res, 0
|
||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i32 %b, i32 *%dest
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret i32 %res
|
||
|
|
}
|
||
|
|
|
||
|
|
; Check that stores do not interfere.
|
||
|
|
define i32 @f23(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
|
||
|
|
; CHECK-LABEL: f23:
|
||
|
|
; CHECK: afi %r2, 1000000
|
||
|
|
; CHECK-NEXT: st %r2, 0(%r4)
|
||
|
|
; CHECK-NEXT: jne .L{{.*}}
|
||
|
|
; CHECK: br %r14
|
||
|
|
entry:
|
||
|
|
%res = add i32 %a, 1000000
|
||
|
|
store i32 %res, i32 *%dest1
|
||
|
|
%cmp = icmp ne i32 %res, 0
|
||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i32 %b, i32 *%dest2
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret i32 %res
|
||
|
|
}
|
||
|
|
|
||
|
|
; Check that calls do interfere.
|
||
|
|
define void @f24(i32 *%ptr) {
|
||
|
|
; CHECK-LABEL: f24:
|
||
|
|
; CHECK: afi [[REG:%r[0-9]+]], 1000000
|
||
|
|
; CHECK-NEXT: brasl %r14, foo@PLT
|
||
|
|
; CHECK-NEXT: cijlh [[REG]], 0, .L{{.*}}
|
||
|
|
; CHECK: br %r14
|
||
|
|
entry:
|
||
|
|
%val = load i32 *%ptr
|
||
|
|
%xor = xor i32 %val, 1
|
||
|
|
%add = add i32 %xor, 1000000
|
||
|
|
call void @foo()
|
||
|
|
%cmp = icmp ne i32 %add, 0
|
||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i32 %add, i32 *%ptr
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
; Check that inline asms don't interfere if they don't clobber CC.
|
||
|
|
define void @f25(i32 %a, i32 *%ptr) {
|
||
|
|
; CHECK-LABEL: f25:
|
||
|
|
; CHECK: afi %r2, 1000000
|
||
|
|
; CHECK-NEXT: #APP
|
||
|
|
; CHECK-NEXT: blah
|
||
|
|
; CHECK-NEXT: #NO_APP
|
||
|
|
; CHECK-NEXT: jne .L{{.*}}
|
||
|
|
; CHECK: br %r14
|
||
|
|
entry:
|
||
|
|
%add = add i32 %a, 1000000
|
||
|
|
call void asm sideeffect "blah", "r"(i32 %add)
|
||
|
|
%cmp = icmp ne i32 %add, 0
|
||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i32 %add, i32 *%ptr
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
; ...but do interfere if they do clobber CC.
|
||
|
|
define void @f26(i32 %a, i32 *%ptr) {
|
||
|
|
; CHECK-LABEL: f26:
|
||
|
|
; CHECK: afi %r2, 1000000
|
||
|
|
; CHECK-NEXT: #APP
|
||
|
|
; CHECK-NEXT: blah
|
||
|
|
; CHECK-NEXT: #NO_APP
|
||
|
|
; CHECK-NEXT: cijlh %r2, 0, .L{{.*}}
|
||
|
|
; CHECK: br %r14
|
||
|
|
entry:
|
||
|
|
%add = add i32 %a, 1000000
|
||
|
|
call void asm sideeffect "blah", "r,~{cc}"(i32 %add)
|
||
|
|
%cmp = icmp ne i32 %add, 0
|
||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i32 %add, i32 *%ptr
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
; Test a case where CC is set based on a different register from the
|
||
|
|
; compare input.
|
||
|
|
define i32 @f27(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
|
||
|
|
; CHECK-LABEL: f27:
|
||
|
|
; CHECK: afi %r2, 1000000
|
||
|
|
; CHECK-NEXT: sr %r3, %r2
|
||
|
|
; CHECK-NEXT: st %r3, 0(%r4)
|
||
|
|
; CHECK-NEXT: cije %r2, 0, .L{{.*}}
|
||
|
|
; CHECK: br %r14
|
||
|
|
entry:
|
||
|
|
%add = add i32 %a, 1000000
|
||
|
|
%sub = sub i32 %b, %add
|
||
|
|
store i32 %sub, i32 *%dest1
|
||
|
|
%cmp = icmp eq i32 %add, 0
|
||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i32 %sub, i32 *%dest2
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret i32 %add
|
||
|
|
}
|
||
|
|
|
||
|
|
; Make sure that we don't confuse a base register for a destination.
|
||
|
|
define void @f28(i64 %a, i64 *%dest) {
|
||
|
|
; CHECK-LABEL: f28:
|
||
|
|
; CHECK: xi 0(%r2), 15
|
||
|
|
; CHECK: cgije %r2, 0, .L{{.*}}
|
||
|
|
; CHECK: br %r14
|
||
|
|
entry:
|
||
|
|
%ptr = inttoptr i64 %a to i8 *
|
||
|
|
%val = load i8 *%ptr
|
||
|
|
%xor = xor i8 %val, 15
|
||
|
|
store i8 %xor, i8 *%ptr
|
||
|
|
%cmp = icmp eq i64 %a, 0
|
||
|
|
br i1 %cmp, label %exit, label %store
|
||
|
|
|
||
|
|
store:
|
||
|
|
store i64 %a, i64 *%dest
|
||
|
|
br label %exit
|
||
|
|
|
||
|
|
exit:
|
||
|
|
ret void
|
||
|
|
}
|