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https://github.com/c64scene-ar/llvm-6502.git
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19 lines
546 B
LLVM
19 lines
546 B
LLVM
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; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; Check that we generate sp floating point add in V5.
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; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}}, r{{[0-9]+}})
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define i32 @main() nounwind {
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entry:
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%a = alloca float, align 4
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%b = alloca float, align 4
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%c = alloca float, align 4
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store float 0x402ECCCCC0000000, float* %a, align 4
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store float 0x4022333340000000, float* %b, align 4
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%0 = load float* %a, align 4
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%1 = load float* %b, align 4
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%add = fadd float %0, %1
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store float %add, float* %c, align 4
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ret i32 0
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}
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