llvm-6502/test/TableGen/ifbit.td

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TableGen
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// RUN: tblgen %s | FileCheck %s
// XFAIL: vg_leak
// CHECK: a = 6
// CHECK: a = 5
class A<bit b = 1> {
int a = !if(b, 5, 6);
}
def X : A<0>;
def Y : A;