llvm-6502/test/MC/ARM/thumb2-ldrd.s

// RUN: not llvm-mc -arch thumb -mattr=+thumb2 \
// RUN: < %s >/dev/null 2> %t
// RUN: grep "error: destination operands can't be identical" %t | count 4
// rdar://14479780

ldrd r0, r0, [pc, #0]
ldrd r0, r0, [r1, #4]
ldrd r0, r0, [r1], #4
ldrd r0, r0, [r1, #4]!
ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands. LDRD<c> <Rt>, <Rt2>, <label> LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}] LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm> LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]! As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2. If this constraint is not met the result of executing the instruction will be unpredictable. Fixes rdar://14479780. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191504 91177308-0d34-0410-b5e6-96231b3b80d8 2013-09-27 10:30:18 +00:00			`// RUN: not llvm-mc -arch thumb -mattr=+thumb2 \`
			`// RUN: < %s >/dev/null 2> %t`
			`// RUN: grep "error: destination operands can't be identical" %t \| count 4`
			`// rdar://14479780`

			`ldrd r0, r0, [pc, #0]`
			`ldrd r0, r0, [r1, #4]`
			`ldrd r0, r0, [r1], #4`
			`ldrd r0, r0, [r1, #4]!`