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llvm-6502/test/MC/ARM/arm_instructions.s

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ArmAsm
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Mark ARM subtarget features that are available for the assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 16:59:54 +00:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:20 +00:00
@ CHECK: nop
fix the asmmatcher generator to handle targets with no RegisterPrefix (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:28:42 +00:00
@ CHECK: encoding: [0x00,0xf0,0x20,0xe3]
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:20 +00:00
nop
@ CHECK: nopeq
fix the asmmatcher generator to handle targets with no RegisterPrefix (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:28:42 +00:00
@ CHECK: encoding: [0x00,0xf0,0x20,0x03]
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 06:37:20 +00:00
nopeq
fix the asmmatcher generator to handle targets with no RegisterPrefix (like ARM) correctly. With this change, we can now match "bx lr" because we recognize lr as a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:28:42 +00:00
@ CHECK: bx lr
@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
bx lr
most simple arm instructions match correctly now, it looks like we're not handling [] operands though git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117607 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 21:31:07 +00:00
@ CHECK: vqdmull.s32 q8, d17, d16
@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
vqdmull.s32 q8, d17, d16
add simple support for addrmode5 operands, allowing vldr.64 to work. I have no idea if this is fully right, but it is in the right direction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 00:27:31 +00:00
@ CHECK: vldr.64 d17, [r0]
@ CHECK: encoding: [0x00,0x0b,0x10,0xed]
vldr.64 d17, [r0]
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