2013-05-17 15:23:21 +00:00
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; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600-CHECK %s
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; The earliest R600 GPUs have a slightly different encoding than the rest of
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; the VLIW4/5 GPUs.
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; EG-CHECK: @test
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2013-05-17 16:50:56 +00:00
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; EG-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]
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2013-05-17 15:23:21 +00:00
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; R600-CHECK: @test
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2013-05-17 16:50:56 +00:00
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; R600-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
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2013-05-17 15:23:21 +00:00
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2013-11-11 22:10:24 +00:00
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define void @test(<4 x float> inreg %reg0) #0 {
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2013-05-17 15:23:21 +00:00
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entry:
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2013-11-11 22:10:24 +00:00
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%r0 = extractelement <4 x float> %reg0, i32 0
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%r1 = extractelement <4 x float> %reg0, i32 1
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%r2 = fmul float %r0, %r1
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%vec = insertelement <4 x float> undef, float %r2, i32 0
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call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
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2013-05-17 15:23:21 +00:00
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ret void
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}
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2013-11-11 22:10:24 +00:00
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declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
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2013-05-17 15:23:21 +00:00
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2013-11-11 22:10:24 +00:00
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attributes #0 = { "ShaderType"="0" }
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