2011-01-11 23:53:41 +00:00
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@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s
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2011-01-12 00:19:25 +00:00
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@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \
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2013-04-12 04:06:46 +00:00
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@ RUN: llvm-readobj -s -sd -sr | FileCheck -check-prefix=OBJ %s
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2011-01-11 23:53:41 +00:00
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.syntax unified
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.text
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.globl barf
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.align 2
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.type barf,%function
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barf: @ @barf
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@ BB#0: @ %entry
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movw r0, :lower16:GOT-(.LPC0_2+8)
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This fixes one divergence between LLVM and binutils for ARM in the
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:55:25 +00:00
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movt r0, :upper16:GOT-(.LPC0_2+8)
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2011-01-11 23:53:41 +00:00
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.LPC0_2:
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2011-01-13 07:58:56 +00:00
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@ ASM: movw r0, :lower16:(GOT-(.LPC0_2+8))
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This fixes one divergence between LLVM and binutils for ARM in the
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:55:25 +00:00
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@ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8))
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2011-01-11 23:53:41 +00:00
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2011-01-12 00:19:25 +00:00
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@@ make sure that the text section fixups are sane too
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2013-04-12 04:06:46 +00:00
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@ OBJ: Section {
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@ OBJ: Name: .text
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@ OBJ-NEXT: Type: SHT_PROGBITS
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@ OBJ-NEXT: Flags [ (0x6)
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@ OBJ-NEXT: SHF_ALLOC
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@ OBJ-NEXT: SHF_EXECINSTR
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@ OBJ-NEXT: ]
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@ OBJ-NEXT: Address: 0x0
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@ OBJ-NEXT: Offset: 0x34
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@ OBJ-NEXT: Size: 8
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@ OBJ-NEXT: Link: 0
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@ OBJ-NEXT: Info: 0
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@ OBJ-NEXT: AddressAlignment: 4
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@ OBJ-NEXT: EntrySize: 0
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@ OBJ-NEXT: Relocations [
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@ OBJ-NEXT: ]
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@ OBJ-NEXT: SectionData (
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@ OBJ-NEXT: 0000: F00F0FE3 F40F4FE3
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@ OBJ-NEXT: )
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2013-05-30 03:05:14 +00:00
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@ OBJ-NEXT: }
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@ OBJ-NEXT: Section {
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@ OBJ-NEXT: Index: 2
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@ OBJ-NEXT: Name: .rel.text (1)
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@ OBJ-NEXT: Type: SHT_REL (0x9)
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@ OBJ-NEXT: Flags [ (0x0)
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@ OBJ-NEXT: ]
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@ OBJ-NEXT: Address: 0x0
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@ OBJ-NEXT: Offset: 0x22C
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@ OBJ-NEXT: Size: 16
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@ OBJ-NEXT: Link: 6
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@ OBJ-NEXT: Info: 1
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@ OBJ-NEXT: AddressAlignment: 4
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@ OBJ-NEXT: EntrySize: 8
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@ OBJ-NEXT: Relocations [
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@ OBJ-NEXT: 0x0 R_ARM_MOVW_PREL_NC
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@ OBJ-NEXT: 0x4 R_ARM_MOVT_PREL
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@ OBJ-NEXT: ]
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@ OBJ-NEXT: SectionData (
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@ OBJ-NEXT: 0000: 00000000 2D060000 04000000 2E060000 |....-...........|
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@ OBJ-NEXT: )
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@ OBJ-NEXT: }
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