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llvm-6502/test/CodeGen/Mips/alloca16.ll

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This patch is for the implementation of mips16 complex pattern addr16. Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28 06:02:37 +00:00
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@iiii = global i32 25, align 4
@jjjj = global i32 35, align 4
@kkkk = global i32 100, align 4
Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31 05:21:10 +00:00
@t = global i32 25, align 4
This patch is for the implementation of mips16 complex pattern addr16. Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28 06:02:37 +00:00
@riii = common global i32 0, align 4
@rjjj = common global i32 0, align 4
@rkkk = common global i32 0, align 4
Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31 05:21:10 +00:00
define void @temp(i32 %foo) nounwind {
entry:
%foo.addr = alloca i32, align 4
store i32 %foo, i32* %foo.addr, align 4
%0 = load i32* %foo.addr, align 4
store i32 %0, i32* @t, align 4
ret void
}
This patch is for the implementation of mips16 complex pattern addr16. Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28 06:02:37 +00:00
define void @test() nounwind {
entry:
Add the saving of S2. This is needed for some of the floating point helper functions. This can be optimized out later when the remaining parts of the helper function work is moved into the Mips16HardFloat pass. For now it forces us to use the 32 bit save/restore instructions instead of the 16 bit ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187712 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-04 23:56:53 +00:00
; 16: .frame $sp,24,$ra
; 16: save $ra, $s0, $s1, $s2, 24
This patch is for the implementation of mips16 complex pattern addr16. Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28 06:02:37 +00:00
; 16: move $16, $sp
; 16: move ${{[0-9]+}}, $sp
; 16: subu $[[REGISTER:[0-9]+]], ${{[0-9]+}}, ${{[0-9]+}}
; 16: move $sp, $[[REGISTER]]
Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31 05:21:10 +00:00
%sssi = alloca i32, align 4
%ip = alloca i32*, align 4
%sssj = alloca i32, align 4
%0 = load i32* @iiii, align 4
store i32 %0, i32* %sssi, align 4
%1 = load i32* @kkkk, align 4
%mul = mul nsw i32 %1, 100
%2 = alloca i8, i32 %mul
%3 = bitcast i8* %2 to i32*
store i32* %3, i32** %ip, align 4
%4 = load i32* @jjjj, align 4
store i32 %4, i32* %sssj, align 4
%5 = load i32* @jjjj, align 4
%6 = load i32* @iiii, align 4
%7 = load i32** %ip, align 4
%arrayidx = getelementptr inbounds i32* %7, i32 %6
store i32 %5, i32* %arrayidx, align 4
%8 = load i32* @kkkk, align 4
%9 = load i32* @jjjj, align 4
%10 = load i32** %ip, align 4
%arrayidx1 = getelementptr inbounds i32* %10, i32 %9
store i32 %8, i32* %arrayidx1, align 4
%11 = load i32* @iiii, align 4
%12 = load i32* @kkkk, align 4
%13 = load i32** %ip, align 4
%arrayidx2 = getelementptr inbounds i32* %13, i32 %12
store i32 %11, i32* %arrayidx2, align 4
%14 = load i32** %ip, align 4
%arrayidx3 = getelementptr inbounds i32* %14, i32 25
%15 = load i32* %arrayidx3, align 4
store i32 %15, i32* @riii, align 4
%16 = load i32** %ip, align 4
%arrayidx4 = getelementptr inbounds i32* %16, i32 35
%17 = load i32* %arrayidx4, align 4
store i32 %17, i32* @rjjj, align 4
%18 = load i32** %ip, align 4
%arrayidx5 = getelementptr inbounds i32* %18, i32 100
%19 = load i32* %arrayidx5, align 4
store i32 %19, i32* @rkkk, align 4
%20 = load i32* @t, align 4
%21 = load i32** %ip, align 4
%arrayidx6 = getelementptr inbounds i32* %21, i32 %20
%22 = load i32* %arrayidx6, align 4
fix most of remaining issues with large frames. these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:07:42 +00:00
; 16: addiu $sp, -16
Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31 05:21:10 +00:00
call void @temp(i32 %22)
fix most of remaining issues with large frames. these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:07:42 +00:00
; 16: addiu $sp, 16
This patch is for the implementation of mips16 complex pattern addr16. Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28 06:02:37 +00:00
ret void
}
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