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76 lines
2.6 KiB
TableGen
76 lines
2.6 KiB
TableGen
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//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// SystemZ supported processors
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"z10", []>;
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//===----------------------------------------------------------------------===//
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// Register file description
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//===----------------------------------------------------------------------===//
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include "SystemZRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Calling convention description
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//===----------------------------------------------------------------------===//
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include "SystemZCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction descriptions
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//===----------------------------------------------------------------------===//
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include "SystemZOperators.td"
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include "SystemZOperands.td"
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include "SystemZPatterns.td"
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include "SystemZInstrFormats.td"
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include "SystemZInstrInfo.td"
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include "SystemZInstrFP.td"
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def SystemZInstrInfo : InstrInfo {}
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//===----------------------------------------------------------------------===//
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// Assembly parser
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//===----------------------------------------------------------------------===//
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def SystemZAsmParser : AsmParser {
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let ShouldEmitMatchRegisterName = 0;
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}
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//===----------------------------------------------------------------------===//
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// Assembly writer
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//===----------------------------------------------------------------------===//
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def SystemZAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Top-level target declaration
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//===----------------------------------------------------------------------===//
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def SystemZ : Target {
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let InstructionSet = SystemZInstrInfo;
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let AssemblyParsers = [SystemZAsmParser];
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let AssemblyWriters = [SystemZAsmWriter];
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}
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