llvm-6502/test/CodeGen/Blackfin/cmp64.ll

; RUN: llc < %s -march=bfin

; This test tries to use a JustCC register as a data operand for MOVEcc.  It
; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to
; D.  The proper solution would be to restrict the virtual register to D only.

define i32 @main() {
entry:
	br label %loopentry

loopentry:
	%done = icmp sle i64 undef, 5
	br i1 %done, label %loopentry, label %exit.1

exit.1:
	ret i32 0
}
Eliminate more uses of llvm-as and llvm-dis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8 2009-09-09 00:09:15 +00:00			`; RUN: llc < %s -march=bfin`
Analog Devices Blackfin back-end. Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8 2009-08-02 17:32:10 +00:00
			`; This test tries to use a JustCC register as a data operand for MOVEcc. It`
			`; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to`
			`; D. The proper solution would be to restrict the virtual register to D only.`

			`define i32 @main() {`
			`entry:`
			`br label %loopentry`

			`loopentry:`
			`%done = icmp sle i64 undef, 5`
			`br i1 %done, label %loopentry, label %exit.1`

			`exit.1:`
			`ret i32 0`
			`}`