2014-07-15 20:18:31 +00:00
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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2012-12-11 21:25:42 +00:00
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2013-08-01 15:23:42 +00:00
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; These tests check that fdiv is expanded correctly and also test that the
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; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate
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; instruction groups.
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2012-12-11 21:25:42 +00:00
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2014-10-01 17:15:17 +00:00
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; FUNC-LABEL: {{^}}fdiv_f32:
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2014-07-15 20:18:31 +00:00
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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2014-11-05 14:50:53 +00:00
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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2014-07-15 20:18:31 +00:00
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define void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) {
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entry:
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%0 = fdiv float %a, %b
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store float %0, float addrspace(1)* %out
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ret void
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}
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2014-10-01 17:15:17 +00:00
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; FUNC-LABEL: {{^}}fdiv_v2f32:
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2014-07-15 20:18:31 +00:00
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
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2014-11-05 14:50:53 +00:00
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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2013-08-01 15:23:42 +00:00
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define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
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2013-07-23 01:48:18 +00:00
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entry:
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2013-08-01 15:23:42 +00:00
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%0 = fdiv <2 x float> %a, %b
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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2014-10-01 17:15:17 +00:00
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; FUNC-LABEL: {{^}}fdiv_v4f32:
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2014-07-15 20:18:31 +00:00
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
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2014-11-05 14:50:53 +00:00
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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; SI-DAG: v_rcp_f32
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; SI-DAG: v_mul_f32
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2013-08-01 15:23:42 +00:00
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define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
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%a = load <4 x float> addrspace(1) * %in
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%b = load <4 x float> addrspace(1) * %b_ptr
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%result = fdiv <4 x float> %a, %b
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store <4 x float> %result, <4 x float> addrspace(1)* %out
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2012-12-11 21:25:42 +00:00
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ret void
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}
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