2014-06-19 01:19:19 +00:00
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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2014-09-26 17:55:11 +00:00
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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2014-06-23 18:28:28 +00:00
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declare { float, i1 } @llvm.AMDGPU.div.scale.f32(float, float, i1) nounwind readnone
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declare { double, i1 } @llvm.AMDGPU.div.scale.f64(double, double, i1) nounwind readnone
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2014-06-19 01:19:19 +00:00
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2014-06-23 18:28:28 +00:00
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; SI-LABEL @test_div_scale_f32_1:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%a = load float addrspace(1)* %gep.0, align 4
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%b = load float addrspace(1)* %gep.1, align 4
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2014-06-23 18:28:28 +00:00
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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2014-06-19 01:19:19 +00:00
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ret void
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}
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2014-06-23 18:28:28 +00:00
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; SI-LABEL @test_div_scale_f32_2:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%a = load float addrspace(1)* %gep.0, align 4
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%b = load float addrspace(1)* %gep.1, align 4
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2014-06-23 18:28:28 +00:00
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f64_1:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
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%a = load double addrspace(1)* %gep.0, align 8
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%b = load double addrspace(1)* %gep.1, align 8
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2014-06-23 18:28:28 +00:00
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_1:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x8
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr double addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr double addrspace(1)* %gep.0, i32 1
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%a = load double addrspace(1)* %gep.0, align 8
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%b = load double addrspace(1)* %gep.1, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f32_scalar_num_1:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]]
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; SI-DAG: s_load_dword [[A:s[0-9]+]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr float addrspace(1)* %in, i32 %tid
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%b = load float addrspace(1)* %gep, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_scalar_num_2:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]]
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; SI-DAG: s_load_dword [[A:s[0-9]+]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr float addrspace(1)* %in, i32 %tid
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%b = load float addrspace(1)* %gep, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_scalar_den_1:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]]
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; SI-DAG: s_load_dword [[B:s[0-9]+]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr float addrspace(1)* %in, i32 %tid
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%a = load float addrspace(1)* %gep, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_scalar_den_2:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]]
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; SI-DAG: s_load_dword [[B:s[0-9]+]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr float addrspace(1)* %in, i32 %tid
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%a = load float addrspace(1)* %gep, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f64_scalar_num_1:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]
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; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr double addrspace(1)* %in, i32 %tid
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%b = load double addrspace(1)* %gep, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_scalar_num_2:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr double addrspace(1)* %in, i32 %tid
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%b = load double addrspace(1)* %gep, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_scalar_den_1:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
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; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr double addrspace(1)* %in, i32 %tid
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%a = load double addrspace(1)* %gep, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_scalar_den_2:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
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; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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; SI: buffer_store_dwordx2 [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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define void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr double addrspace(1)* %in, i32 %tid
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%a = load double addrspace(1)* %gep, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f32_all_scalar_1:
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2014-11-05 14:50:53 +00:00
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; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
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; SI: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]]
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; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]]
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; SI: buffer_store_dword [[RESULT0]]
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; SI: s_endpgm
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2014-09-26 17:55:11 +00:00
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|
|
define void @test_div_scale_f32_all_scalar_1(float addrspace(1)* %out, float %a, float %b) nounwind {
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
|
|
|
|
store float %result0, float addrspace(1)* %out, align 4
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
; SI-LABEL @test_div_scale_f32_all_scalar_2:
|
2014-11-05 14:50:53 +00:00
|
|
|
; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
|
|
|
; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc
|
|
|
|
; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
|
|
|
|
; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]]
|
|
|
|
; SI: buffer_store_dword [[RESULT0]]
|
|
|
|
; SI: s_endpgm
|
2014-09-26 17:55:11 +00:00
|
|
|
define void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, float %a, float %b) nounwind {
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|
|
|
%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
|
|
|
|
%result0 = extractvalue { float, i1 } %result, 0
|
|
|
|
store float %result0, float addrspace(1)* %out, align 4
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
; SI-LABEL @test_div_scale_f64_all_scalar_1:
|
2014-11-05 14:50:53 +00:00
|
|
|
; SI-DAG: s_load_dwordx2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
|
|
|
; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
|
|
|
|
; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]]
|
|
|
|
; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]]
|
|
|
|
; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}}
|
|
|
|
; SI: buffer_store_dwordx2 [[RESULT0]]
|
|
|
|
; SI: s_endpgm
|
2014-09-26 17:55:11 +00:00
|
|
|
define void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, double %a, double %b) nounwind {
|
|
|
|
%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
|
|
|
|
%result0 = extractvalue { double, i1 } %result, 0
|
|
|
|
store double %result0, double addrspace(1)* %out, align 8
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
; SI-LABEL @test_div_scale_f64_all_scalar_2:
|
2014-11-05 14:50:53 +00:00
|
|
|
; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
|
|
|
|
; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd
|
|
|
|
; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]]
|
|
|
|
; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]]
|
|
|
|
; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]]
|
|
|
|
; SI: buffer_store_dwordx2 [[RESULT0]]
|
|
|
|
; SI: s_endpgm
|
2014-09-26 17:55:11 +00:00
|
|
|
define void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, double %a, double %b) nounwind {
|
2014-06-23 18:28:28 +00:00
|
|
|
%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
|
|
|
|
%result0 = extractvalue { double, i1 } %result, 0
|
|
|
|
store double %result0, double addrspace(1)* %out, align 8
|
2014-06-19 01:19:19 +00:00
|
|
|
ret void
|
|
|
|
}
|