llvm-6502/test/CodeGen/Thumb2/thumb2-barrier.ll

; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s

declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1)

define void @t_st() {
; CHECK: t_st:
; CHECK: dmb st
  call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 true)
  ret void
}

define void @t_sy() {
; CHECK: t_sy:
; CHECK: dmb sy
  call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 true)
  ret void
}

define void @t_ishst() {
; CHECK: t_ishst:
; CHECK: dmb ishst
  call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 false)
  ret void
}

define void @t_ish() {
; CHECK: t_ish:
; CHECK: dmb ish
  call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 false)
  ret void
}
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:22:01 +00:00			`; RUN: llc < %s -march=thumb -mcpu=cortex-a8 \| FileCheck %s`

Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-30 00:54:37 +00:00			`declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1)`
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:22:01 +00:00
Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-30 00:54:37 +00:00			`define void @t_st() {`
			`; CHECK: t_st:`
			`; CHECK: dmb st`
			`call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 true)`
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:22:01 +00:00			`ret void`
			`}`

Overhaul memory barriers in the ARM backend. Radar 8601999. There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8 2010-10-30 00:54:37 +00:00			`define void @t_sy() {`
			`; CHECK: t_sy:`
			`; CHECK: dmb sy`
			`call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 true)`
			`ret void`
			`}`

			`define void @t_ishst() {`
			`; CHECK: t_ishst:`
			`; CHECK: dmb ishst`
			`call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 false)`
			`ret void`
			`}`

			`define void @t_ish() {`
			`; CHECK: t_ish:`
			`; CHECK: dmb ish`
			`call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 false)`
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8 2010-08-11 06:22:01 +00:00			`ret void`
			`}`